am 9222d911: am c8518616: am 02f68c4b: am 4800e20e: Merge "system/core: rename aarch64 target to arm64"
* commit '9222d911a89d30a9b0537e8cdb95401be3a4999e': system/core: rename aarch64 target to arm64
This commit is contained in:
Colin Cross
Android Git Automerger
commit
892af2303f
24 changed files with 177 additions and 177 deletions
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@ -44,7 +44,7 @@ extern "C" {
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#endif
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#if defined(__aarch64__)
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#include <cutils/atomic-aarch64.h>
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#include <cutils/atomic-arm64.h>
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#elif defined(__arm__)
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#include <cutils/atomic-arm.h>
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#elif defined(__i386__) || defined(__x86_64__)
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@ -148,10 +148,10 @@ LOCAL_CFLAGS += \
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-DGTEST_OS_LINUX_ANDROID \
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-DGTEST_HAS_STD_STRING \
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ifeq ($(TARGET_ARCH),aarch64)
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ifeq ($(TARGET_ARCH),arm64)
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$(info TODO: $(LOCAL_PATH)/Android.mk -fstack-protector not yet available for the AArch64 toolchain)
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LOCAL_CFLAGS += -fno-stack-protector
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endif # aarch64
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endif # arm64
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LOCAL_CONLYFLAGS += \
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$(common_conlyflags) \
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@ -52,11 +52,11 @@ endif
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LOCAL_SHARED_LIBRARIES := libcutils liblog
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ifeq ($(TARGET_ARCH),aarch64)
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PIXELFLINGER_SRC_FILES += arch-aarch64/t32cb16blend.S
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PIXELFLINGER_SRC_FILES += arch-aarch64/col32cb16blend.S
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PIXELFLINGER_SRC_FILES += codeflinger/Aarch64Assembler.cpp
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PIXELFLINGER_SRC_FILES += codeflinger/Aarch64Disassembler.cpp
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ifeq ($(TARGET_ARCH),arm64)
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PIXELFLINGER_SRC_FILES += arch-arm64/t32cb16blend.S
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PIXELFLINGER_SRC_FILES += arch-arm64/col32cb16blend.S
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PIXELFLINGER_SRC_FILES += codeflinger/Arm64Assembler.cpp
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PIXELFLINGER_SRC_FILES += codeflinger/Arm64Disassembler.cpp
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PIXELFLINGER_CFLAGS += -fstrict-aliasing -fomit-frame-pointer
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endif
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@ -28,7 +28,7 @@
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.text
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.align
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.global scanline_col32cb16blend_aarch64
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.global scanline_col32cb16blend_arm64
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//
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// This function alpha blends a fixed color into a destination scanline, using
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@ -46,7 +46,7 @@
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// w2 = count
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scanline_col32cb16blend_aarch64:
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scanline_col32cb16blend_arm64:
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lsr w5, w1, #24 // shift down alpha
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mov w9, #0xff // create mask
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@ -28,7 +28,7 @@
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.text
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.align
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.global scanline_t32cb16blend_aarch64
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.global scanline_t32cb16blend_arm64
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/*
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* .macro pixel
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@ -155,7 +155,7 @@
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// w12: scratch
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// w14: pixel
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scanline_t32cb16blend_aarch64:
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scanline_t32cb16blend_arm64:
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// align DST to 32 bits
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tst x0, #0x3
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@ -63,7 +63,7 @@ public:
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};
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enum {
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CODEGEN_ARCH_ARM = 1, CODEGEN_ARCH_MIPS, CODEGEN_ARCH_AARCH64
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CODEGEN_ARCH_ARM = 1, CODEGEN_ARCH_MIPS, CODEGEN_ARCH_ARM64
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};
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// -----------------------------------------------------------------------
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@ -26,7 +26,7 @@
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* SUCH DAMAGE.
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*/
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#define LOG_TAG "ArmToAarch64Assembler"
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#define LOG_TAG "ArmToArm64Assembler"
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#include <stdio.h>
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#include <stdlib.h>
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@ -36,45 +36,45 @@
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#include <cutils/properties.h>
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#include <private/pixelflinger/ggl_context.h>
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#include "codeflinger/Aarch64Assembler.h"
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#include "codeflinger/Arm64Assembler.h"
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#include "codeflinger/CodeCache.h"
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#include "codeflinger/Aarch64Disassembler.h"
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#include "codeflinger/Arm64Disassembler.h"
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/*
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** --------------------------------------------
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** Support for Aarch64 in GGLAssembler JIT
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** Support for Arm64 in GGLAssembler JIT
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** --------------------------------------------
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**
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** Approach
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** - GGLAssembler and associated files are largely un-changed.
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** - A translator class maps ArmAssemblerInterface calls to
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** generate AArch64 instructions.
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** generate Arm64 instructions.
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**
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** ----------------------
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** ArmToAarch64Assembler
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** ArmToArm64Assembler
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** ----------------------
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**
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** - Subclassed from ArmAssemblerInterface
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**
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** - Translates each ArmAssemblerInterface call to generate
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** one or more Aarch64 instructions as necessary.
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** one or more Arm64 instructions as necessary.
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**
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** - Does not implement ArmAssemblerInterface portions unused by GGLAssembler
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** It calls NOT_IMPLEMENTED() for such cases, which in turn logs
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** a fatal message.
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**
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** - Uses A64_.. series of functions to generate instruction machine code
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** for Aarch64 instructions. These functions also log the instruction
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** to LOG, if AARCH64_ASM_DEBUG define is set to 1
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** for Arm64 instructions. These functions also log the instruction
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** to LOG, if ARM64_ASM_DEBUG define is set to 1
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**
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** - Dumps machine code and eqvt assembly if "debug.pf.disasm" option is set
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** It uses aarch64_disassemble to perform disassembly
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** It uses arm64_disassemble to perform disassembly
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**
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** - Uses register 13 (SP in ARM), 15 (PC in ARM), 16, 17 for storing
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** intermediate results. GGLAssembler does not use SP and PC as these
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** registers are marked as reserved. The temporary registers are not
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** saved/restored on stack as these are caller-saved registers in Aarch64
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** saved/restored on stack as these are caller-saved registers in Arm64
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**
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** - Uses CSEL instruction to support conditional execution. The result is
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** stored in a temporary register and then copied to the target register
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@ -89,10 +89,10 @@
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** move immediate instructions followed by register-register instruction.
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**
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** --------------------------------------------
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** ArmToAarch64Assembler unit test bench
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** ArmToArm64Assembler unit test bench
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** --------------------------------------------
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**
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** - Tests ArmToAarch64Assembler interface for all the possible
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** - Tests ArmToArm64Assembler interface for all the possible
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** ways in which GGLAssembler uses ArmAssemblerInterface interface.
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**
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** - Uses test jacket (written in assembly) to set the registers,
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@ -105,10 +105,10 @@
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** (ii) data transfer tests and (iii) LDM/STM tests.
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**
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** ----------------------
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** Aarch64 disassembler
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** Arm64 disassembler
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** ----------------------
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** - This disassembler disassembles only those machine codes which can be
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** generated by ArmToAarch64Assembler. It has a unit testbench which
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** generated by ArmToArm64Assembler. It has a unit testbench which
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** tests all the instructions supported by the disassembler.
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**
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** ------------------------------------------------------------------
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@ -122,13 +122,13 @@
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** These are ADDR_LDR, ADDR_STR, ADDR_ADD, ADDR_SUB and they map to
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** default 32 bit implementations in ARMAssemblerInterface.
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**
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** - ArmToAarch64Assembler maps these functions to appropriate 64 bit
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** - ArmToArm64Assembler maps these functions to appropriate 64 bit
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** functions.
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**
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** ----------------------
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** GGLAssembler changes
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** ----------------------
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** - Since ArmToAarch64Assembler can generate 4 Aarch64 instructions for
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** - Since ArmToArm64Assembler can generate 4 Arm64 instructions for
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** each call in worst case, the memory required is set to 4 times
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** ARM memory
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**
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@ -140,9 +140,9 @@
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#define NOT_IMPLEMENTED() LOG_FATAL("Arm instruction %s not yet implemented\n", __func__)
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#define AARCH64_ASM_DEBUG 0
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#define ARM64_ASM_DEBUG 0
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#if AARCH64_ASM_DEBUG
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#if ARM64_ASM_DEBUG
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#define LOG_INSTR(...) ALOGD("\t" __VA_ARGS__)
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#define LOG_LABEL(...) ALOGD(__VA_ARGS__)
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#else
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@ -163,7 +163,7 @@ static const char *cc_codes[] =
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"GE", "LT", "GT", "LE", "AL", "NV"
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};
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ArmToAarch64Assembler::ArmToAarch64Assembler(const sp<Assembly>& assembly)
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ArmToArm64Assembler::ArmToArm64Assembler(const sp<Assembly>& assembly)
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: ARMAssemblerInterface(),
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mAssembly(assembly)
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{
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@ -175,7 +175,7 @@ ArmToAarch64Assembler::ArmToAarch64Assembler(const sp<Assembly>& assembly)
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mTmpReg3 = 17;
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}
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ArmToAarch64Assembler::ArmToAarch64Assembler(void *base)
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ArmToArm64Assembler::ArmToArm64Assembler(void *base)
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: ARMAssemblerInterface(), mAssembly(NULL)
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{
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mBase = mPC = (uint32_t *)base;
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@ -187,21 +187,21 @@ ArmToAarch64Assembler::ArmToAarch64Assembler(void *base)
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mTmpReg3 = 17;
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}
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ArmToAarch64Assembler::~ArmToAarch64Assembler()
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ArmToArm64Assembler::~ArmToArm64Assembler()
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{
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}
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uint32_t* ArmToAarch64Assembler::pc() const
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uint32_t* ArmToArm64Assembler::pc() const
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{
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return mPC;
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}
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uint32_t* ArmToAarch64Assembler::base() const
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uint32_t* ArmToArm64Assembler::base() const
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{
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return mBase;
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}
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void ArmToAarch64Assembler::reset()
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void ArmToArm64Assembler::reset()
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{
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if(mAssembly == NULL)
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mPC = mBase;
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@ -211,19 +211,19 @@ void ArmToAarch64Assembler::reset()
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mLabels.clear();
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mLabelsInverseMapping.clear();
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mComments.clear();
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#if AARCH64_ASM_DEBUG
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#if ARM64_ASM_DEBUG
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ALOGI("RESET\n");
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#endif
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}
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int ArmToAarch64Assembler::getCodegenArch()
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int ArmToArm64Assembler::getCodegenArch()
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{
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return CODEGEN_ARCH_AARCH64;
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return CODEGEN_ARCH_ARM64;
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}
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// ----------------------------------------------------------------------------
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void ArmToAarch64Assembler::disassemble(const char* name)
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void ArmToArm64Assembler::disassemble(const char* name)
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{
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if(name)
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{
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@ -246,34 +246,34 @@ void ArmToAarch64Assembler::disassemble(const char* name)
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printf("%p: %08x ", i, uint32_t(i[0]));
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{
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char instr[256];
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::aarch64_disassemble(*i, instr);
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::arm64_disassemble(*i, instr);
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printf("%s\n", instr);
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}
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i++;
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}
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}
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void ArmToAarch64Assembler::comment(const char* string)
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void ArmToArm64Assembler::comment(const char* string)
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{
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mComments.add(mPC, string);
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LOG_INSTR("//%s\n", string);
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}
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void ArmToAarch64Assembler::label(const char* theLabel)
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void ArmToArm64Assembler::label(const char* theLabel)
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{
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mLabels.add(theLabel, mPC);
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mLabelsInverseMapping.add(mPC, theLabel);
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LOG_LABEL("%s:\n", theLabel);
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}
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void ArmToAarch64Assembler::B(int cc, const char* label)
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void ArmToArm64Assembler::B(int cc, const char* label)
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{
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mBranchTargets.add(branch_target_t(label, mPC));
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LOG_INSTR("B%s %s\n", cc_codes[cc], label );
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*mPC++ = (0x54 << 24) | cc;
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}
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void ArmToAarch64Assembler::BL(int cc, const char* label)
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void ArmToArm64Assembler::BL(int cc, const char* label)
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{
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NOT_IMPLEMENTED(); //Not Required
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}
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@ -282,21 +282,21 @@ void ArmToAarch64Assembler::BL(int cc, const char* label)
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//Prolog/Epilog & Generate...
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// ----------------------------------------------------------------------------
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void ArmToAarch64Assembler::prolog()
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void ArmToArm64Assembler::prolog()
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{
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// write prolog code
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mPrologPC = mPC;
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*mPC++ = A64_MOVZ_X(mZeroReg,0,0);
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}
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void ArmToAarch64Assembler::epilog(uint32_t touched)
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void ArmToArm64Assembler::epilog(uint32_t touched)
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{
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// write epilog code
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static const int XLR = 30;
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*mPC++ = A64_RET(XLR);
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}
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int ArmToAarch64Assembler::generate(const char* name)
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int ArmToArm64Assembler::generate(const char* name)
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{
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// fixup all the branches
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size_t count = mBranchTargets.size();
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@ -329,7 +329,7 @@ int ArmToAarch64Assembler::generate(const char* name)
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return NO_ERROR;
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}
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uint32_t* ArmToAarch64Assembler::pcForLabel(const char* label)
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uint32_t* ArmToArm64Assembler::pcForLabel(const char* label)
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{
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return mLabels.valueFor(label);
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}
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@ -337,7 +337,7 @@ uint32_t* ArmToAarch64Assembler::pcForLabel(const char* label)
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// ----------------------------------------------------------------------------
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// Data Processing...
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// ----------------------------------------------------------------------------
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void ArmToAarch64Assembler::dataProcessingCommon(int opcode,
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void ArmToArm64Assembler::dataProcessingCommon(int opcode,
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int s, int Rd, int Rn, uint32_t Op2)
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{
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if(opcode != opSUB && s == 1)
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@ -405,7 +405,7 @@ void ArmToAarch64Assembler::dataProcessingCommon(int opcode,
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}
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}
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void ArmToAarch64Assembler::dataProcessing(int opcode, int cc,
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void ArmToArm64Assembler::dataProcessing(int opcode, int cc,
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int s, int Rd, int Rn, uint32_t Op2)
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{
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uint32_t Wd;
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@ -460,7 +460,7 @@ void ArmToAarch64Assembler::dataProcessing(int opcode, int cc,
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// Address Processing...
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// ----------------------------------------------------------------------------
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void ArmToAarch64Assembler::ADDR_ADD(int cc,
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void ArmToArm64Assembler::ADDR_ADD(int cc,
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int s, int Rd, int Rn, uint32_t Op2)
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{
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if(cc != AL){ NOT_IMPLEMENTED(); return;} //Not required
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@ -495,7 +495,7 @@ void ArmToAarch64Assembler::ADDR_ADD(int cc,
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}
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}
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void ArmToAarch64Assembler::ADDR_SUB(int cc,
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void ArmToArm64Assembler::ADDR_SUB(int cc,
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int s, int Rd, int Rn, uint32_t Op2)
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{
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if(cc != AL){ NOT_IMPLEMENTED(); return;} //Not required
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@ -516,7 +516,7 @@ void ArmToAarch64Assembler::ADDR_SUB(int cc,
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// ----------------------------------------------------------------------------
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// multiply...
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// ----------------------------------------------------------------------------
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void ArmToAarch64Assembler::MLA(int cc, int s,int Rd, int Rm, int Rs, int Rn)
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void ArmToArm64Assembler::MLA(int cc, int s,int Rd, int Rm, int Rs, int Rn)
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{
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if(cc != AL){ NOT_IMPLEMENTED(); return;} //Not required
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|
@ -524,28 +524,28 @@ void ArmToAarch64Assembler::MLA(int cc, int s,int Rd, int Rm, int Rs, int Rn)
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if(s == 1)
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dataProcessingCommon(opSUB, 1, mTmpReg1, Rd, mZeroReg);
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}
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void ArmToAarch64Assembler::MUL(int cc, int s, int Rd, int Rm, int Rs)
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void ArmToArm64Assembler::MUL(int cc, int s, int Rd, int Rm, int Rs)
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{
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if(cc != AL){ NOT_IMPLEMENTED(); return;} //Not required
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if(s != 0) { NOT_IMPLEMENTED(); return;} //Not required
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*mPC++ = A64_MADD_W(Rd, Rm, Rs, mZeroReg);
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}
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void ArmToAarch64Assembler::UMULL(int cc, int s,
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void ArmToArm64Assembler::UMULL(int cc, int s,
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int RdLo, int RdHi, int Rm, int Rs)
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{
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NOT_IMPLEMENTED(); //Not required
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}
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void ArmToAarch64Assembler::UMUAL(int cc, int s,
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void ArmToArm64Assembler::UMUAL(int cc, int s,
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int RdLo, int RdHi, int Rm, int Rs)
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{
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NOT_IMPLEMENTED(); //Not required
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}
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void ArmToAarch64Assembler::SMULL(int cc, int s,
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void ArmToArm64Assembler::SMULL(int cc, int s,
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int RdLo, int RdHi, int Rm, int Rs)
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{
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NOT_IMPLEMENTED(); //Not required
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}
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void ArmToAarch64Assembler::SMUAL(int cc, int s,
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void ArmToArm64Assembler::SMUAL(int cc, int s,
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int RdLo, int RdHi, int Rm, int Rs)
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{
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NOT_IMPLEMENTED(); //Not required
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||||
|
|
@ -554,15 +554,15 @@ void ArmToAarch64Assembler::SMUAL(int cc, int s,
|
|||
// ----------------------------------------------------------------------------
|
||||
// branches relative to PC...
|
||||
// ----------------------------------------------------------------------------
|
||||
void ArmToAarch64Assembler::B(int cc, uint32_t* pc){
|
||||
void ArmToArm64Assembler::B(int cc, uint32_t* pc){
|
||||
NOT_IMPLEMENTED(); //Not required
|
||||
}
|
||||
|
||||
void ArmToAarch64Assembler::BL(int cc, uint32_t* pc){
|
||||
void ArmToArm64Assembler::BL(int cc, uint32_t* pc){
|
||||
NOT_IMPLEMENTED(); //Not required
|
||||
}
|
||||
|
||||
void ArmToAarch64Assembler::BX(int cc, int Rn){
|
||||
void ArmToArm64Assembler::BX(int cc, int Rn){
|
||||
NOT_IMPLEMENTED(); //Not required
|
||||
}
|
||||
|
||||
|
|
@ -574,7 +574,7 @@ enum dataTransferOp
|
|||
opLDR,opLDRB,opLDRH,opSTR,opSTRB,opSTRH
|
||||
};
|
||||
|
||||
void ArmToAarch64Assembler::dataTransfer(int op, int cc,
|
||||
void ArmToArm64Assembler::dataTransfer(int op, int cc,
|
||||
int Rd, int Rn, uint32_t op_type, uint32_t size)
|
||||
{
|
||||
const int XSP = 31;
|
||||
|
|
@ -631,46 +631,46 @@ void ArmToAarch64Assembler::dataTransfer(int op, int cc,
|
|||
return;
|
||||
|
||||
}
|
||||
void ArmToAarch64Assembler::ADDR_LDR(int cc, int Rd, int Rn, uint32_t op_type)
|
||||
void ArmToArm64Assembler::ADDR_LDR(int cc, int Rd, int Rn, uint32_t op_type)
|
||||
{
|
||||
return dataTransfer(opLDR, cc, Rd, Rn, op_type, 64);
|
||||
}
|
||||
void ArmToAarch64Assembler::ADDR_STR(int cc, int Rd, int Rn, uint32_t op_type)
|
||||
void ArmToArm64Assembler::ADDR_STR(int cc, int Rd, int Rn, uint32_t op_type)
|
||||
{
|
||||
return dataTransfer(opSTR, cc, Rd, Rn, op_type, 64);
|
||||
}
|
||||
void ArmToAarch64Assembler::LDR(int cc, int Rd, int Rn, uint32_t op_type)
|
||||
void ArmToArm64Assembler::LDR(int cc, int Rd, int Rn, uint32_t op_type)
|
||||
{
|
||||
return dataTransfer(opLDR, cc, Rd, Rn, op_type);
|
||||
}
|
||||
void ArmToAarch64Assembler::LDRB(int cc, int Rd, int Rn, uint32_t op_type)
|
||||
void ArmToArm64Assembler::LDRB(int cc, int Rd, int Rn, uint32_t op_type)
|
||||
{
|
||||
return dataTransfer(opLDRB, cc, Rd, Rn, op_type);
|
||||
}
|
||||
void ArmToAarch64Assembler::STR(int cc, int Rd, int Rn, uint32_t op_type)
|
||||
void ArmToArm64Assembler::STR(int cc, int Rd, int Rn, uint32_t op_type)
|
||||
{
|
||||
return dataTransfer(opSTR, cc, Rd, Rn, op_type);
|
||||
}
|
||||
|
||||
void ArmToAarch64Assembler::STRB(int cc, int Rd, int Rn, uint32_t op_type)
|
||||
void ArmToArm64Assembler::STRB(int cc, int Rd, int Rn, uint32_t op_type)
|
||||
{
|
||||
return dataTransfer(opSTRB, cc, Rd, Rn, op_type);
|
||||
}
|
||||
|
||||
void ArmToAarch64Assembler::LDRH(int cc, int Rd, int Rn, uint32_t op_type)
|
||||
void ArmToArm64Assembler::LDRH(int cc, int Rd, int Rn, uint32_t op_type)
|
||||
{
|
||||
return dataTransfer(opLDRH, cc, Rd, Rn, op_type);
|
||||
}
|
||||
void ArmToAarch64Assembler::LDRSB(int cc, int Rd, int Rn, uint32_t offset)
|
||||
void ArmToArm64Assembler::LDRSB(int cc, int Rd, int Rn, uint32_t offset)
|
||||
{
|
||||
NOT_IMPLEMENTED(); //Not required
|
||||
}
|
||||
void ArmToAarch64Assembler::LDRSH(int cc, int Rd, int Rn, uint32_t offset)
|
||||
void ArmToArm64Assembler::LDRSH(int cc, int Rd, int Rn, uint32_t offset)
|
||||
{
|
||||
NOT_IMPLEMENTED(); //Not required
|
||||
}
|
||||
|
||||
void ArmToAarch64Assembler::STRH(int cc, int Rd, int Rn, uint32_t op_type)
|
||||
void ArmToArm64Assembler::STRH(int cc, int Rd, int Rn, uint32_t op_type)
|
||||
{
|
||||
return dataTransfer(opSTRH, cc, Rd, Rn, op_type);
|
||||
}
|
||||
|
|
@ -678,7 +678,7 @@ void ArmToAarch64Assembler::STRH(int cc, int Rd, int Rn, uint32_t op_type)
|
|||
// ----------------------------------------------------------------------------
|
||||
// block data transfer...
|
||||
// ----------------------------------------------------------------------------
|
||||
void ArmToAarch64Assembler::LDM(int cc, int dir,
|
||||
void ArmToArm64Assembler::LDM(int cc, int dir,
|
||||
int Rn, int W, uint32_t reg_list)
|
||||
{
|
||||
const int XSP = 31;
|
||||
|
|
@ -699,7 +699,7 @@ void ArmToAarch64Assembler::LDM(int cc, int dir,
|
|||
}
|
||||
}
|
||||
|
||||
void ArmToAarch64Assembler::STM(int cc, int dir,
|
||||
void ArmToArm64Assembler::STM(int cc, int dir,
|
||||
int Rn, int W, uint32_t reg_list)
|
||||
{
|
||||
const int XSP = 31;
|
||||
|
|
@ -723,15 +723,15 @@ void ArmToAarch64Assembler::STM(int cc, int dir,
|
|||
// ----------------------------------------------------------------------------
|
||||
// special...
|
||||
// ----------------------------------------------------------------------------
|
||||
void ArmToAarch64Assembler::SWP(int cc, int Rn, int Rd, int Rm)
|
||||
void ArmToArm64Assembler::SWP(int cc, int Rn, int Rd, int Rm)
|
||||
{
|
||||
NOT_IMPLEMENTED(); //Not required
|
||||
}
|
||||
void ArmToAarch64Assembler::SWPB(int cc, int Rn, int Rd, int Rm)
|
||||
void ArmToArm64Assembler::SWPB(int cc, int Rn, int Rd, int Rm)
|
||||
{
|
||||
NOT_IMPLEMENTED(); //Not required
|
||||
}
|
||||
void ArmToAarch64Assembler::SWI(int cc, uint32_t comment)
|
||||
void ArmToArm64Assembler::SWI(int cc, uint32_t comment)
|
||||
{
|
||||
NOT_IMPLEMENTED(); //Not required
|
||||
}
|
||||
|
|
@ -739,31 +739,31 @@ void ArmToAarch64Assembler::SWI(int cc, uint32_t comment)
|
|||
// ----------------------------------------------------------------------------
|
||||
// DSP instructions...
|
||||
// ----------------------------------------------------------------------------
|
||||
void ArmToAarch64Assembler::PLD(int Rn, uint32_t offset) {
|
||||
void ArmToArm64Assembler::PLD(int Rn, uint32_t offset) {
|
||||
NOT_IMPLEMENTED(); //Not required
|
||||
}
|
||||
|
||||
void ArmToAarch64Assembler::CLZ(int cc, int Rd, int Rm)
|
||||
void ArmToArm64Assembler::CLZ(int cc, int Rd, int Rm)
|
||||
{
|
||||
NOT_IMPLEMENTED(); //Not required
|
||||
}
|
||||
|
||||
void ArmToAarch64Assembler::QADD(int cc, int Rd, int Rm, int Rn)
|
||||
void ArmToArm64Assembler::QADD(int cc, int Rd, int Rm, int Rn)
|
||||
{
|
||||
NOT_IMPLEMENTED(); //Not required
|
||||
}
|
||||
|
||||
void ArmToAarch64Assembler::QDADD(int cc, int Rd, int Rm, int Rn)
|
||||
void ArmToArm64Assembler::QDADD(int cc, int Rd, int Rm, int Rn)
|
||||
{
|
||||
NOT_IMPLEMENTED(); //Not required
|
||||
}
|
||||
|
||||
void ArmToAarch64Assembler::QSUB(int cc, int Rd, int Rm, int Rn)
|
||||
void ArmToArm64Assembler::QSUB(int cc, int Rd, int Rm, int Rn)
|
||||
{
|
||||
NOT_IMPLEMENTED(); //Not required
|
||||
}
|
||||
|
||||
void ArmToAarch64Assembler::QDSUB(int cc, int Rd, int Rm, int Rn)
|
||||
void ArmToArm64Assembler::QDSUB(int cc, int Rd, int Rm, int Rn)
|
||||
{
|
||||
NOT_IMPLEMENTED(); //Not required
|
||||
}
|
||||
|
|
@ -771,7 +771,7 @@ void ArmToAarch64Assembler::QDSUB(int cc, int Rd, int Rm, int Rn)
|
|||
// ----------------------------------------------------------------------------
|
||||
// 16 x 16 multiplication
|
||||
// ----------------------------------------------------------------------------
|
||||
void ArmToAarch64Assembler::SMUL(int cc, int xy,
|
||||
void ArmToArm64Assembler::SMUL(int cc, int xy,
|
||||
int Rd, int Rm, int Rs)
|
||||
{
|
||||
if(cc != AL){ NOT_IMPLEMENTED(); return;} //Not required
|
||||
|
|
@ -791,7 +791,7 @@ void ArmToAarch64Assembler::SMUL(int cc, int xy,
|
|||
// ----------------------------------------------------------------------------
|
||||
// 32 x 16 multiplication
|
||||
// ----------------------------------------------------------------------------
|
||||
void ArmToAarch64Assembler::SMULW(int cc, int y, int Rd, int Rm, int Rs)
|
||||
void ArmToArm64Assembler::SMULW(int cc, int y, int Rd, int Rm, int Rs)
|
||||
{
|
||||
if(cc != AL){ NOT_IMPLEMENTED(); return;} //Not required
|
||||
|
||||
|
|
@ -807,7 +807,7 @@ void ArmToAarch64Assembler::SMULW(int cc, int y, int Rd, int Rm, int Rs)
|
|||
// ----------------------------------------------------------------------------
|
||||
// 16 x 16 multiplication and accumulate
|
||||
// ----------------------------------------------------------------------------
|
||||
void ArmToAarch64Assembler::SMLA(int cc, int xy, int Rd, int Rm, int Rs, int Rn)
|
||||
void ArmToArm64Assembler::SMLA(int cc, int xy, int Rd, int Rm, int Rs, int Rn)
|
||||
{
|
||||
if(cc != AL){ NOT_IMPLEMENTED(); return;} //Not required
|
||||
if(xy != xyBB) { NOT_IMPLEMENTED(); return;} //Not required
|
||||
|
|
@ -817,14 +817,14 @@ void ArmToAarch64Assembler::SMLA(int cc, int xy, int Rd, int Rm, int Rs, int Rn)
|
|||
*mPC++ = A64_MADD_W(Rd, mTmpReg1, mTmpReg2, Rn);
|
||||
}
|
||||
|
||||
void ArmToAarch64Assembler::SMLAL(int cc, int xy,
|
||||
void ArmToArm64Assembler::SMLAL(int cc, int xy,
|
||||
int RdHi, int RdLo, int Rs, int Rm)
|
||||
{
|
||||
NOT_IMPLEMENTED(); //Not required
|
||||
return;
|
||||
}
|
||||
|
||||
void ArmToAarch64Assembler::SMLAW(int cc, int y,
|
||||
void ArmToArm64Assembler::SMLAW(int cc, int y,
|
||||
int Rd, int Rm, int Rs, int Rn)
|
||||
{
|
||||
NOT_IMPLEMENTED(); //Not required
|
||||
|
|
@ -834,7 +834,7 @@ void ArmToAarch64Assembler::SMLAW(int cc, int y,
|
|||
// ----------------------------------------------------------------------------
|
||||
// Byte/half word extract and extend
|
||||
// ----------------------------------------------------------------------------
|
||||
void ArmToAarch64Assembler::UXTB16(int cc, int Rd, int Rm, int rotate)
|
||||
void ArmToArm64Assembler::UXTB16(int cc, int Rd, int Rm, int rotate)
|
||||
{
|
||||
if(cc != AL){ NOT_IMPLEMENTED(); return;} //Not required
|
||||
|
||||
|
|
@ -849,7 +849,7 @@ void ArmToAarch64Assembler::UXTB16(int cc, int Rd, int Rm, int rotate)
|
|||
// ----------------------------------------------------------------------------
|
||||
// Bit manipulation
|
||||
// ----------------------------------------------------------------------------
|
||||
void ArmToAarch64Assembler::UBFX(int cc, int Rd, int Rn, int lsb, int width)
|
||||
void ArmToArm64Assembler::UBFX(int cc, int Rd, int Rn, int lsb, int width)
|
||||
{
|
||||
if(cc != AL){ NOT_IMPLEMENTED(); return;} //Not required
|
||||
*mPC++ = A64_UBFM_W(Rd, Rn, lsb, lsb + width - 1);
|
||||
|
|
@ -857,7 +857,7 @@ void ArmToAarch64Assembler::UBFX(int cc, int Rd, int Rn, int lsb, int width)
|
|||
// ----------------------------------------------------------------------------
|
||||
// Shifters...
|
||||
// ----------------------------------------------------------------------------
|
||||
int ArmToAarch64Assembler::buildImmediate(
|
||||
int ArmToArm64Assembler::buildImmediate(
|
||||
uint32_t immediate, uint32_t& rot, uint32_t& imm)
|
||||
{
|
||||
rot = 0;
|
||||
|
|
@ -866,13 +866,13 @@ int ArmToAarch64Assembler::buildImmediate(
|
|||
}
|
||||
|
||||
|
||||
bool ArmToAarch64Assembler::isValidImmediate(uint32_t immediate)
|
||||
bool ArmToArm64Assembler::isValidImmediate(uint32_t immediate)
|
||||
{
|
||||
uint32_t rot, imm;
|
||||
return buildImmediate(immediate, rot, imm) == 0;
|
||||
}
|
||||
|
||||
uint32_t ArmToAarch64Assembler::imm(uint32_t immediate)
|
||||
uint32_t ArmToArm64Assembler::imm(uint32_t immediate)
|
||||
{
|
||||
mAddrMode.immediate = immediate;
|
||||
mAddrMode.writeback = false;
|
||||
|
|
@ -882,7 +882,7 @@ uint32_t ArmToAarch64Assembler::imm(uint32_t immediate)
|
|||
|
||||
}
|
||||
|
||||
uint32_t ArmToAarch64Assembler::reg_imm(int Rm, int type, uint32_t shift)
|
||||
uint32_t ArmToArm64Assembler::reg_imm(int Rm, int type, uint32_t shift)
|
||||
{
|
||||
mAddrMode.reg_imm_Rm = Rm;
|
||||
mAddrMode.reg_imm_type = type;
|
||||
|
|
@ -890,13 +890,13 @@ uint32_t ArmToAarch64Assembler::reg_imm(int Rm, int type, uint32_t shift)
|
|||
return OPERAND_REG_IMM;
|
||||
}
|
||||
|
||||
uint32_t ArmToAarch64Assembler::reg_rrx(int Rm)
|
||||
uint32_t ArmToArm64Assembler::reg_rrx(int Rm)
|
||||
{
|
||||
NOT_IMPLEMENTED();
|
||||
return OPERAND_UNSUPPORTED;
|
||||
}
|
||||
|
||||
uint32_t ArmToAarch64Assembler::reg_reg(int Rm, int type, int Rs)
|
||||
uint32_t ArmToArm64Assembler::reg_reg(int Rm, int type, int Rs)
|
||||
{
|
||||
NOT_IMPLEMENTED(); //Not required
|
||||
return OPERAND_UNSUPPORTED;
|
||||
|
|
@ -904,7 +904,7 @@ uint32_t ArmToAarch64Assembler::reg_reg(int Rm, int type, int Rs)
|
|||
// ----------------------------------------------------------------------------
|
||||
// Addressing modes...
|
||||
// ----------------------------------------------------------------------------
|
||||
uint32_t ArmToAarch64Assembler::immed12_pre(int32_t immed12, int W)
|
||||
uint32_t ArmToArm64Assembler::immed12_pre(int32_t immed12, int W)
|
||||
{
|
||||
mAddrMode.immediate = immed12;
|
||||
mAddrMode.writeback = W;
|
||||
|
|
@ -913,7 +913,7 @@ uint32_t ArmToAarch64Assembler::immed12_pre(int32_t immed12, int W)
|
|||
return OPERAND_IMM;
|
||||
}
|
||||
|
||||
uint32_t ArmToAarch64Assembler::immed12_post(int32_t immed12)
|
||||
uint32_t ArmToArm64Assembler::immed12_post(int32_t immed12)
|
||||
{
|
||||
mAddrMode.immediate = immed12;
|
||||
mAddrMode.writeback = true;
|
||||
|
|
@ -922,7 +922,7 @@ uint32_t ArmToAarch64Assembler::immed12_post(int32_t immed12)
|
|||
return OPERAND_IMM;
|
||||
}
|
||||
|
||||
uint32_t ArmToAarch64Assembler::reg_scale_pre(int Rm, int type,
|
||||
uint32_t ArmToArm64Assembler::reg_scale_pre(int Rm, int type,
|
||||
uint32_t shift, int W)
|
||||
{
|
||||
if(type != 0 || shift != 0 || W != 0)
|
||||
|
|
@ -937,13 +937,13 @@ uint32_t ArmToAarch64Assembler::reg_scale_pre(int Rm, int type,
|
|||
}
|
||||
}
|
||||
|
||||
uint32_t ArmToAarch64Assembler::reg_scale_post(int Rm, int type, uint32_t shift)
|
||||
uint32_t ArmToArm64Assembler::reg_scale_post(int Rm, int type, uint32_t shift)
|
||||
{
|
||||
NOT_IMPLEMENTED(); //Not required
|
||||
return OPERAND_UNSUPPORTED;
|
||||
}
|
||||
|
||||
uint32_t ArmToAarch64Assembler::immed8_pre(int32_t immed8, int W)
|
||||
uint32_t ArmToArm64Assembler::immed8_pre(int32_t immed8, int W)
|
||||
{
|
||||
mAddrMode.immediate = immed8;
|
||||
mAddrMode.writeback = W;
|
||||
|
|
@ -952,7 +952,7 @@ uint32_t ArmToAarch64Assembler::immed8_pre(int32_t immed8, int W)
|
|||
return OPERAND_IMM;
|
||||
}
|
||||
|
||||
uint32_t ArmToAarch64Assembler::immed8_post(int32_t immed8)
|
||||
uint32_t ArmToArm64Assembler::immed8_post(int32_t immed8)
|
||||
{
|
||||
mAddrMode.immediate = immed8;
|
||||
mAddrMode.writeback = true;
|
||||
|
|
@ -961,7 +961,7 @@ uint32_t ArmToAarch64Assembler::immed8_post(int32_t immed8)
|
|||
return OPERAND_IMM;
|
||||
}
|
||||
|
||||
uint32_t ArmToAarch64Assembler::reg_pre(int Rm, int W)
|
||||
uint32_t ArmToArm64Assembler::reg_pre(int Rm, int W)
|
||||
{
|
||||
if(W != 0)
|
||||
{
|
||||
|
|
@ -975,7 +975,7 @@ uint32_t ArmToAarch64Assembler::reg_pre(int Rm, int W)
|
|||
}
|
||||
}
|
||||
|
||||
uint32_t ArmToAarch64Assembler::reg_post(int Rm)
|
||||
uint32_t ArmToArm64Assembler::reg_post(int Rm)
|
||||
{
|
||||
NOT_IMPLEMENTED(); //Not required
|
||||
return OPERAND_UNSUPPORTED;
|
||||
|
|
@ -999,7 +999,7 @@ static const uint32_t dataTransferOpCode [] =
|
|||
((0x38u << 24) | (0x1 << 21) | (0x6 << 13) | (0x1 << 12) |(0x1 << 11)),
|
||||
((0x78u << 24) | (0x1 << 21) | (0x6 << 13) | (0x0 << 12) |(0x1 << 11))
|
||||
};
|
||||
uint32_t ArmToAarch64Assembler::A64_LDRSTR_Wm_SXTW_0(uint32_t op,
|
||||
uint32_t ArmToArm64Assembler::A64_LDRSTR_Wm_SXTW_0(uint32_t op,
|
||||
uint32_t size, uint32_t Rt,
|
||||
uint32_t Rn, uint32_t Rm)
|
||||
{
|
||||
|
|
@ -1017,7 +1017,7 @@ uint32_t ArmToAarch64Assembler::A64_LDRSTR_Wm_SXTW_0(uint32_t op,
|
|||
}
|
||||
}
|
||||
|
||||
uint32_t ArmToAarch64Assembler::A64_STR_IMM_PreIndex(uint32_t Rt,
|
||||
uint32_t ArmToArm64Assembler::A64_STR_IMM_PreIndex(uint32_t Rt,
|
||||
uint32_t Rn, int32_t simm)
|
||||
{
|
||||
if(Rn == 31)
|
||||
|
|
@ -1029,7 +1029,7 @@ uint32_t ArmToAarch64Assembler::A64_STR_IMM_PreIndex(uint32_t Rt,
|
|||
return (0xB8 << 24) | (imm9 << 12) | (0x3 << 10) | (Rn << 5) | Rt;
|
||||
}
|
||||
|
||||
uint32_t ArmToAarch64Assembler::A64_LDR_IMM_PostIndex(uint32_t Rt,
|
||||
uint32_t ArmToArm64Assembler::A64_LDR_IMM_PostIndex(uint32_t Rt,
|
||||
uint32_t Rn, int32_t simm)
|
||||
{
|
||||
if(Rn == 31)
|
||||
|
|
@ -1042,7 +1042,7 @@ uint32_t ArmToAarch64Assembler::A64_LDR_IMM_PostIndex(uint32_t Rt,
|
|||
(imm9 << 12) | (0x1 << 10) | (Rn << 5) | Rt;
|
||||
|
||||
}
|
||||
uint32_t ArmToAarch64Assembler::A64_ADD_X_Wm_SXTW(uint32_t Rd,
|
||||
uint32_t ArmToArm64Assembler::A64_ADD_X_Wm_SXTW(uint32_t Rd,
|
||||
uint32_t Rn,
|
||||
uint32_t Rm,
|
||||
uint32_t amount)
|
||||
|
|
@ -1053,7 +1053,7 @@ uint32_t ArmToAarch64Assembler::A64_ADD_X_Wm_SXTW(uint32_t Rd,
|
|||
|
||||
}
|
||||
|
||||
uint32_t ArmToAarch64Assembler::A64_SUB_X_Wm_SXTW(uint32_t Rd,
|
||||
uint32_t ArmToArm64Assembler::A64_SUB_X_Wm_SXTW(uint32_t Rd,
|
||||
uint32_t Rn,
|
||||
uint32_t Rm,
|
||||
uint32_t amount)
|
||||
|
|
@ -1064,13 +1064,13 @@ uint32_t ArmToAarch64Assembler::A64_SUB_X_Wm_SXTW(uint32_t Rd,
|
|||
|
||||
}
|
||||
|
||||
uint32_t ArmToAarch64Assembler::A64_B_COND(uint32_t cc, uint32_t offset)
|
||||
uint32_t ArmToArm64Assembler::A64_B_COND(uint32_t cc, uint32_t offset)
|
||||
{
|
||||
LOG_INSTR("B.%s #.+%d\n", cc_codes[cc], offset);
|
||||
return (0x54 << 24) | ((offset/4) << 5) | (cc);
|
||||
|
||||
}
|
||||
uint32_t ArmToAarch64Assembler::A64_ADD_X(uint32_t Rd, uint32_t Rn,
|
||||
uint32_t ArmToArm64Assembler::A64_ADD_X(uint32_t Rd, uint32_t Rn,
|
||||
uint32_t Rm, uint32_t shift,
|
||||
uint32_t amount)
|
||||
{
|
||||
|
|
@ -1079,21 +1079,21 @@ uint32_t ArmToAarch64Assembler::A64_ADD_X(uint32_t Rd, uint32_t Rn,
|
|||
return ((0x8B << 24) | (shift << 22) | ( Rm << 16) |
|
||||
(amount << 10) |(Rn << 5) | Rd);
|
||||
}
|
||||
uint32_t ArmToAarch64Assembler::A64_ADD_IMM_X(uint32_t Rd, uint32_t Rn,
|
||||
uint32_t ArmToArm64Assembler::A64_ADD_IMM_X(uint32_t Rd, uint32_t Rn,
|
||||
uint32_t imm, uint32_t shift)
|
||||
{
|
||||
LOG_INSTR("ADD X%d, X%d, #%d, LSL #%d\n", Rd, Rn, imm, shift);
|
||||
return (0x91 << 24) | ((shift/12) << 22) | (imm << 10) | (Rn << 5) | Rd;
|
||||
}
|
||||
|
||||
uint32_t ArmToAarch64Assembler::A64_SUB_IMM_X(uint32_t Rd, uint32_t Rn,
|
||||
uint32_t ArmToArm64Assembler::A64_SUB_IMM_X(uint32_t Rd, uint32_t Rn,
|
||||
uint32_t imm, uint32_t shift)
|
||||
{
|
||||
LOG_INSTR("SUB X%d, X%d, #%d, LSL #%d\n", Rd, Rn, imm, shift);
|
||||
return (0xD1 << 24) | ((shift/12) << 22) | (imm << 10) | (Rn << 5) | Rd;
|
||||
}
|
||||
|
||||
uint32_t ArmToAarch64Assembler::A64_ADD_W(uint32_t Rd, uint32_t Rn,
|
||||
uint32_t ArmToArm64Assembler::A64_ADD_W(uint32_t Rd, uint32_t Rn,
|
||||
uint32_t Rm, uint32_t shift,
|
||||
uint32_t amount)
|
||||
{
|
||||
|
|
@ -1103,7 +1103,7 @@ uint32_t ArmToAarch64Assembler::A64_ADD_W(uint32_t Rd, uint32_t Rn,
|
|||
(amount << 10) |(Rn << 5) | Rd);
|
||||
}
|
||||
|
||||
uint32_t ArmToAarch64Assembler::A64_SUB_W(uint32_t Rd, uint32_t Rn,
|
||||
uint32_t ArmToArm64Assembler::A64_SUB_W(uint32_t Rd, uint32_t Rn,
|
||||
uint32_t Rm, uint32_t shift,
|
||||
uint32_t amount,
|
||||
uint32_t setflag)
|
||||
|
|
@ -1124,7 +1124,7 @@ uint32_t ArmToAarch64Assembler::A64_SUB_W(uint32_t Rd, uint32_t Rn,
|
|||
}
|
||||
}
|
||||
|
||||
uint32_t ArmToAarch64Assembler::A64_AND_W(uint32_t Rd, uint32_t Rn,
|
||||
uint32_t ArmToArm64Assembler::A64_AND_W(uint32_t Rd, uint32_t Rn,
|
||||
uint32_t Rm, uint32_t shift,
|
||||
uint32_t amount)
|
||||
{
|
||||
|
|
@ -1134,7 +1134,7 @@ uint32_t ArmToAarch64Assembler::A64_AND_W(uint32_t Rd, uint32_t Rn,
|
|||
(amount << 10) |(Rn << 5) | Rd);
|
||||
}
|
||||
|
||||
uint32_t ArmToAarch64Assembler::A64_ORR_W(uint32_t Rd, uint32_t Rn,
|
||||
uint32_t ArmToArm64Assembler::A64_ORR_W(uint32_t Rd, uint32_t Rn,
|
||||
uint32_t Rm, uint32_t shift,
|
||||
uint32_t amount)
|
||||
{
|
||||
|
|
@ -1144,7 +1144,7 @@ uint32_t ArmToAarch64Assembler::A64_ORR_W(uint32_t Rd, uint32_t Rn,
|
|||
(amount << 10) |(Rn << 5) | Rd);
|
||||
}
|
||||
|
||||
uint32_t ArmToAarch64Assembler::A64_ORN_W(uint32_t Rd, uint32_t Rn,
|
||||
uint32_t ArmToArm64Assembler::A64_ORN_W(uint32_t Rd, uint32_t Rn,
|
||||
uint32_t Rm, uint32_t shift,
|
||||
uint32_t amount)
|
||||
{
|
||||
|
|
@ -1154,76 +1154,76 @@ uint32_t ArmToAarch64Assembler::A64_ORN_W(uint32_t Rd, uint32_t Rn,
|
|||
(amount << 10) |(Rn << 5) | Rd);
|
||||
}
|
||||
|
||||
uint32_t ArmToAarch64Assembler::A64_CSEL_X(uint32_t Rd, uint32_t Rn,
|
||||
uint32_t ArmToArm64Assembler::A64_CSEL_X(uint32_t Rd, uint32_t Rn,
|
||||
uint32_t Rm, uint32_t cond)
|
||||
{
|
||||
LOG_INSTR("CSEL X%d, X%d, X%d, %s\n", Rd, Rn, Rm, cc_codes[cond]);
|
||||
return ((0x9A << 24)|(0x1 << 23)|(Rm << 16) |(cond << 12)| (Rn << 5) | Rd);
|
||||
}
|
||||
|
||||
uint32_t ArmToAarch64Assembler::A64_CSEL_W(uint32_t Rd, uint32_t Rn,
|
||||
uint32_t ArmToArm64Assembler::A64_CSEL_W(uint32_t Rd, uint32_t Rn,
|
||||
uint32_t Rm, uint32_t cond)
|
||||
{
|
||||
LOG_INSTR("CSEL W%d, W%d, W%d, %s\n", Rd, Rn, Rm, cc_codes[cond]);
|
||||
return ((0x1A << 24)|(0x1 << 23)|(Rm << 16) |(cond << 12)| (Rn << 5) | Rd);
|
||||
}
|
||||
|
||||
uint32_t ArmToAarch64Assembler::A64_RET(uint32_t Rn)
|
||||
uint32_t ArmToArm64Assembler::A64_RET(uint32_t Rn)
|
||||
{
|
||||
LOG_INSTR("RET X%d\n", Rn);
|
||||
return ((0xD6 << 24) | (0x1 << 22) | (0x1F << 16) | (Rn << 5));
|
||||
}
|
||||
|
||||
uint32_t ArmToAarch64Assembler::A64_MOVZ_X(uint32_t Rd, uint32_t imm,
|
||||
uint32_t ArmToArm64Assembler::A64_MOVZ_X(uint32_t Rd, uint32_t imm,
|
||||
uint32_t shift)
|
||||
{
|
||||
LOG_INSTR("MOVZ X%d, #0x%x, LSL #%d\n", Rd, imm, shift);
|
||||
return(0xD2 << 24) | (0x1 << 23) | ((shift/16) << 21) | (imm << 5) | Rd;
|
||||
}
|
||||
|
||||
uint32_t ArmToAarch64Assembler::A64_MOVK_W(uint32_t Rd, uint32_t imm,
|
||||
uint32_t ArmToArm64Assembler::A64_MOVK_W(uint32_t Rd, uint32_t imm,
|
||||
uint32_t shift)
|
||||
{
|
||||
LOG_INSTR("MOVK W%d, #0x%x, LSL #%d\n", Rd, imm, shift);
|
||||
return (0x72 << 24) | (0x1 << 23) | ((shift/16) << 21) | (imm << 5) | Rd;
|
||||
}
|
||||
|
||||
uint32_t ArmToAarch64Assembler::A64_MOVZ_W(uint32_t Rd, uint32_t imm,
|
||||
uint32_t ArmToArm64Assembler::A64_MOVZ_W(uint32_t Rd, uint32_t imm,
|
||||
uint32_t shift)
|
||||
{
|
||||
LOG_INSTR("MOVZ W%d, #0x%x, LSL #%d\n", Rd, imm, shift);
|
||||
return(0x52 << 24) | (0x1 << 23) | ((shift/16) << 21) | (imm << 5) | Rd;
|
||||
}
|
||||
|
||||
uint32_t ArmToAarch64Assembler::A64_SMADDL(uint32_t Rd, uint32_t Rn,
|
||||
uint32_t ArmToArm64Assembler::A64_SMADDL(uint32_t Rd, uint32_t Rn,
|
||||
uint32_t Rm, uint32_t Ra)
|
||||
{
|
||||
LOG_INSTR("SMADDL X%d, W%d, W%d, X%d\n",Rd, Rn, Rm, Ra);
|
||||
return ((0x9B << 24) | (0x1 << 21) | (Rm << 16)|(Ra << 10)|(Rn << 5) | Rd);
|
||||
}
|
||||
|
||||
uint32_t ArmToAarch64Assembler::A64_MADD_W(uint32_t Rd, uint32_t Rn,
|
||||
uint32_t ArmToArm64Assembler::A64_MADD_W(uint32_t Rd, uint32_t Rn,
|
||||
uint32_t Rm, uint32_t Ra)
|
||||
{
|
||||
LOG_INSTR("MADD W%d, W%d, W%d, W%d\n",Rd, Rn, Rm, Ra);
|
||||
return ((0x1B << 24) | (Rm << 16) | (Ra << 10) |(Rn << 5) | Rd);
|
||||
}
|
||||
|
||||
uint32_t ArmToAarch64Assembler::A64_SBFM_W(uint32_t Rd, uint32_t Rn,
|
||||
uint32_t ArmToArm64Assembler::A64_SBFM_W(uint32_t Rd, uint32_t Rn,
|
||||
uint32_t immr, uint32_t imms)
|
||||
{
|
||||
LOG_INSTR("SBFM W%d, W%d, #%d, #%d\n", Rd, Rn, immr, imms);
|
||||
return ((0x13 << 24) | (immr << 16) | (imms << 10) | (Rn << 5) | Rd);
|
||||
|
||||
}
|
||||
uint32_t ArmToAarch64Assembler::A64_UBFM_W(uint32_t Rd, uint32_t Rn,
|
||||
uint32_t ArmToArm64Assembler::A64_UBFM_W(uint32_t Rd, uint32_t Rn,
|
||||
uint32_t immr, uint32_t imms)
|
||||
{
|
||||
LOG_INSTR("UBFM W%d, W%d, #%d, #%d\n", Rd, Rn, immr, imms);
|
||||
return ((0x53 << 24) | (immr << 16) | (imms << 10) | (Rn << 5) | Rd);
|
||||
|
||||
}
|
||||
uint32_t ArmToAarch64Assembler::A64_UBFM_X(uint32_t Rd, uint32_t Rn,
|
||||
uint32_t ArmToArm64Assembler::A64_UBFM_X(uint32_t Rd, uint32_t Rn,
|
||||
uint32_t immr, uint32_t imms)
|
||||
{
|
||||
LOG_INSTR("UBFM X%d, X%d, #%d, #%d\n", Rd, Rn, immr, imms);
|
||||
|
|
@ -1231,7 +1231,7 @@ uint32_t ArmToAarch64Assembler::A64_UBFM_X(uint32_t Rd, uint32_t Rn,
|
|||
(immr << 16) | (imms << 10) | (Rn << 5) | Rd);
|
||||
|
||||
}
|
||||
uint32_t ArmToAarch64Assembler::A64_EXTR_W(uint32_t Rd, uint32_t Rn,
|
||||
uint32_t ArmToArm64Assembler::A64_EXTR_W(uint32_t Rd, uint32_t Rn,
|
||||
uint32_t Rm, uint32_t lsb)
|
||||
{
|
||||
LOG_INSTR("EXTR W%d, W%d, W%d, #%d\n", Rd, Rn, Rm, lsb);
|
||||
|
|
@ -26,8 +26,8 @@
|
|||
* SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
#ifndef ANDROID_ARMTOAARCH64ASSEMBLER_H
|
||||
#define ANDROID_ARMTOAARCH64ASSEMBLER_H
|
||||
#ifndef ANDROID_ARMTOARM64ASSEMBLER_H
|
||||
#define ANDROID_ARMTOARM64ASSEMBLER_H
|
||||
|
||||
#include <stdint.h>
|
||||
#include <sys/types.h>
|
||||
|
|
@ -44,12 +44,12 @@ namespace android {
|
|||
|
||||
// ----------------------------------------------------------------------------
|
||||
|
||||
class ArmToAarch64Assembler : public ARMAssemblerInterface
|
||||
class ArmToArm64Assembler : public ARMAssemblerInterface
|
||||
{
|
||||
public:
|
||||
ArmToAarch64Assembler(const sp<Assembly>& assembly);
|
||||
ArmToAarch64Assembler(void *base);
|
||||
virtual ~ArmToAarch64Assembler();
|
||||
ArmToArm64Assembler(const sp<Assembly>& assembly);
|
||||
ArmToArm64Assembler(void *base);
|
||||
virtual ~ArmToArm64Assembler();
|
||||
|
||||
uint32_t* base() const;
|
||||
uint32_t* pc() const;
|
||||
|
|
@ -176,8 +176,8 @@ public:
|
|||
virtual void UBFX(int cc, int Rd, int Rn, int lsb, int width);
|
||||
|
||||
private:
|
||||
ArmToAarch64Assembler(const ArmToAarch64Assembler& rhs);
|
||||
ArmToAarch64Assembler& operator = (const ArmToAarch64Assembler& rhs);
|
||||
ArmToArm64Assembler(const ArmToArm64Assembler& rhs);
|
||||
ArmToArm64Assembler& operator = (const ArmToArm64Assembler& rhs);
|
||||
|
||||
// -----------------------------------------------------------------------
|
||||
// helper functions
|
||||
|
|
@ -189,7 +189,7 @@ private:
|
|||
int Rd, int Rn, uint32_t Op2);
|
||||
|
||||
// -----------------------------------------------------------------------
|
||||
// Aarch64 instructions
|
||||
// Arm64 instructions
|
||||
// -----------------------------------------------------------------------
|
||||
uint32_t A64_B_COND(uint32_t cc, uint32_t offset);
|
||||
uint32_t A64_RET(uint32_t Rn);
|
||||
|
|
@ -287,4 +287,4 @@ private:
|
|||
|
||||
}; // namespace android
|
||||
|
||||
#endif //ANDROID_AARCH64ASSEMBLER_H
|
||||
#endif //ANDROID_ARM64ASSEMBLER_H
|
||||
|
|
@ -267,7 +267,7 @@ static void decode_token(uint32_t code, char *token, char *instr_part)
|
|||
return;
|
||||
}
|
||||
|
||||
int aarch64_disassemble(uint32_t code, char* instr)
|
||||
int arm64_disassemble(uint32_t code, char* instr)
|
||||
{
|
||||
uint32_t i;
|
||||
char token[256];
|
||||
|
|
@ -26,10 +26,10 @@
|
|||
* SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
#ifndef ANDROID_AARCH64DISASSEMBLER_H
|
||||
#define ANDROID_AARCH64DISASSEMBLER_H
|
||||
#ifndef ANDROID_ARM64DISASSEMBLER_H
|
||||
#define ANDROID_ARM64DISASSEMBLER_H
|
||||
|
||||
#include <inttypes.h>
|
||||
int aarch64_disassemble(uint32_t code, char* instr);
|
||||
int arm64_disassemble(uint32_t code, char* instr);
|
||||
|
||||
#endif //ANDROID_AARCH64ASSEMBLER_H
|
||||
#endif //ANDROID_ARM64ASSEMBLER_H
|
||||
|
|
@ -901,7 +901,7 @@ void GGLAssembler::build_and_immediate(int d, int s, uint32_t mask, int bits)
|
|||
AND( AL, 0, d, s, imm(mask) );
|
||||
return;
|
||||
}
|
||||
else if (getCodegenArch() == CODEGEN_ARCH_AARCH64) {
|
||||
else if (getCodegenArch() == CODEGEN_ARCH_ARM64) {
|
||||
AND( AL, 0, d, s, imm(mask) );
|
||||
return;
|
||||
}
|
||||
|
|
|
|||
|
|
@ -34,7 +34,7 @@
|
|||
#if defined(__arm__)
|
||||
#include "codeflinger/ARMAssembler.h"
|
||||
#elif defined(__aarch64__)
|
||||
#include "codeflinger/Aarch64Assembler.h"
|
||||
#include "codeflinger/Arm64Assembler.h"
|
||||
#elif defined(__mips__)
|
||||
#include "codeflinger/MIPSAssembler.h"
|
||||
#endif
|
||||
|
|
@ -128,8 +128,8 @@ extern "C" void scanline_t32cb16_arm(uint16_t *dst, uint32_t *src, size_t ct);
|
|||
extern "C" void scanline_col32cb16blend_neon(uint16_t *dst, uint32_t *col, size_t ct);
|
||||
extern "C" void scanline_col32cb16blend_arm(uint16_t *dst, uint32_t col, size_t ct);
|
||||
#elif defined(__aarch64__)
|
||||
extern "C" void scanline_t32cb16blend_aarch64(uint16_t*, uint32_t*, size_t);
|
||||
extern "C" void scanline_col32cb16blend_aarch64(uint16_t *dst, uint32_t col, size_t ct);
|
||||
extern "C" void scanline_t32cb16blend_arm64(uint16_t*, uint32_t*, size_t);
|
||||
extern "C" void scanline_col32cb16blend_arm64(uint16_t *dst, uint32_t col, size_t ct);
|
||||
#elif defined(__mips__)
|
||||
extern "C" void scanline_t32cb16blend_mips(uint16_t*, uint32_t*, size_t);
|
||||
#endif
|
||||
|
|
@ -405,7 +405,7 @@ static void pick_scanline(context_t* c)
|
|||
#if defined(__mips__)
|
||||
GGLAssembler assembler( new ArmToMipsAssembler(a) );
|
||||
#elif defined(__aarch64__)
|
||||
GGLAssembler assembler( new ArmToAarch64Assembler(a) );
|
||||
GGLAssembler assembler( new ArmToArm64Assembler(a) );
|
||||
#endif
|
||||
// generate the scanline code for the given needs
|
||||
int err = assembler.scanline(c->state.needs, c);
|
||||
|
|
@ -2098,7 +2098,7 @@ void scanline_col32cb16blend(context_t* c)
|
|||
scanline_col32cb16blend_arm(dst, GGL_RGBA_TO_HOST(c->packed8888), ct);
|
||||
#endif // defined(__ARM_HAVE_NEON) && BYTE_ORDER == LITTLE_ENDIAN
|
||||
#elif ((ANDROID_CODEGEN >= ANDROID_CODEGEN_ASM) && defined(__aarch64__))
|
||||
scanline_col32cb16blend_aarch64(dst, GGL_RGBA_TO_HOST(c->packed8888), ct);
|
||||
scanline_col32cb16blend_arm64(dst, GGL_RGBA_TO_HOST(c->packed8888), ct);
|
||||
#else
|
||||
uint32_t s = GGL_RGBA_TO_HOST(c->packed8888);
|
||||
int sA = (s>>24);
|
||||
|
|
@ -2186,7 +2186,7 @@ void scanline_t32cb16blend(context_t* c)
|
|||
#ifdef __arm__
|
||||
scanline_t32cb16blend_arm(dst, src, ct);
|
||||
#elif defined(__aarch64__)
|
||||
scanline_t32cb16blend_aarch64(dst, src, ct);
|
||||
scanline_t32cb16blend_arm64(dst, src, ct);
|
||||
#elif defined(__mips__)
|
||||
scanline_t32cb16blend_mips(dst, src, ct);
|
||||
#endif
|
||||
|
|
|
|||
|
|
@ -1,3 +1,3 @@
|
|||
ifeq ($(TARGET_ARCH),aarch64)
|
||||
ifeq ($(TARGET_ARCH),arm64)
|
||||
include $(all-subdir-makefiles)
|
||||
endif
|
||||
|
|
@ -2,7 +2,7 @@ LOCAL_PATH:= $(call my-dir)
|
|||
include $(CLEAR_VARS)
|
||||
|
||||
LOCAL_SRC_FILES:= \
|
||||
aarch64_assembler_test.cpp\
|
||||
arm64_assembler_test.cpp\
|
||||
asm_test_jacket.S
|
||||
|
||||
LOCAL_SHARED_LIBRARIES := \
|
||||
|
|
@ -12,7 +12,7 @@ LOCAL_SHARED_LIBRARIES := \
|
|||
LOCAL_C_INCLUDES := \
|
||||
system/core/libpixelflinger
|
||||
|
||||
LOCAL_MODULE:= test-pixelflinger-aarch64-assembler-test
|
||||
LOCAL_MODULE:= test-pixelflinger-arm64-assembler-test
|
||||
|
||||
LOCAL_MODULE_TAGS := tests
|
||||
|
||||
|
|
@ -40,7 +40,7 @@
|
|||
#include <inttypes.h>
|
||||
|
||||
#include "codeflinger/ARMAssemblerInterface.h"
|
||||
#include "codeflinger/Aarch64Assembler.h"
|
||||
#include "codeflinger/Arm64Assembler.h"
|
||||
using namespace android;
|
||||
|
||||
#define TESTS_DATAOP_ENABLE 1
|
||||
|
|
@ -712,7 +712,7 @@ int main(void)
|
|||
{
|
||||
uint32_t i;
|
||||
|
||||
/* Allocate memory to store instructions generated by ArmToAarch64Assembler */
|
||||
/* Allocate memory to store instructions generated by ArmToArm64Assembler */
|
||||
{
|
||||
int fd = ashmem_create_region("code cache", instrMemSize);
|
||||
if(fd < 0)
|
||||
|
|
@ -723,7 +723,7 @@ int main(void)
|
|||
MAP_PRIVATE, fd, 0);
|
||||
}
|
||||
|
||||
ArmToAarch64Assembler a64asm(instrMem);
|
||||
ArmToArm64Assembler a64asm(instrMem);
|
||||
|
||||
if(TESTS_DATAOP_ENABLE)
|
||||
{
|
||||
|
|
@ -3,13 +3,13 @@ include $(CLEAR_VARS)
|
|||
|
||||
LOCAL_SRC_FILES:= \
|
||||
col32cb16blend_test.c \
|
||||
../../../arch-aarch64/col32cb16blend.S
|
||||
../../../arch-arm64/col32cb16blend.S
|
||||
|
||||
LOCAL_SHARED_LIBRARIES :=
|
||||
|
||||
LOCAL_C_INCLUDES :=
|
||||
|
||||
LOCAL_MODULE:= test-pixelflinger-aarch64-col32cb16blend
|
||||
LOCAL_MODULE:= test-pixelflinger-arm64-col32cb16blend
|
||||
|
||||
LOCAL_MODULE_TAGS := tests
|
||||
|
||||
|
|
@ -60,7 +60,7 @@ struct test_t tests[] =
|
|||
{"Count 10, Src=Rand, Dst=Rand", 0x12345678, 0x9ABC, 10}
|
||||
};
|
||||
|
||||
void scanline_col32cb16blend_aarch64(uint16_t *dst, int32_t src, size_t count);
|
||||
void scanline_col32cb16blend_arm64(uint16_t *dst, int32_t src, size_t count);
|
||||
void scanline_col32cb16blend_c(uint16_t * dst, int32_t src, size_t count)
|
||||
{
|
||||
int srcAlpha = (src>>24);
|
||||
|
|
@ -103,7 +103,7 @@ void scanline_col32cb16blend_test()
|
|||
|
||||
|
||||
scanline_col32cb16blend_c(dst_c, test.src_color, test.count);
|
||||
scanline_col32cb16blend_aarch64(dst_asm, test.src_color, test.count);
|
||||
scanline_col32cb16blend_arm64(dst_asm, test.src_color, test.count);
|
||||
|
||||
|
||||
if(memcmp(dst_c, dst_asm, sizeof(dst_c)) == 0)
|
||||
|
|
@ -2,15 +2,15 @@ LOCAL_PATH:= $(call my-dir)
|
|||
include $(CLEAR_VARS)
|
||||
|
||||
LOCAL_SRC_FILES:= \
|
||||
aarch64_diassembler_test.cpp \
|
||||
../../../codeflinger/Aarch64Disassembler.cpp
|
||||
arm64_diassembler_test.cpp \
|
||||
../../../codeflinger/Arm64Disassembler.cpp
|
||||
|
||||
LOCAL_SHARED_LIBRARIES :=
|
||||
|
||||
LOCAL_C_INCLUDES := \
|
||||
system/core/libpixelflinger/codeflinger
|
||||
|
||||
LOCAL_MODULE:= test-pixelflinger-aarch64-disassembler-test
|
||||
LOCAL_MODULE:= test-pixelflinger-arm64-disassembler-test
|
||||
|
||||
LOCAL_MODULE_TAGS := tests
|
||||
|
||||
|
|
@ -29,7 +29,7 @@
|
|||
#include <inttypes.h>
|
||||
#include <string.h>
|
||||
|
||||
int aarch64_disassemble(uint32_t code, char* instr);
|
||||
int arm64_disassemble(uint32_t code, char* instr);
|
||||
|
||||
struct test_table_entry_t
|
||||
{
|
||||
|
|
@ -298,7 +298,7 @@ int main()
|
|||
{
|
||||
test_table_entry_t *test;
|
||||
test = &test_table[i];
|
||||
aarch64_disassemble(test->code, instr);
|
||||
arm64_disassemble(test->code, instr);
|
||||
if(strcmp(instr, test->instr) != 0)
|
||||
{
|
||||
printf("Test Failed \n"
|
||||
|
|
@ -3,13 +3,13 @@ include $(CLEAR_VARS)
|
|||
|
||||
LOCAL_SRC_FILES:= \
|
||||
t32cb16blend_test.c \
|
||||
../../../arch-aarch64/t32cb16blend.S
|
||||
../../../arch-arm64/t32cb16blend.S
|
||||
|
||||
LOCAL_SHARED_LIBRARIES :=
|
||||
|
||||
LOCAL_C_INCLUDES :=
|
||||
|
||||
LOCAL_MODULE:= test-pixelflinger-aarch64-t32cb16blend
|
||||
LOCAL_MODULE:= test-pixelflinger-arm64-t32cb16blend
|
||||
|
||||
LOCAL_MODULE_TAGS := tests
|
||||
|
||||
|
|
@ -61,7 +61,7 @@ struct test_t tests[] =
|
|||
|
||||
};
|
||||
|
||||
void scanline_t32cb16blend_aarch64(uint16_t*, uint32_t*, size_t);
|
||||
void scanline_t32cb16blend_arm64(uint16_t*, uint32_t*, size_t);
|
||||
void scanline_t32cb16blend_c(uint16_t * dst, uint32_t* src, size_t count)
|
||||
{
|
||||
while (count--)
|
||||
|
|
@ -112,7 +112,7 @@ void scanline_t32cb16blend_test()
|
|||
}
|
||||
|
||||
scanline_t32cb16blend_c(dst_c,src,test.count);
|
||||
scanline_t32cb16blend_aarch64(dst_asm,src,test.count);
|
||||
scanline_t32cb16blend_arm64(dst_asm,src,test.count);
|
||||
|
||||
|
||||
if(memcmp(dst_c, dst_asm, sizeof(dst_c)) == 0)
|
||||
|
|
@ -10,7 +10,7 @@
|
|||
#include "codeflinger/GGLAssembler.h"
|
||||
#include "codeflinger/ARMAssembler.h"
|
||||
#include "codeflinger/MIPSAssembler.h"
|
||||
#include "codeflinger/Aarch64Assembler.h"
|
||||
#include "codeflinger/Arm64Assembler.h"
|
||||
|
||||
#if defined(__arm__) || defined(__mips__) || defined(__aarch64__)
|
||||
# define ANDROID_ARM_CODEGEN 1
|
||||
|
|
@ -57,7 +57,7 @@ static void ggl_test_codegen(uint32_t n, uint32_t p, uint32_t t0, uint32_t t1)
|
|||
#endif
|
||||
|
||||
#if defined(__aarch64__)
|
||||
GGLAssembler assembler( new ArmToAarch64Assembler(a) );
|
||||
GGLAssembler assembler( new ArmToArm64Assembler(a) );
|
||||
#endif
|
||||
|
||||
int err = assembler.scanline(needs, (context_t*)c);
|
||||
|
|
@ -66,7 +66,7 @@ static void ggl_test_codegen(uint32_t n, uint32_t p, uint32_t t0, uint32_t t1)
|
|||
}
|
||||
gglUninit(c);
|
||||
#else
|
||||
printf("This test runs only on ARM, Aarch64 or MIPS\n");
|
||||
printf("This test runs only on ARM, Arm64 or MIPS\n");
|
||||
#endif
|
||||
}
|
||||
|
||||
|
|
|
|||
Loading…
Add table
Reference in a new issue