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Merge commit '0b961aa60cdb2326244b8098b976b8decc0096ff' into android12-5.4-lahaina

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* commit '0b961aa60cdb2326244b8098b976b8decc0096ff':
  ARM: dts: msm: add support panel ili9881c for bengal/scuba
  ARM: dts: msm: change target for bengal/scuba
  ARM: dts: msm: add dispcc clock reference for holi dsi-dsiplay node
  ARM: dts: msm: Add 120fps panel support for r66451 on Blair CDP
  ARM: dts: msm: enable dsi phy clamps
  ARM: dts: msm: add pll dts of display for QCS610
  ARM: dts: msm: add sde display dts for bengal
  ARM: dts: msm: add sde display dts for scuba
  ARM: dts: msm: add sde dts of display for QCS610
  ARM: dts: msm: Add video mode ILI988C LCD panel
  ARM: dts: msm: Add display support for idp-nopmi on Yupik
  ARM: dts: msm: delay backlight update until first frame on Blair
  ARM: dts: msm: add dispcc clock reference for blair dsi-dsiplay node
  ARM: dts: qcom: update idle mode commands for RM69090 cmd panel
  ARM: dts: msm: enable esd check for rm69090 amoled panel
  ARM: dts: msm: update dsi commands for rm69090 panel
  ARM: dts: msm: update regulator load values
  bindings: Documentation: add property for cwb mixer mask
  ARM: dts: msm: add sde-mixer-cwb-mask property
  ARM: dts: msm: update interrupt type for QPIC display
  ARM: dts: msm: enable ulps for panels on monaco
  ARM: dts: msm: update init sequence for display panel
  ARM: dts: msm: add dummy ibb regulator supply for amoled panel
  ARM: dts: msm: add video mode support for RM69090 panel
  ARM: dts: msm: add panel support for monaco WDP
  ARM: dts: msm: update max clk rate for display clocks
  ARM: dts: msm: add dts of display for qrb2210-rb1
  ARM: dts: msm: add cpu irq latency for display
  ARM: dts: qcom: update idle mode commands for RM69090 cmd panel
  ARM: dts: msm: update vddio for r66451 panel
  ARM: dts: msm: add panel dtsi for monaco WDP
  ARM: dts: msm: add idle mode commands in panel dtsi
  ARM: dts: msm: Add display support for Blair ATP platform
  ARM: dts: msm: Add  rounded corner dtsi nodes for monaco
  ARM: dts: msm: Update phy timings based on Blair revision YK
  ARM: dts: msm: add dummy regulator for ibb supply for Blair
  ARM: dts: msm: remove the t-clk-post and t-clk-pre timings for blair QRD
  ARM: dts: msm: remove the t-clk-post and t-clk-pre timings from Blair
  ARM: dts: msm: Enable NT36672E C-PHY LCD panel for Blair target
  ARM: dts: msm: Enable NT36672E D-PHY LCD panel for Blair target
  ARM: dts: msm: update supply-min-voltage of dsi phy supply for Blair
  ARM: dts: msm: add list-cells property for mdp node
  ARM: dts: msm: update tear irq offsets for monaco
  ARM: dts: msm: update sde qos config for monaco
  ARM: dts: msm: add support of sim panel for Blair target
  bindings: Documentation: LP11 insertion between lines feature
  ARM: dts: msm: update lane-config settings for monaco-sde
  ARM: dts: msm: add a new display qrd dtsi for Blair
  ARM: dts: msm: update clock list for monaco-sde
  ARM: dts: msm:  add support for QPIC display
  bindings: Documentation: add documentation for qpic display
  ARM: dts: msm: Update dsi phy addresses and timings for Blair target

Change-Id: Ida65afb821a775470c14b671d3bcfd129ae6db44
This commit is contained in:
Michael Bestas 2022-10-02 02:11:59 +03:00
commit 1abb0c9217
No known key found for this signature in database
GPG key ID: CC95044519BE6669
29 changed files with 2244 additions and 29 deletions
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279
arch/arm64/boot/dts/vendor/qcom/display/bengal-sde-common.dtsi vendored Normal file
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@ -0,0 +1,279 @@
#include <dt-bindings/clock/mdss-14nm-pll-clk.h>
&soc {
mdss_mdp: qcom,mdss_mdp {
compatible = "qcom,sde-kms";
reg = <0x5e00000 0x8f030>,
<0x5eb0000 0x2008>,
<0x5e8f000 0x02c>,
<0xc125ba4 0x20>;
reg-names = "mdp_phys",
"vbif_phys",
"sid_phys",
"sde_imem_phys";
clock-rate = <0 0 0 300000000 19200000 192000000>;
clock-max-rate = <0 0 0 400000000 19200000 400000000>;
sde-vdd-supply = <&mdss_core_gdsc>;
/* Enable thermal cooling device */
#cooling-cells = <2>;
/* interrupt config */
interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>;
interrupt-controller;
#interrupt-cells = <1>;
#power-domain-cells = <0>;
/* hw blocks */
qcom,sde-off = <0x1000>;
qcom,sde-len = <0x494>;
qcom,sde-ctl-off = <0x2000>;
qcom,sde-ctl-size = <0x1dc>;
qcom,sde-ctl-display-pref = "primary";
qcom,sde-mixer-off = <0x45000>;
qcom,sde-mixer-size = <0x320>;
qcom,sde-mixer-display-pref = "primary";
qcom,sde-dspp-top-off = <0x1300>;
qcom,sde-dspp-top-size = <0x80>;
qcom,sde-dspp-off = <0x55000>;
qcom,sde-dspp-size = <0xfe4>;
qcom,sde-intf-off = <0x0 0x6b800>;
qcom,sde-intf-size = <0x2b8>;
qcom,sde-intf-type = "none", "dsi";
qcom,sde-pp-off = <0x71000>;
qcom,sde-pp-size = <0xd4>;
qcom,sde-dither-off = <0x30e0>;
qcom,sde-dither-version = <0x00010000>;
qcom,sde-dither-size = <0x20>;
qcom,sde-sspp-type = "vig", "dma";
qcom,sde-sspp-off = <0x5000 0x25000>;
qcom,sde-sspp-src-size = <0x1f8>;
qcom,sde-sspp-xin-id = <0 1>;
qcom,sde-sspp-excl-rect = <1 1>;
qcom,sde-sspp-smart-dma-priority = <2 1>;
qcom,sde-smart-dma-rev = "smart_dma_v2p5";
qcom,sde-mixer-pair-mask = <0>;
qcom,sde-mixer-blend-op-off = <0x20 0x38 0x50 0x68 0x80 0x98
0xb0 0xc8 0xe0 0xf8 0x110>;
qcom,sde-mixer-stage-base-layer;
qcom,sde-max-per-pipe-bw-kbps = <2600000 2600000>;
qcom,sde-max-per-pipe-bw-high-kbps = <2600000 2600000>;
/* offsets are relative to "mdp_phys + qcom,sde-off */
qcom,sde-sspp-clk-ctrl =
<0x2ac 0>, <0x2ac 8>;
qcom,sde-mixer-linewidth = <2048>;
qcom,sde-mixer-blendstages = <0x4>;
qcom,sde-panic-per-pipe;
qcom,sde-has-cdp;
qcom,sde-has-dim-layer;
qcom,sde-has-idle-pc;
qcom,sde-max-bw-low-kbps = <3100000>;
qcom,sde-max-bw-high-kbps = <4000000>;
qcom,sde-min-core-ib-kbps = <2400000>;
qcom,sde-min-llcc-ib-kbps = <800000>;
qcom,sde-min-dram-ib-kbps = <800000>;
qcom,sde-dram-channels = <1>;
qcom,sde-num-nrt-paths = <0>;
qcom,sde-vbif-off = <0>;
qcom,sde-vbif-size = <0x2008>;
qcom,sde-vbif-id = <0>;
qcom,sde-vbif-memtype-0 = <3 3 3 3 3 3 3 3>;
qcom,sde-vbif-memtype-1 = <3 3 3 3 3 3>;
qcom,sde-vbif-qos-rt-remap = <3 3 4 4 5 5 6 6>;
/*Pending macrotile & macrotile-qseed has the same configs */
qcom,sde-danger-lut = <0x000000ff 0x0000ffff
0x00000000 0x00000000 0x0000ffff>;
qcom,sde-safe-lut-linear = <0 0xfff0>;
qcom,sde-qos-lut-linear = <0 0x00112222 0x22335777>;
qcom,sde-cdp-setting = <1 1>, <1 0>;
qcom,sde-qos-cpu-mask = <0x3>;
qcom,sde-qos-cpu-dma-latency = <300>;
qcom,sde-secure-sid-mask = <0x0000421>;
qcom,sde-num-mnoc-ports = <1>;
qcom,sde-axi-bus-width = <16>;
qcom,sde-reg-bus,vectors-KBps = <0 0>,
<0 76800>,
<0 150000>,
<0 300000>;
qcom,sde-sspp-vig-blocks {
};
qcom,sde-dspp-blocks {
qcom,sde-dspp-igc = <0x0 0x00030001>;
qcom,sde-dspp-hsic = <0x800 0x00010007>;
qcom,sde-dspp-memcolor = <0x880 0x00010007>;
qcom,sde-dspp-hist = <0x800 0x00010007>;
qcom,sde-dspp-sixzone= <0x900 0x00010007>;
qcom,sde-dspp-vlut = <0xa00 0x00010008>;
qcom,sde-dspp-pcc = <0x1700 0x00040000>;
qcom,sde-dspp-gc = <0x17c0 0x00010008>;
qcom,sde-dspp-dither = <0x82c 0x00010007>;
};
qcom,platform-supply-entries {
#address-cells = <1>;
#size-cells = <0>;
qcom,platform-supply-entry@0 {
reg = <0>;
qcom,supply-name = "sde-vdd";
qcom,supply-min-voltage = <0>;
qcom,supply-max-voltage = <0>;
qcom,supply-enable-load = <0>;
qcom,supply-disable-load = <0>;
};
};
/* data and reg bus scale settings */
qcom,sde-data-bus {
qcom,msm-bus,name = "mdss_sde";
qcom,msm-bus,num-cases = <3>;
qcom,msm-bus,num-paths = <1>;
qcom,msm-bus,vectors-KBps =
<22 512 0 0>,
<22 512 0 4800000>,
<22 512 0 4800000>;
};
qcom,sde-limits {
qcom,sde-linewidth-limits {
qcom,sde-limit-name = "sspp_linewidth_usecases";
qcom,sde-limit-cases = "vig", "dma", "scale";
qcom,sde-limit-ids= <0x1 0x2 0x4>;
qcom,sde-limit-values = <0x1 4096>,
<0x5 2560>,
<0x2 2160>;
};
qcom,sde-bw-limits {
qcom,sde-limit-name = "sde_bwlimit_usecases";
qcom,sde-limit-cases = "per_vig_pipe",
"per_dma_pipe",
"total_max_bw",
"camera_concurrency";
qcom,sde-limit-ids = <0x1 0x2 0x4 0x8>;
qcom,sde-limit-values = <0x1 2600000>,
<0x9 2600000>,
<0x2 2600000>,
<0xa 2600000>,
<0x4 4000000>,
<0xc 3100000>;
};
};
};
mdss_dsi0: qcom,mdss_dsi_ctrl0@5e94000 {
compatible = "qcom,dsi-ctrl-hw-v2.4";
label = "dsi-ctrl-0";
cell-index = <0>;
frame-threshold-time-us = <800>;
reg = <0x5e94000 0x400>,
<0x5f08000 0x4>;
reg-names = "dsi_ctrl", "disp_cc_base";
interrupt-parent = <&mdss_mdp>;
interrupts = <4 0>;
qcom,ctrl-supply-entries {
#address-cells = <1>;
#size-cells = <0>;
qcom,ctrl-supply-entry@0 {
reg = <0>;
qcom,supply-name = "vdda-1p2";
qcom,supply-min-voltage = <1232000>;
qcom,supply-max-voltage = <1232000>;
qcom,supply-enable-load = <21800>;
qcom,supply-disable-load = <0>;
};
};
qcom,core-supply-entries {
#address-cells = <1>;
#size-cells = <0>;
qcom,core-supply-entry@0 {
reg = <0>;
qcom,supply-name = "refgen";
qcom,supply-min-voltage = <0>;
qcom,supply-max-voltage = <0>;
qcom,supply-enable-load = <0>;
qcom,supply-disable-load = <0>;
};
};
};
mdss_dsi_phy0: qcom,mdss_dsi_phy0@5e94400 {
compatible = "qcom,dsi-phy-v2.0";
label = "dsi-phy-0";
cell-index = <0>;
#clock-cells = <1>;
reg = <0x5e94400 0x588>,
<0x5e01400 0x100>,
<0x5e94200 0x100>,
<0x5e94400 0x588>,
<0x5f03000 0x8>;
reg-names = "dsi_phy", "phy_clamp_base",
"dyn_refresh_base", "pll_base", "gdsc_base";
pll-label = "dsi_pll_14nm";
qcom,platform-strength-ctrl = [ff 06
ff 06
ff 06
ff 06
ff 00];
qcom,platform-lane-config = [00 00 10 0f
00 00 10 0f
00 00 10 0f
00 00 10 0f
00 00 10 8f];
qcom,platform-regulator-settings = [1d 1d 1d 1d 1d];
qcom,phy-supply-entries {
#address-cells = <1>;
#size-cells = <0>;
qcom,phy-supply-entry@0 {
reg = <0>;
qcom,supply-name = "vdda-0p9";
qcom,supply-min-voltage =
<RPM_SMD_REGULATOR_LEVEL_NOM>;
qcom,supply-max-voltage =
<RPM_SMD_REGULATOR_LEVEL_TURBO_NO_CPR>;
qcom,supply-off-min-voltage =
<RPM_SMD_REGULATOR_LEVEL_RETENTION>;
qcom,supply-enable-load = <0>;
qcom,supply-disable-load = <0>;
};
};
};
};

58
arch/arm64/boot/dts/vendor/qcom/display/bengal-sde-display-common.dtsi vendored Normal file
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@ -0,0 +1,58 @@
#include "dsi-panel-ext-bridge-1080p.dtsi"
#include "dsi-panel-ili988c-dual-video.dtsi"
#include <dt-bindings/clock/mdss-14nm-pll-clk.h>
&soc {
dsi_panel_pwr_supply_no_labibb: dsi_panel_pwr_supply_no_labibb {
#address-cells = <1>;
#size-cells = <0>;
qcom,panel-supply-entry@0 {
reg = <0>;
qcom,supply-name = "vddio";
qcom,supply-min-voltage = <1800000>;
qcom,supply-max-voltage = <1800000>;
qcom,supply-enable-load = <62000>;
qcom,supply-disable-load = <80>;
qcom,supply-post-on-sleep = <20>;
};
};
sde_dsi: qcom,dsi-display-primary {
compatible = "qcom,dsi-display";
label = "primary";
qcom,dsi-ctrl = <&mdss_dsi0>;
qcom,dsi-phy = <&mdss_dsi_phy0>;
qcom,mdp = <&mdss_mdp>;
qcom,dsi-default-panel = <&dsi_ili9881c_720p_video>;
};
};
&dsi_ext_bridge_1080p {
qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0",
"src_byte_clk0", "src_pixel_clk0",
"shadow_byte_clk0", "shadow_pixel_clk0";
};
&dsi_ili9881c_720p_video {
qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0",
"src_byte_clk0", "src_pixel_clk0",
"shadow_byte_clk0", "shadow_pixel_clk0";
qcom,mdss-dsi-t-clk-post = <0x0a>;
qcom,mdss-dsi-t-clk-pre = <0x21>;
qcom,mdss-dsi-display-timings {
timing@0 {
qcom,mdss-dsi-panel-timings = [
1F 1C 04 06 03 02 0a
1F 1C 04 06 03 02 0a
1F 1C 04 06 03 02 0a
1F 1C 04 06 03 02 0a
1F 10 04 06 03 02 0a
];
qcom,display-topology = <1 0 1>;
qcom,default-topology-index = <0>;
};
};
};

19
arch/arm64/boot/dts/vendor/qcom/display/bengal-sde-display-qrd.dtsi vendored Normal file
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@ -0,0 +1,19 @@
#include "bengal-sde-display.dtsi"
&dsi_ili9881c_720p_video {
qcom,panel-supply-entries = <&dsi_panel_pwr_supply_no_labibb>;
qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_pwm";
pwms = <&pm6125_pwm 0 0>;
qcom,bl-pmic-pwm-period-usecs = <100>;
qcom,mdss-dsi-bl-min-level = <1>;
qcom,mdss-dsi-bl-max-level = <4095>;
qcom,platform-te-gpio = <&tlmm 40 0>;
qcom,platform-reset-gpio = <&ioexp21 2 0>;
qcom,platform-reset-gpio-always-on;
qcom,platform-bklight-en-gpio = <&ioexp21 3 0>;
qcom,platform-en-gpio = <&ioexp22 6 0>;
};
&sde_dsi {
qcom,dsi-default-panel = <&dsi_ili9881c_720p_video>;
};

27
arch/arm64/boot/dts/vendor/qcom/display/bengal-sde-display.dtsi vendored Normal file
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@ -0,0 +1,27 @@
#include "bengal-sde-display-common.dtsi"
#include <dt-bindings/clock/qcom,dispcc-bengal.h>
&sde_dsi {
clocks = <&mdss_dsi_phy0 BYTE0_MUX_CLK>,
<&mdss_dsi_phy0 PIX0_MUX_CLK>,
<&mdss_dsi_phy0 BYTE0_SRC_CLK>,
<&mdss_dsi_phy0 PIX0_SRC_CLK>,
<&mdss_dsi_phy0 SHADOW_BYTE0_SRC_CLK>,
<&mdss_dsi_phy0 SHADOW_PIX0_SRC_CLK>;
clock-names = "mux_byte_clk0", "mux_pixel_clk0",
"src_byte_clk0", "src_pixel_clk0",
"shadow_byte_clk0", "shadow_pixel_clk0";
pinctrl-names = "panel_active", "panel_suspend";
pinctrl-0 = <&sde_dsi_active &sde_te_active>;
pinctrl-1 = <&sde_dsi_suspend &sde_te_suspend>;
qcom,platform-te-gpio = <&tlmm 40 0>;
qcom,panel-te-source = <0>;
vddio-supply = <&L9A>;
};
&mdss_mdp {
connectors = <&smmu_sde_unsec &sde_dsi>;
};

57
arch/arm64/boot/dts/vendor/qcom/display/bengal-sde.dtsi vendored Normal file
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@ -0,0 +1,57 @@
#include "bengal-sde-common.dtsi"
#include <dt-bindings/clock/mdss-14nm-pll-clk.h>
&soc {
smmu_sde_unsec: qcom,smmu_sde_unsec_cb {
compatible = "qcom,smmu_sde_unsec";
iommus = <&apps_smmu 0x420 0x2>;
qcom,iommu-dma-addr-pool = <0x00020000 0xfffe0000>;
qcom,iommu-faults = "non-fatal";
qcom,iommu-earlymap; /* for cont-splash */
};
smmu_sde_sec: qcom,smmu_sde_sec_cb {
compatible = "qcom,smmu_sde_sec";
iommus = <&apps_smmu 0x421 0x0>;
qcom,iommu-dma-addr-pool = <0x00020000 0xfffe0000>;
qcom,iommu-faults = "non-fatal";
qcom,iommu-vmid = <0xa>;
};
};
&mdss_mdp {
clocks =
<&gcc GCC_DISP_HF_AXI_CLK>,
<&gcc GCC_DISP_THROTTLE_CORE_CLK>,
<&dispcc DISP_CC_MDSS_AHB_CLK>,
<&dispcc DISP_CC_MDSS_MDP_CLK>,
<&dispcc DISP_CC_MDSS_VSYNC_CLK>,
<&dispcc DISP_CC_MDSS_MDP_LUT_CLK>;
clock-names = "gcc_bus", "throttle_clk", "iface_clk",
"core_clk", "vsync_clk", "lut_clk";
/* data and reg bus scale settings */
interconnects = <&mmrt_virt MASTER_MDP_PORT0 &bimc SLAVE_EBI_CH0>,
<&bimc MASTER_AMPSS_M0 &config_noc SLAVE_DISPLAY_CFG>;
interconnect-names = "qcom,sde-data-bus0", "qcom,sde-reg-bus";
};
&mdss_dsi0 {
vdda-1p2-supply = <&L18A>;
clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>,
<&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>,
<&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>,
<&dispcc DISP_CC_MDSS_PCLK0_CLK>,
<&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>,
<&dispcc DISP_CC_MDSS_ESC0_CLK>;
clock-names = "byte_clk", "byte_clk_rcg", "byte_intf_clk",
"pixel_clk", "pixel_clk_rcg", "esc_clk";
};
&mdss_dsi_phy0 {
vdda-0p9-supply = <&VDD_MX_LEVEL>;
qcom,panel-allow-phy-poweroff;
qcom,dsi-pll-ssc-en;
qcom,dsi-pll-ssc-mode = "down-spread";
memory-region = <&dfps_data_memory>;
};

4
arch/arm64/boot/dts/vendor/qcom/display/bindings/sde.txt vendored
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@ -514,6 +514,9 @@ Optional properties:
for CWB. Possible values:
"cwb" - preferred for cwb
"none" - no preference on display
-qcom,sde-mixer-cwb-mask: A u32 array of bitmask for each mixer which has CWB preference set.
The bitmask indicates the mux connections existed in HW from all
the mixers to the cwb mixer id in the list.
- qcom,sde-ctl-display-pref: A string array indicating the preferred display type
for the ctl block. Possible values:
"primary" - preferred for primary display
@ -621,6 +624,7 @@ Example:
"none", "none";
qcom,sde-mixer-cwb-pref = "none", "none",
"cwb", "none";
qcom,sde-mixer-cwb-mask = <0x0 0x0 0x5 0xa 0x11 0x22>;
qcom,sde-dspp-top-off = <0x1300>;
qcom,sde-dspp-off = <0x00055000 0x00057000>;
qcom,sde-dspp-ad-off = <0x24000 0x22800>;

22
arch/arm64/boot/dts/vendor/qcom/display/blair-sde-display-atp.dtsi vendored
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@ -1,5 +1,6 @@
/* Should extend holi-sde-display-atp.dtsi */
#include <dt-bindings/clock/mdss-5nm-pll-clk.h>
#include <dt-bindings/clock/qcom,dispcc-blair.h>
&sde_dsi {
clocks = <&mdss_dsi_phy0 BYTECLK_MUX_0_CLK>,
@ -11,12 +12,29 @@
<&mdss_dsi_phy0 SHADOW_BYTECLK_SRC_0_CLK>,
<&mdss_dsi_phy0 SHADOW_PCLK_SRC_0_CLK>,
<&mdss_dsi_phy0 SHADOW_CPHY_BYTECLK_SRC_0_CLK>,
<&mdss_dsi_phy0 SHADOW_CPHY_PCLK_SRC_0_CLK>;
<&mdss_dsi_phy0 SHADOW_CPHY_PCLK_SRC_0_CLK>,
/*
* Currently the dsi clock handles are under the dsi
* controller DT node. As soon as the controller probe
* finishes, the dispcc sync state can get called before
* the dsi_display probe potentially disturbing the clock
* votes for cont_splash use case. Hence we are no longer
* protected by the component model in this case against the
* disp cc sync state getting triggered after the dsi_ctrl
* probe. To protect against this incorrect sync state trigger
* add this dummy MDP clk vote handle to the dsi_display
* DT node. Since the dsi_display driver does not parse
* MDP clock nodes, no actual vote shall be added and this
* change is done just to satisfy sync state requirements.
*/
<&dispcc DISP_CC_MDSS_MDP_CLK>;
clock-names = "mux_byte_clk0", "mux_pixel_clk0",
"cphy_byte_clk0", "cphy_pixel_clk0",
"src_byte_clk0", "src_pixel_clk0",
"shadow_byte_clk0", "shadow_pixel_clk0",
"shadow_cphybyte_clk0", "shadow_cphypixel_clk0";
"shadow_cphybyte_clk0", "shadow_cphypixel_clk0",
"mdp_core_clk";
};
&dsi_sim_vid {

54
arch/arm64/boot/dts/vendor/qcom/display/blair-sde-display-cdp.dtsi vendored
View file

@ -1,5 +1,6 @@
/* Should extend holi-sde-display-cdp-pm6125.dtsi */
#include <dt-bindings/clock/mdss-5nm-pll-clk.h>
#include <dt-bindings/clock/qcom,dispcc-blair.h>
#include "dsi-panel-nt36672e-fhd-plus-144hz-video-cphy.dtsi"
&tlmm {
@ -56,12 +57,29 @@
<&mdss_dsi_phy0 SHADOW_BYTECLK_SRC_0_CLK>,
<&mdss_dsi_phy0 SHADOW_PCLK_SRC_0_CLK>,
<&mdss_dsi_phy0 SHADOW_CPHY_BYTECLK_SRC_0_CLK>,
<&mdss_dsi_phy0 SHADOW_CPHY_PCLK_SRC_0_CLK>;
<&mdss_dsi_phy0 SHADOW_CPHY_PCLK_SRC_0_CLK>,
/*
* Currently the dsi clock handles are under the dsi
* controller DT node. As soon as the controller probe
* finishes, the dispcc sync state can get called before
* the dsi_display probe potentially disturbing the clock
* votes for cont_splash use case. Hence we are no longer
* protected by the component model in this case against the
* disp cc sync state getting triggered after the dsi_ctrl
* probe. To protect against this incorrect sync state trigger
* add this dummy MDP clk vote handle to the dsi_display
* DT node. Since the dsi_display driver does not parse
* MDP clock nodes, no actual vote shall be added and this
* change is done just to satisfy sync state requirements.
*/
<&dispcc DISP_CC_MDSS_MDP_CLK>;
clock-names = "mux_byte_clk0", "mux_pixel_clk0",
"cphy_byte_clk0", "cphy_pixel_clk0",
"src_byte_clk0", "src_pixel_clk0",
"shadow_byte_clk0", "shadow_pixel_clk0",
"shadow_cphybyte_clk0", "shadow_cphypixel_clk0";
"shadow_cphybyte_clk0", "shadow_cphypixel_clk0",
"mdp_core_clk";
pinctrl-names = "panel_active", "panel_suspend", "pwm_pin";
pinctrl-0 = <&sde_te_active &disp_pins_reset &lcd_bias_en_active>;
@ -93,6 +111,38 @@
};
};
&dsi_r66451_amoled_cmd {
/delete-property/ qcom,mdss-dsi-t-clk-post;
/delete-property/ qcom,mdss-dsi-t-clk-pre;
qcom,mdss-dsi-display-timings {
timing@0 {
qcom,mdss-dsi-panel-phy-timings = [00 10 04 04 12 1e 04
04 03 02 04 00 0e 09];
};
timing@1 {
qcom,mdss-dsi-panel-phy-timings = [00 16 06 05 14 1f 06
06 06 02 04 00 14 0b];
};
timing@2 {
qcom,mdss-dsi-panel-phy-timings = [00 1c 08 07 17 16 07
07 08 02 04 00 19 0c];
};
};
};
&dsi_r66451_amoled_video {
/delete-property/ qcom,mdss-dsi-t-clk-post;
/delete-property/ qcom,mdss-dsi-t-clk-pre;
qcom,mdss-dsi-display-timings {
timing@0 {
qcom,mdss-dsi-panel-phy-timings = [00 1c 08 07 17 16 07
07 08 02 04 00 19 0c];
};
};
};
&dsi_rm69299_visionox_amoled_cmd {
/delete-property/ qcom,mdss-dsi-t-clk-post;
/delete-property/ qcom,mdss-dsi-t-clk-pre;

21
arch/arm64/boot/dts/vendor/qcom/display/blair-sde-display-mtp.dtsi vendored
View file

@ -1,5 +1,6 @@
/* Should extend holi-sde-display-mtp-pm6125.dtsi */
#include <dt-bindings/clock/mdss-5nm-pll-clk.h>
#include <dt-bindings/clock/qcom,dispcc-blair.h>
&sde_dsi {
clocks = <&mdss_dsi_phy0 BYTECLK_MUX_0_CLK>,
@ -11,12 +12,28 @@
<&mdss_dsi_phy0 SHADOW_BYTECLK_SRC_0_CLK>,
<&mdss_dsi_phy0 SHADOW_PCLK_SRC_0_CLK>,
<&mdss_dsi_phy0 SHADOW_CPHY_BYTECLK_SRC_0_CLK>,
<&mdss_dsi_phy0 SHADOW_CPHY_PCLK_SRC_0_CLK>;
<&mdss_dsi_phy0 SHADOW_CPHY_PCLK_SRC_0_CLK>,
/*
* Currently the dsi clock handles are under the dsi
* controller DT node. As soon as the controller probe
* finishes, the dispcc sync state can get called before
* the dsi_display probe potentially disturbing the clock
* votes for cont_splash use case. Hence we are no longer
* protected by the component model in this case against the
* disp cc sync state getting triggered after the dsi_ctrl
* probe. To protect against this incorrect sync state trigger
* add this dummy MDP clk vote handle to the dsi_display
* DT node. Since the dsi_display driver does not parse
* MDP clock nodes, no actual vote shall be added and this
* change is done just to satisfy sync state requirements.
*/
<&dispcc DISP_CC_MDSS_MDP_CLK>;
clock-names = "mux_byte_clk0", "mux_pixel_clk0",
"cphy_byte_clk0", "cphy_pixel_clk0",
"src_byte_clk0", "src_pixel_clk0",
"shadow_byte_clk0", "shadow_pixel_clk0",
"shadow_cphybyte_clk0", "shadow_cphypixel_clk0";
"shadow_cphybyte_clk0", "shadow_cphypixel_clk0",
"mdp_core_clk";
};
&dsi_sim_vid {

247
arch/arm64/boot/dts/vendor/qcom/display/dsi-panel-ili988c-dual-video.dtsi vendored Normal file
View file

@ -0,0 +1,247 @@
&mdss_mdp {
dsi_ili9881c_720p_video: qcom,mdss_dsi_ili9881c_720p_video {
qcom,mdss-dsi-panel-name = "ILI988C video signal panel";
qcom,mdss-dsi-panel-type = "dsi_video_mode";
qcom,dsi-ctrl-num = <0>;
qcom,dsi-phy-num = <0>;
qcom,mdss-dsi-virtual-channel-id = <0>;
qcom,mdss-dsi-stream = <0>;
qcom,mdss-dsi-h-left-border = <0>;
qcom,mdss-dsi-h-right-border = <0>;
qcom,mdss-dsi-v-top-border = <0>;
qcom,mdss-dsi-v-bottom-border = <0>;
qcom,mdss-dsi-bpp = <24>;
qcom,mdss-dsi-underflow-color = <0x3ff>;
qcom,mdss-dsi-border-color = <0>;
qcom,mdss-dsi-h-sync-pulse = <0>;
qcom,mdss-dsi-traffic-mode = "burst_mode";
qcom,mdss-dsi-bllp-eof-power-mode;
qcom,mdss-dsi-bllp-power-mode;
qcom,mdss-dsi-lane-0-state;
qcom,mdss-dsi-lane-1-state;
qcom,mdss-dsi-lane-2-state;
qcom,mdss-dsi-lane-3-state;
qcom,mdss-dsi-lp11-init;
qcom,mdss-dsi-dma-trigger = "trigger_sw";
qcom,mdss-dsi-mdp-trigger = "none";
qcom,mdss-pan-physical-width-dimension = <62>;
qcom,mdss-pan-physical-height-dimension = <110>;
qcom,mdss-dsi-reset-sequence = <1 20>, <0 1>, <1 20>;
qcom,mdss-dsi-display-timings {
timing@0 {
qcom,mdss-dsi-panel-width = <720>;
qcom,mdss-dsi-panel-height = <1280>;
qcom,mdss-dsi-h-front-porch = <200>;
qcom,mdss-dsi-h-back-porch = <100>;
qcom,mdss-dsi-h-pulse-width = <8>;
qcom,mdss-dsi-h-sync-skew = <0>;
qcom,mdss-dsi-v-back-porch = <24>;
qcom,mdss-dsi-v-front-porch = <24>;
qcom,mdss-dsi-v-pulse-width = <8>;
qcom,mdss-dsi-panel-framerate = <60>;
qcom,mdss-dsi-on-command = [
39 01 00 00 00 00 04 FF 98 81 03
39 01 00 00 00 00 02 01 00
39 01 00 00 00 00 02 02 00
39 01 00 00 00 00 02 03 73
39 01 00 00 00 00 02 04 00
39 01 00 00 00 00 02 05 00
39 01 00 00 00 00 02 06 0C
39 01 00 00 00 00 02 07 00
39 01 00 00 00 00 02 08 00
39 01 00 00 00 00 02 09 01
39 01 00 00 00 00 02 0A 01
39 01 00 00 00 00 02 0B 01
39 01 00 00 00 00 02 0C 01
39 01 00 00 00 00 02 0D 01
39 01 00 00 00 00 02 0E 01
39 01 00 00 00 00 02 0F 00
39 01 00 00 00 00 02 10 00
39 01 00 00 00 00 02 11 00
39 01 00 00 00 00 02 12 00
39 01 00 00 00 00 02 13 00
39 01 00 00 00 00 02 14 00
39 01 00 00 00 00 02 15 00
39 01 00 00 00 00 02 16 00
39 01 00 00 00 00 02 17 00
39 01 00 00 00 00 02 18 00
39 01 00 00 00 00 02 19 00
39 01 00 00 00 00 02 1A 00
39 01 00 00 00 00 02 1B 00
39 01 00 00 00 00 02 1C 00
39 01 00 00 00 00 02 1D 00
39 01 00 00 00 00 02 1E 44
39 01 00 00 00 00 02 1F C0
39 01 00 00 00 00 02 20 0A
39 01 00 00 00 00 02 21 03
39 01 00 00 00 00 02 22 0A
39 01 00 00 00 00 02 23 00
39 01 00 00 00 00 02 24 8C
39 01 00 00 00 00 02 25 8C
39 01 00 00 00 00 02 26 00
39 01 00 00 00 00 02 27 00
39 01 00 00 00 00 02 28 3B
39 01 00 00 00 00 02 29 03
39 01 00 00 00 00 02 2A 00
39 01 00 00 00 00 02 2B 00
39 01 00 00 00 00 02 2C 00
39 01 00 00 00 00 02 2D 00
39 01 00 00 00 00 02 2E 00
39 01 00 00 00 00 02 2F 00
39 01 00 00 00 00 02 30 00
39 01 00 00 00 00 02 31 00
39 01 00 00 00 00 02 32 00
39 01 00 00 00 00 02 33 00
39 01 00 00 00 00 02 34 00
39 01 00 00 00 00 02 35 00
39 01 00 00 00 00 02 36 00
39 01 00 00 00 00 02 37 00
39 01 00 00 00 00 02 38 00
39 01 00 00 00 00 02 39 00
39 01 00 00 00 00 02 3A 00
39 01 00 00 00 00 02 3B 00
39 01 00 00 00 00 02 3C 00
39 01 00 00 00 00 02 3D 00
39 01 00 00 00 00 02 3E 00
39 01 00 00 00 00 02 3F 00
39 01 00 00 00 00 02 40 00
39 01 00 00 00 00 02 41 00
39 01 00 00 00 00 02 42 00
39 01 00 00 00 00 02 43 00
39 01 00 00 00 00 02 44 00
39 01 00 00 00 00 02 50 01
39 01 00 00 00 00 02 51 23
39 01 00 00 00 00 02 52 45
39 01 00 00 00 00 02 53 67
39 01 00 00 00 00 02 54 89
39 01 00 00 00 00 02 55 AB
39 01 00 00 00 00 02 56 01
39 01 00 00 00 00 02 57 23
39 01 00 00 00 00 02 58 45
39 01 00 00 00 00 02 59 67
39 01 00 00 00 00 02 5A 89
39 01 00 00 00 00 02 5B AB
39 01 00 00 00 00 02 5C CD
39 01 00 00 00 00 02 5D EF
39 01 00 00 00 00 02 5E 11
39 01 00 00 00 00 02 5F 0C
39 01 00 00 00 00 02 60 0D
39 01 00 00 00 00 02 61 0E
39 01 00 00 00 00 02 62 0F
39 01 00 00 00 00 02 63 06
39 01 00 00 00 00 02 64 07
39 01 00 00 00 00 02 65 02
39 01 00 00 00 00 02 66 02
39 01 00 00 00 00 02 67 02
39 01 00 00 00 00 02 68 02
39 01 00 00 00 00 02 69 02
39 01 00 00 00 00 02 6A 02
39 01 00 00 00 00 02 6B 02
39 01 00 00 00 00 02 6C 02
39 01 00 00 00 00 02 6D 02
39 01 00 00 00 00 02 6E 02
39 01 00 00 00 00 02 6F 02
39 01 00 00 00 00 02 70 02
39 01 00 00 00 00 02 71 02
39 01 00 00 00 00 02 72 02
39 01 00 00 00 00 02 73 01
39 01 00 00 00 00 02 74 00
39 01 00 00 00 00 02 75 0C
39 01 00 00 00 00 02 76 0D
39 01 00 00 00 00 02 77 0E
39 01 00 00 00 00 02 78 0F
39 01 00 00 00 00 02 79 06
39 01 00 00 00 00 02 7A 07
39 01 00 00 00 00 02 7B 02
39 01 00 00 00 00 02 7C 02
39 01 00 00 00 00 02 7D 02
39 01 00 00 00 00 02 7E 02
39 01 00 00 00 00 02 7F 02
39 01 00 00 00 00 02 80 02
39 01 00 00 00 00 02 81 02
39 01 00 00 00 00 02 82 02
39 01 00 00 00 00 02 83 02
39 01 00 00 00 00 02 84 02
39 01 00 00 00 00 02 85 02
39 01 00 00 00 00 02 86 02
39 01 00 00 00 00 02 87 02
39 01 00 00 00 00 02 88 02
39 01 00 00 00 00 02 89 01
39 01 00 00 00 00 02 8A 00
39 01 00 00 00 00 04 FF 98 81 04
39 01 00 00 00 00 02 6C 15
39 01 00 00 00 00 02 6E 1A
39 01 00 00 00 00 02 6F A5
39 01 00 00 00 00 02 3A 24
39 01 00 00 00 00 02 8D 1F
39 01 00 00 00 00 02 87 BA
39 01 00 00 00 00 02 26 76
39 01 00 00 00 00 02 B2 D1
39 01 00 00 00 00 04 FF 98 81 01
39 01 00 00 00 00 02 22 0A
39 01 00 00 00 00 02 31 00
39 01 00 00 00 00 02 40 33
39 01 00 00 00 00 02 50 A6
39 01 00 00 00 00 02 51 A6
39 01 00 00 00 00 02 60 06
39 01 00 00 00 00 02 61 01
39 01 00 00 00 00 02 62 19
39 01 00 00 00 00 02 63 10
39 01 00 00 00 00 02 A0 1A
39 01 00 00 00 00 02 A1 1D
39 01 00 00 00 00 02 A2 2A
39 01 00 00 00 00 02 A3 10
39 01 00 00 00 00 02 A4 13
39 01 00 00 00 00 02 A5 27
39 01 00 00 00 00 02 A6 1D
39 01 00 00 00 00 02 A7 1E
39 01 00 00 00 00 02 A8 84
39 01 00 00 00 00 02 A9 1C
39 01 00 00 00 00 02 AA 27
39 01 00 00 00 00 02 AB 70
39 01 00 00 00 00 02 AC 16
39 01 00 00 00 00 02 AD 14
39 01 00 00 00 00 02 AE 49
39 01 00 00 00 00 02 AF 21
39 01 00 00 00 00 02 B0 28
39 01 00 00 00 00 02 B1 5D
39 01 00 00 00 00 02 B2 6E
39 01 00 00 00 00 02 B3 39
39 01 00 00 00 00 02 C0 03
39 01 00 00 00 00 02 C1 1D
39 01 00 00 00 00 02 C2 2A
39 01 00 00 00 00 02 C3 10
39 01 00 00 00 00 02 C4 13
39 01 00 00 00 00 02 C5 27
39 01 00 00 00 00 02 C6 1D
39 01 00 00 00 00 02 C7 1E
39 01 00 00 00 00 02 C8 84
39 01 00 00 00 00 02 C9 1C
39 01 00 00 00 00 02 CA 27
39 01 00 00 00 00 02 CB 70
39 01 00 00 00 00 02 CC 16
39 01 00 00 00 00 02 CD 14
39 01 00 00 00 00 02 CE 49
39 01 00 00 00 00 02 CF 21
39 01 00 00 00 00 02 D0 28
39 01 00 00 00 00 02 D1 5D
39 01 00 00 00 00 02 D2 6E
39 01 00 00 00 00 02 D3 39
39 01 00 00 00 00 04 FF 98 81 00
39 01 00 00 00 00 02 35 00
05 01 00 00 78 00 02 11 00
05 01 00 00 14 00 02 29 00
];
qcom,mdss-dsi-off-command = [
05 01 00 00 14 00 01 28
05 01 00 00 78 00 01 10
];
qcom,mdss-dsi-on-command-state = "dsi_lp_mode";
qcom,mdss-dsi-off-command-state = "dsi_hs_mode";
};
};
};
};

2
arch/arm64/boot/dts/vendor/qcom/display/dsi-panel-rm69090-amoled-178-cmd.dtsi vendored
View file

@ -53,6 +53,7 @@
qcom,mdss-dsi-on-command = [
15 01 00 00 00 00 02 FE 01
15 01 00 00 00 00 02 6A 03
15 01 00 00 00 00 02 2A 03
15 01 00 00 00 00 02 FE 00
15 01 00 00 00 00 02 35 00
15 01 00 00 00 00 02 51 FF
@ -80,7 +81,6 @@
15 01 00 00 00 00 02 FE 00
29 01 00 00 00 00 05 2A 00 10 01 7F
29 01 00 00 00 00 05 2B 00 00 01 BF
05 01 00 00 00 00 02 12 00
];
};
};

77
arch/arm64/boot/dts/vendor/qcom/display/dsi-panel-rm69090-amoled-178-vid.dtsi vendored Normal file
View file

@ -0,0 +1,77 @@
&mdss_mdp {
dsi_rm69090_amoled_vid: qcom,mdss_dsi_rm69090_amoled_178_vid {
qcom,mdss-dsi-panel-name =
"RM69090 1.78 amoled vid mode";
qcom,mdss-dsi-panel-type = "dsi_video_mode";
qcom,mdss-dsi-panel-physical-type = "oled";
qcom,mdss-dsi-virtual-channel-id = <0>;
qcom,mdss-dsi-stream = <0>;
qcom,mdss-dsi-bpp = <24>;
qcom,mdss-dsi-color-order = "rgb_swap_rgb";
qcom,mdss-dsi-underflow-color = <0xff>;
qcom,mdss-dsi-border-color = <0>;
qcom,dsi-ctrl-num = <0>;
qcom,dsi-phy-num = <0>;
qcom,mdss-dsi-traffic-mode = "burst_mode";
qcom,mdss-dsi-lane-map = "lane_map_0123";
qcom,mdss-dsi-bllp-eof-power-mode;
qcom,mdss-dsi-bllp-power-mode;
qcom,mdss-dsi-lane-0-state;
qcom,mdss-dsi-lane-1-state;
qcom,mdss-dsi-dma-trigger = "trigger_sw";
qcom,mdss-dsi-mdp-trigger = "none";
qcom,mdss-dsi-reset-sequence = <1 10>, <0 10>, <1 10>;
qcom,mdss-dsi-te-pin-select = <1>;
qcom,mdss-dsi-te-dcs-command = <1>;
qcom,mdss-dsi-te-check-enable;
qcom,mdss-dsi-te-using-te-pin;
qcom,mdss-dsi-t-clk-post = <0x09>;
qcom,mdss-dsi-t-clk-pre = <0x2c>;
qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
qcom,mdss-dsi-bl-min-level = <1>;
qcom,mdss-dsi-bl-max-level = <255>;
qcom,mdss-dsi-display-timings {
timing@0 {
qcom,mdss-dsi-panel-framerate = <60>;
qcom,mdss-dsi-panel-width = <368>;
qcom,mdss-dsi-panel-height = <448>;
qcom,mdss-dsi-h-front-porch = <40>;
qcom,mdss-dsi-h-back-porch = <20>;
qcom,mdss-dsi-h-pulse-width = <4>;
qcom,mdss-dsi-h-sync-skew = <0>;
qcom,mdss-dsi-v-back-porch = <8>;
qcom,mdss-dsi-v-front-porch = <6>;
qcom,mdss-dsi-v-pulse-width = <2>;
qcom,mdss-dsi-h-left-border = <0>;
qcom,mdss-dsi-h-right-border = <0>;
qcom,mdss-dsi-v-top-border = <0>;
qcom,mdss-dsi-v-bottom-border = <0>;
qcom,mdss-dsi-on-command = [
15 01 00 00 00 00 02 FE 01
15 01 00 00 00 00 02 0D 01
15 01 00 00 00 00 02 6A 03
15 01 00 00 00 00 02 FE 00
15 01 00 00 00 00 02 35 00
15 01 00 00 00 00 02 51 FF
39 01 00 00 00 00 05 2A 00 10 01 7F
39 01 00 00 00 00 05 2B 00 00 01 BF
05 01 00 00 78 00 02 11 00
05 01 00 00 40 00 02 29 00
];
qcom,mdss-dsi-off-command = [
05 01 00 00 14 00 02 28 00
05 01 00 00 78 00 02 10 00
15 01 00 00 00 00 02 4F 01];
qcom,mdss-dsi-on-command-state = "dsi_lp_mode";
qcom,mdss-dsi-off-command-state = "dsi_hs_mode";
};
};
};
};

30
arch/arm64/boot/dts/vendor/qcom/display/dsi-panel-rm6d030-amoled-141-cmd.dtsi vendored
View file

@ -51,21 +51,27 @@
qcom,mdss-dsi-v-bottom-border = <0>;
qcom,mdss-dsi-on-command = [
15 01 00 00 00 00 02 FE 20
15 01 00 00 00 00 02 5A 0E
15 01 00 00 00 00 02 58 07
15 01 00 00 00 00 02 FE 00
15 01 00 00 00 00 02 C4 80
39 01 00 00 00 00 05 2A 00 06 01 61
39 01 00 00 00 00 05 2B 00 00 01 B9
39 01 00 00 00 00 05 30 00 01 01 B8
39 01 00 00 00 00 05 31 00 07 01 60
15 01 00 00 00 00 02 35 00
39 01 00 00 00 00 05 2A 00 00 01 3F
39 01 00 00 00 00 05 2B 00 00 01 67
39 01 00 00 00 00 05 30 00 00 01 67
39 01 00 00 00 00 05 31 00 00 01 3F
15 01 00 00 00 00 02 35 02
15 01 00 00 00 00 02 53 20
15 01 00 00 00 00 02 51 FF
05 01 00 00 60 00 02 11 00
15 01 00 00 00 00 02 63 FF
05 01 00 00 00 00 02 12 00
05 01 00 00 32 00 02 11 00
05 01 00 00 00 00 02 29 00
];
qcom,mdss-dsi-off-command = [
05 01 00 00 14 00 02 28 00
05 01 00 00 78 00 02 10 00
15 01 00 00 00 00 02 4F 01];
05 01 00 00 00 00 02 28 00
05 01 00 00 53 00 02 10 00
15 01 00 00 00 00 02 4F 01
];
qcom,mdss-dsi-on-command-state = "dsi_lp_mode";
qcom,mdss-dsi-off-command-state = "dsi_hs_mode";
qcom,mdss-dsi-lp2-command = [
@ -76,8 +82,8 @@
qcom,mdss-dsi-nolp-command = [
05 01 00 00 1f 00 01 38 /* Idle-Mode Off */
15 01 00 00 00 00 02 FE 00
39 01 00 00 00 00 05 2A 00 06 01 61
39 01 00 00 00 00 05 2B 00 00 01 B9
39 01 00 00 00 00 05 2A 00 00 01 3F
39 01 00 00 00 00 05 2B 00 00 01 67
05 01 00 00 00 00 02 12 00
];
};

25
arch/arm64/boot/dts/vendor/qcom/display/holi-sde-display-cdp-pm6125.dtsi vendored
View file

@ -75,6 +75,7 @@
qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
qcom,mdss-dsi-bl-min-level = <1>;
qcom,mdss-dsi-bl-max-level = <255>;
qcom,bl-update-flag = "delay_until_first_frame";
qcom,platform-reset-gpio = <&pmr735a_gpios 2 0>;
};
@ -83,6 +84,30 @@
qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
qcom,mdss-dsi-bl-min-level = <1>;
qcom,mdss-dsi-bl-max-level = <255>;
qcom,bl-update-flag = "delay_until_first_frame";
qcom,platform-te-gpio = <&tlmm 23 0>;
qcom,platform-reset-gpio = <&pmr735a_gpios 2 0>;
};
&dsi_r66451_amoled_video {
qcom,panel-supply-entries = <&dsi_panel_pwr_supply_avdd>;
qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
qcom,mdss-dsi-bl-min-level = <1>;
qcom,mdss-brightness-max-level = <255>;
qcom,mdss-dsi-bl-inverted-dbv;
qcom,bl-update-flag = "delay_until_first_frame";
qcom,mdss-dsi-bl-max-level = <4095>;
qcom,platform-reset-gpio = <&pmr735a_gpios 2 0>;
};
&dsi_r66451_amoled_cmd {
qcom,panel-supply-entries = <&dsi_panel_pwr_supply_avdd>;
qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
qcom,mdss-dsi-bl-min-level = <1>;
qcom,mdss-brightness-max-level = <255>;
qcom,mdss-dsi-bl-max-level = <4095>;
qcom,mdss-dsi-bl-inverted-dbv;
qcom,bl-update-flag = "delay_until_first_frame";
qcom,platform-te-gpio = <&tlmm 23 0>;
qcom,platform-reset-gpio = <&pmr735a_gpios 2 0>;
};

2
arch/arm64/boot/dts/vendor/qcom/display/holi-sde-display-mtp-pm6125.dtsi vendored
View file

@ -75,6 +75,7 @@
qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
qcom,mdss-dsi-bl-min-level = <1>;
qcom,mdss-dsi-bl-max-level = <255>;
qcom,bl-update-flag = "delay_until_first_frame";
qcom,platform-reset-gpio = <&pmr735a_gpios 2 0>;
};
@ -83,6 +84,7 @@
qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
qcom,mdss-dsi-bl-min-level = <1>;
qcom,mdss-dsi-bl-max-level = <255>;
qcom,bl-update-flag = "delay_until_first_frame";
qcom,platform-te-gpio = <&tlmm 23 0>;
qcom,platform-reset-gpio = <&pmr735a_gpios 2 0>;
};

6
arch/arm64/boot/dts/vendor/qcom/display/holi-sde-display-qrd-pm6125.dtsi vendored
View file

@ -71,6 +71,7 @@
qcom,mdss-brightness-max-level = <255>;
qcom,mdss-dsi-bl-max-level = <4095>;
qcom,mdss-dsi-bl-inverted-dbv;
qcom,bl-update-flag = "delay_until_first_frame";
qcom,platform-te-gpio = <&tlmm 23 0>;
qcom,platform-reset-gpio = <&pmr735a_gpios 2 0>;
};
@ -81,6 +82,7 @@
qcom,mdss-dsi-bl-min-level = <1>;
qcom,mdss-brightness-max-level = <255>;
qcom,mdss-dsi-bl-inverted-dbv;
qcom,bl-update-flag = "delay_until_first_frame";
qcom,mdss-dsi-bl-max-level = <4095>;
qcom,platform-reset-gpio = <&pmr735a_gpios 2 0>;
};
@ -92,6 +94,7 @@
qcom,mdss-dsi-bl-max-level = <4095>;
qcom,mdss-brightness-max-level = <255>;
qcom,mdss-dsi-bl-inverted-dbv;
qcom,bl-update-flag = "delay_until_first_frame";
qcom,platform-reset-gpio = <&pmr735a_gpios 2 0>;
};
@ -102,6 +105,7 @@
qcom,mdss-dsi-bl-max-level = <4095>;
qcom,mdss-brightness-max-level = <255>;
qcom,mdss-dsi-bl-inverted-dbv;
qcom,bl-update-flag = "delay_until_first_frame";
qcom,platform-te-gpio = <&tlmm 23 0>;
qcom,platform-reset-gpio = <&pmr735a_gpios 2 0>;
};
@ -113,6 +117,7 @@
qcom,mdss-brightness-max-level = <255>;
qcom,mdss-dsi-bl-max-level = <4095>;
qcom,mdss-dsi-bl-inverted-dbv;
qcom,bl-update-flag = "delay_until_first_frame";
qcom,platform-te-gpio = <&tlmm 23 0>;
qcom,platform-reset-gpio = <&pmr735a_gpios 2 0>;
};
@ -123,6 +128,7 @@
qcom,mdss-dsi-bl-min-level = <1>;
qcom,mdss-brightness-max-level = <255>;
qcom,mdss-dsi-bl-inverted-dbv;
qcom,bl-update-flag = "delay_until_first_frame";
qcom,mdss-dsi-bl-max-level = <4095>;
qcom,platform-reset-gpio = <&pmr735a_gpios 2 0>;
};

21
arch/arm64/boot/dts/vendor/qcom/display/holi-sde-display.dtsi vendored
View file

@ -1,4 +1,5 @@
#include "holi-sde-display-common.dtsi"
#include <dt-bindings/clock/qcom,dispcc-holi.h>
&sde_dsi {
clocks = <&mdss_dsi_phy0 BYTECLK_MUX_0_CLK>,
@ -6,10 +7,26 @@
<&mdss_dsi_phy0 BYTECLK_SRC_0_CLK>,
<&mdss_dsi_phy0 PCLK_SRC_0_CLK>,
<&mdss_dsi_phy0 SHADOW_BYTECLK_SRC_0_CLK>,
<&mdss_dsi_phy0 SHADOW_PCLK_SRC_0_CLK>;
<&mdss_dsi_phy0 SHADOW_PCLK_SRC_0_CLK>,
/*
* Currently the dsi clock handles are under the dsi
* controller DT node. As soon as the controller probe
* finishes, the dispcc sync state can get called before
* the dsi_display probe potentially disturbing the clock
* votes for cont_splash use case. Hence we are no longer
* protected by the component model in this case against the
* disp cc sync state getting triggered after the dsi_ctrl
* probe. To protect against this incorrect sync state trigger
* add this dummy MDP clk vote handle to the dsi_display
* DT node. Since the dsi_display driver does not parse
* MDP clock nodes, no actual vote shall be added and this
* change is done just to satisfy sync state requirements.
*/
<&dispcc DISP_CC_MDSS_MDP_CLK>;
clock-names = "mux_byte_clk0", "mux_pixel_clk0",
"src_byte_clk0", "src_pixel_clk0",
"shadow_byte_clk0", "shadow_pixel_clk0";
"shadow_byte_clk0", "shadow_pixel_clk0",
"mdp_core_clk";
pinctrl-names = "panel_active", "panel_suspend";
pinctrl-0 = <&sde_te_active &disp_pins_default>;

85
arch/arm64/boot/dts/vendor/qcom/display/monaco-sde-display.dtsi vendored
View file

@ -1,5 +1,6 @@
#include <dt-bindings/clock/mdss-5nm-pll-clk.h>
#include "dsi-panel-rm69090-amoled-178-cmd.dtsi"
#include "dsi-panel-rm69090-amoled-178-vid.dtsi"
#include "dsi-panel-rm6d030-amoled-141-cmd.dtsi"
&soc {
@ -12,8 +13,9 @@
qcom,supply-name = "vddio";
qcom,supply-min-voltage = <1800000>;
qcom,supply-max-voltage = <2000000>;
qcom,supply-enable-load = <62000>;
qcom,supply-enable-load = <4000>;
qcom,supply-disable-load = <80>;
qcom,supply-ulp-load = <100>;
qcom,supply-post-on-sleep = <20>;
};
@ -46,8 +48,9 @@
qcom,supply-name = "vddio";
qcom,supply-min-voltage = <1800000>;
qcom,supply-max-voltage = <2000000>;
qcom,supply-enable-load = <62000>;
qcom,supply-enable-load = <4000>;
qcom,supply-disable-load = <80>;
qcom,supply-ulp-load = <100>;
qcom,supply-post-on-sleep = <20>;
};
};
@ -56,6 +59,31 @@
#address-cells = <1>;
#size-cells = <0>;
qcom,panel-supply-entry@0 {
reg = <0>;
qcom,supply-name = "vddio";
qcom,supply-min-voltage = <1800000>;
qcom,supply-max-voltage = <2000000>;
qcom,supply-enable-load = <4000>;
qcom,supply-disable-load = <80>;
qcom,supply-ulp-load = <100>;
qcom,supply-post-on-sleep = <20>;
};
qcom,panel-supply-entry@1 {
reg = <1>;
qcom,supply-name = "vdda-3p3";
qcom,supply-min-voltage = <3000000>;
qcom,supply-max-voltage = <3000000>;
qcom,supply-enable-load = <13200>;
qcom,supply-disable-load = <80>;
};
};
dsi_panel_pwr_supply_nolab_amoled: dsi_panel_pwr_supply_nolab_amoled {
#address-cells = <1>;
#size-cells = <0>;
qcom,panel-supply-entry@0 {
reg = <0>;
qcom,supply-name = "vddio";
@ -68,14 +96,22 @@
qcom,panel-supply-entry@1 {
reg = <1>;
qcom,supply-name = "vdda-3p3";
qcom,supply-min-voltage = <3000000>;
qcom,supply-max-voltage = <3000000>;
qcom,supply-enable-load = <13200>;
qcom,supply-disable-load = <80>;
qcom,supply-name = "ibb";
qcom,supply-min-voltage = <4600000>;
qcom,supply-max-voltage = <6000000>;
qcom,supply-enable-load = <0>;
qcom,supply-disable-load = <0>;
qcom,supply-post-on-sleep = <20>;
};
};
display_panel_ibb: display_panel_ibb_stub {
compatible = "qcom,stub-regulator";
regulator-name = "display_panel_ibb";
regulator-min-microvolt = <4600000>;
regulator-max-microvolt = <6000000>;
};
sde_dsi: qcom,dsi-display-primary {
compatible = "qcom,dsi-display";
label = "primary";
@ -105,6 +141,7 @@
qcom,platform-te-gpio = <&tlmm 73 0>;
qcom,panel-te-source = <0>;
vddio-supply = <&L21A>;
ibb-supply = <&display_panel_ibb>;
qcom,mdp = <&mdss_mdp>;
qcom,dsi-default-panel =
@ -117,12 +154,20 @@
};
&dsi_rm69090_amoled_cmd {
qcom,ulps-enabled;
qcom,mdss-dsi-t-clk-post = <0x08>;
qcom,mdss-dsi-t-clk-pre = <0x0B>;
qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0", /*TODO: check these*/
"src_byte_clk0", "src_pixel_clk0",
"shadow_byte_clk0", "shadow_pixel_clk0";
qcom,mdss-dsi-panel-status-check-mode = "reg_read";
qcom,mdss-dsi-panel-status-command = [06 01 00 01 00 00 01 0a];
qcom,mdss-dsi-panel-status-command-state = "dsi_lp_mode";
qcom,mdss-dsi-panel-status-value = <0x9c>;
qcom,mdss-dsi-panel-status-read-length = <1>;
qcom,esd-check-enabled;
qcom,mdss-dsi-display-timings {
timing@0 {
qcom,mdss-dsi-panel-phy-timings = [00 0C 03 03 10 1D 03
@ -133,7 +178,33 @@
};
};
&dsi_rm69090_amoled_vid {
qcom,ulps-enabled;
qcom,mdss-dsi-t-clk-post = <0x07>;
qcom,mdss-dsi-t-clk-pre = <0x09>;
qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0",
"src_byte_clk0", "src_pixel_clk0",
"shadow_byte_clk0", "shadow_pixel_clk0";
qcom,mdss-dsi-panel-status-check-mode = "reg_read";
qcom,mdss-dsi-panel-status-command = [06 01 00 01 00 00 01 0a];
qcom,mdss-dsi-panel-status-command-state = "dsi_lp_mode";
qcom,mdss-dsi-panel-status-value = <0x9c>;
qcom,mdss-dsi-panel-status-read-length = <1>;
qcom,esd-check-enabled;
qcom,mdss-dsi-display-timings {
timing@0 {
qcom,mdss-dsi-panel-phy-timings = [00 0A 01 02 0E 1B 02
02 02 01 02 04 09 07];
qcom,display-topology = <1 0 1>;
qcom,default-topology-index = <0>;
};
};
};
&dsi_rm6d030_amoled_cmd {
qcom,ulps-enabled;
qcom,mdss-dsi-t-clk-post = <0x07>;
qcom,mdss-dsi-t-clk-pre = <0x0A>;
qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0",

3
arch/arm64/boot/dts/vendor/qcom/display/monaco-sde.dtsi vendored
View file

@ -266,6 +266,7 @@
qcom,supply-max-voltage = <1312000>;
qcom,supply-enable-load = <21800>;
qcom,supply-disable-load = <0>;
qcom,supply-ulp-load = <0>;
};
};
@ -308,6 +309,7 @@
00 00 0a 0a
00 00 8a 8a];
qcom,platform-regulator-settings = [1d 1d 1d 1d 1d];
qcom,phy-clamp-enable;
qcom,panel-allow-phy-poweroff;
qcom,dsi-pll-ssc-en;
qcom,dsi-pll-ssc-mode = "down-spread";
@ -321,6 +323,7 @@
qcom,supply-max-voltage = <904000>;
qcom,supply-enable-load = <37550>;
qcom,supply-disable-load = <0>;
qcom,supply-ulp-load = <0>;
};
};
};

276
arch/arm64/boot/dts/vendor/qcom/display/scuba-sde-common.dtsi vendored Normal file
View file

@ -0,0 +1,276 @@
#include <dt-bindings/clock/mdss-14nm-pll-clk.h>
&soc {
mdss_mdp: qcom,mdss_mdp {
compatible = "qcom,sde-kms";
reg = <0x5e00000 0x8f030>,
<0x5eb0000 0x2008>,
<0x5e8f000 0x02c>,
<0xc125ba4 0x20>;
reg-names = "mdp_phys",
"vbif_phys",
"sid_phys",
"sde_imem_phys";
clock-rate = <0 0 0 300000000 19200000 192000000>;
clock-max-rate = <0 0 0 400000000 19200000 400000000>;
sde-vdd-supply = <&mdss_core_gdsc>;
/* Enable thermal cooling device */
#cooling-cells = <2>;
/* interrupt config */
interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>;
interrupt-controller;
#interrupt-cells = <1>;
#power-domain-cells = <0>;
/* hw blocks */
qcom,sde-off = <0x1000>;
qcom,sde-len = <0x494>;
qcom,sde-ctl-off = <0x2000>;
qcom,sde-ctl-size = <0x1dc>;
qcom,sde-ctl-display-pref = "primary";
qcom,sde-mixer-off = <0x45000>;
qcom,sde-mixer-size = <0x320>;
qcom,sde-mixer-display-pref = "primary";
qcom,sde-dspp-top-off = <0x1300>;
qcom,sde-dspp-top-size = <0x80>;
qcom,sde-dspp-off = <0x55000>;
qcom,sde-dspp-size = <0xfe4>;
qcom,sde-intf-off = <0x0 0x6b800>;
qcom,sde-intf-size = <0x2b8>;
qcom,sde-intf-type = "none", "dsi";
qcom,sde-pp-off = <0x71000>;
qcom,sde-pp-size = <0xd4>;
qcom,sde-dither-off = <0x30e0>;
qcom,sde-dither-version = <0x00010000>;
qcom,sde-dither-size = <0x20>;
qcom,sde-sspp-type = "vig", "dma";
qcom,sde-sspp-off = <0x5000 0x25000>;
qcom,sde-sspp-src-size = <0x1f8>;
qcom,sde-sspp-xin-id = <0 1>;
qcom,sde-sspp-excl-rect = <1 1>;
qcom,sde-sspp-smart-dma-priority = <2 1>;
qcom,sde-smart-dma-rev = "smart_dma_v2p5";
qcom,sde-mixer-pair-mask = <0>;
qcom,sde-mixer-blend-op-off = <0x20 0x38 0x50 0x68 0x80 0x98
0xb0 0xc8 0xe0 0xf8 0x110>;
qcom,sde-mixer-stage-base-layer;
qcom,sde-max-per-pipe-bw-kbps = <2700000 2700000>;
qcom,sde-max-per-pipe-bw-high-kbps = <2700000 2700000>;
/* offsets are relative to "mdp_phys + qcom,sde-off */
qcom,sde-sspp-clk-ctrl = <0x2ac 0>, <0x2ac 8>;
qcom,sde-mixer-linewidth = <2048>;
qcom,sde-mixer-blendstages = <0x4>;
qcom,sde-panic-per-pipe;
qcom,sde-has-cdp;
qcom,sde-has-dim-layer;
qcom,sde-has-idle-pc;
qcom,sde-max-bw-low-kbps = <2700000>;
qcom,sde-max-bw-high-kbps = <2700000>;
qcom,sde-min-core-ib-kbps = <1300000>;
qcom,sde-min-llcc-ib-kbps = <0>;
qcom,sde-min-dram-ib-kbps = <1600000>;
qcom,sde-dram-channels = <2>;
qcom,sde-num-nrt-paths = <0>;
qcom,sde-vbif-off = <0>;
qcom,sde-vbif-size = <0x2008>;
qcom,sde-vbif-id = <0>;
qcom,sde-vbif-memtype-0 = <3 3 3 3 3 3 3 3>;
qcom,sde-vbif-memtype-1 = <3 3 3 3 3 3>;
qcom,sde-vbif-qos-rt-remap = <3 3 4 4 5 5 6 6>;
/*Pending macrotile & macrotile-qseed has the same configs */
qcom,sde-danger-lut = <0x000000ff 0x00000000
0x00000000 0x00000000 0x00000000>;
qcom,sde-safe-lut-linear = <0 0xfff0>;
qcom,sde-qos-lut-linear = <0 0x00112222 0x22335777>;
qcom,sde-cdp-setting = <1 0>;
qcom,sde-qos-cpu-mask = <0x3>;
qcom,sde-qos-cpu-dma-latency = <300>;
qcom,sde-secure-sid-mask = <0x0000421>;
qcom,sde-num-mnoc-ports = <1>;
qcom,sde-axi-bus-width = <16>;
qcom,sde-reg-bus,vectors-KBps = <0 0>,
<0 76800>,
<0 150000>,
<0 300000>;
qcom,sde-sspp-vig-blocks {
};
qcom,sde-dspp-blocks {
qcom,sde-dspp-igc = <0x0 0x00030001>;
qcom,sde-dspp-hsic = <0x800 0x00010007>;
qcom,sde-dspp-memcolor = <0x880 0x00010007>;
qcom,sde-dspp-hist = <0x800 0x00010007>;
qcom,sde-dspp-sixzone= <0x900 0x00010007>;
qcom,sde-dspp-vlut = <0xa00 0x00010008>;
qcom,sde-dspp-pcc = <0x1700 0x00040000>;
qcom,sde-dspp-gc = <0x17c0 0x00010008>;
qcom,sde-dspp-dither = <0x82c 0x00010007>;
};
qcom,platform-supply-entries {
#address-cells = <1>;
#size-cells = <0>;
qcom,platform-supply-entry@0 {
reg = <0>;
qcom,supply-name = "sde-vdd";
qcom,supply-min-voltage = <0>;
qcom,supply-max-voltage = <0>;
qcom,supply-enable-load = <0>;
qcom,supply-disable-load = <0>;
};
};
/* data and reg bus scale settings */
qcom,sde-data-bus {
qcom,msm-bus,name = "mdss_sde";
qcom,msm-bus,num-cases = <3>;
qcom,msm-bus,num-paths = <1>;
qcom,msm-bus,vectors-KBps =
<22 512 0 0>,
<22 512 0 4800000>,
<22 512 0 4800000>;
};
qcom,sde-limits {
qcom,sde-linewidth-limits {
qcom,sde-limit-name = "sspp_linewidth_usecases";
qcom,sde-limit-cases = "vig", "dma";
qcom,sde-limit-ids= <0x1 0x2>;
qcom,sde-limit-values = <0x1 2160>,
<0x2 2160>;
};
qcom,sde-bw-limits {
qcom,sde-limit-name = "sde_bwlimit_usecases";
qcom,sde-limit-cases = "per_vig_pipe",
"per_dma_pipe",
"total_max_bw",
"camera_concurrency";
qcom,sde-limit-ids = <0x1 0x2 0x4 0x8>;
qcom,sde-limit-values = <0x1 2700000>,
<0x9 2700000>,
<0x2 2700000>,
<0xa 2700000>,
<0x4 2700000>,
<0xc 2700000>;
};
};
};
mdss_dsi0: qcom,mdss_dsi_ctrl0@5e94000 {
compatible = "qcom,dsi-ctrl-hw-v2.4";
label = "dsi-ctrl-0";
cell-index = <0>;
frame-threshold-time-us = <800>;
reg = <0x5e94000 0x400>,
<0x5f08000 0x4>;
reg-names = "dsi_ctrl", "disp_cc_base";
interrupt-parent = <&mdss_mdp>;
interrupts = <4 0>;
qcom,ctrl-supply-entries {
#address-cells = <1>;
#size-cells = <0>;
qcom,ctrl-supply-entry@0 {
reg = <0>;
qcom,supply-name = "vdda-1p2";
qcom,supply-min-voltage = <1232000>;
qcom,supply-max-voltage = <1312000>;
qcom,supply-enable-load = <21800>;
qcom,supply-disable-load = <0>;
};
};
qcom,core-supply-entries {
#address-cells = <1>;
#size-cells = <0>;
qcom,core-supply-entry@0 {
reg = <0>;
qcom,supply-name = "refgen";
qcom,supply-min-voltage = <0>;
qcom,supply-max-voltage = <0>;
qcom,supply-enable-load = <0>;
qcom,supply-disable-load = <0>;
};
};
};
mdss_dsi_phy0: qcom,mdss_dsi_phy0 {
compatible = "qcom,dsi-phy-v2.0";
label = "dsi-phy-0";
cell-index = <0>;
#clock-cells = <1>;
reg = <0x5e94400 0x588>,
<0x5e01400 0x100>,
<0x5e94200 0x100>,
<0x5e94400 0x588>,
<0x5f03000 0x8>;
reg-names = "dsi_phy", "phy_clamp_base",
"dyn_refresh_base", "pll_base", "gdsc_base";
pll-label = "dsi_pll_14nm";
qcom,platform-strength-ctrl = [ff 06
ff 06
ff 06
ff 06
ff 00];
qcom,platform-lane-config = [00 00 10 0f
00 00 10 0f
00 00 10 0f
00 00 10 0f
00 00 10 8f];
qcom,platform-regulator-settings = [1d 1d 1d 1d 1d];
qcom,phy-supply-entries {
#address-cells = <1>;
#size-cells = <0>;
qcom,phy-supply-entry@0 {
reg = <0>;
qcom,supply-name = "vdda-0p9";
qcom,supply-min-voltage =
<RPM_SMD_REGULATOR_LEVEL_NOM>;
qcom,supply-max-voltage =
<RPM_SMD_REGULATOR_LEVEL_TURBO_NO_CPR>;
qcom,supply-off-min-voltage =
<RPM_SMD_REGULATOR_LEVEL_RETENTION>;
qcom,supply-enable-load = <0>;
qcom,supply-disable-load = <0>;
};
};
};
};

58
arch/arm64/boot/dts/vendor/qcom/display/scuba-sde-display-common.dtsi vendored Normal file
View file

@ -0,0 +1,58 @@
#include "dsi-panel-ext-bridge-1080p.dtsi"
#include "dsi-panel-ili988c-dual-video.dtsi"
#include <dt-bindings/clock/mdss-14nm-pll-clk.h>
&soc {
dsi_panel_pwr_supply_no_labibb: dsi_panel_pwr_supply_no_labibb {
#address-cells = <1>;
#size-cells = <0>;
qcom,panel-supply-entry@0 {
reg = <0>;
qcom,supply-name = "vddio";
qcom,supply-min-voltage = <1800000>;
qcom,supply-max-voltage = <2000000>;
qcom,supply-enable-load = <62000>;
qcom,supply-disable-load = <80>;
qcom,supply-post-on-sleep = <20>;
};
};
sde_dsi: qcom,dsi-display-primary {
compatible = "qcom,dsi-display";
label = "primary";
qcom,dsi-ctrl = <&mdss_dsi0>;
qcom,dsi-phy = <&mdss_dsi_phy0>;
qcom,mdp = <&mdss_mdp>;
qcom,dsi-default-panel = <&dsi_ili9881c_720p_video>;
};
};
&dsi_ext_bridge_1080p {
qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0",
"src_byte_clk0", "src_pixel_clk0",
"shadow_byte_clk0", "shadow_pixel_clk0";
};
&dsi_ili9881c_720p_video {
qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0",
"src_byte_clk0", "src_pixel_clk0",
"shadow_byte_clk0", "shadow_pixel_clk0";
qcom,mdss-dsi-t-clk-post = <0x0a>;
qcom,mdss-dsi-t-clk-pre = <0x21>;
qcom,mdss-dsi-display-timings {
timing@0 {
qcom,mdss-dsi-panel-timings = [
1F 1C 04 06 03 02 0a
1F 1C 04 06 03 02 0a
1F 1C 04 06 03 02 0a
1F 1C 04 06 03 02 0a
1F 10 04 06 03 02 0a
];
qcom,display-topology = <1 0 1>;
qcom,default-topology-index = <0>;
};
};
};

19
arch/arm64/boot/dts/vendor/qcom/display/scuba-sde-display-qrd.dtsi vendored Normal file
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#include "scuba-sde-display.dtsi"
&dsi_ili9881c_720p_video {
qcom,panel-supply-entries = <&dsi_panel_pwr_supply_no_labibb>;
qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_pwm";
pwms = <&pm2250_pwm3 0 0>;
qcom,bl-pmic-pwm-period-usecs = <100>;
qcom,mdss-dsi-bl-min-level = <1>;
qcom,mdss-dsi-bl-max-level = <4095>;
qcom,platform-te-gpio = <&tlmm 40 0>;
qcom,platform-reset-gpio = <&ioexp21 2 0>;
qcom,platform-reset-gpio-always-on;
qcom,platform-bklight-en-gpio = <&ioexp21 3 0>;
qcom,platform-en-gpio = <&ioexp22 6 0>;
};
&sde_dsi {
qcom,dsi-default-panel = <&dsi_ili9881c_720p_video>;
};

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arch/arm64/boot/dts/vendor/qcom/display/scuba-sde-display.dtsi vendored Normal file
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#include "scuba-sde-display-common.dtsi"
#include <dt-bindings/clock/qcom,dispcc-scuba.h>
&sde_dsi {
clocks = <&mdss_dsi_phy0 BYTE0_MUX_CLK>,
<&mdss_dsi_phy0 PIX0_MUX_CLK>,
<&mdss_dsi_phy0 BYTE0_SRC_CLK>,
<&mdss_dsi_phy0 PIX0_SRC_CLK>,
<&mdss_dsi_phy0 SHADOW_BYTE0_SRC_CLK>,
<&mdss_dsi_phy0 SHADOW_PIX0_SRC_CLK>;
clock-names = "mux_byte_clk0", "mux_pixel_clk0",
"src_byte_clk0", "src_pixel_clk0",
"shadow_byte_clk0", "shadow_pixel_clk0";
pinctrl-names = "panel_active", "panel_suspend";
pinctrl-0 = <&sde_dsi_active &sde_te_active>;
pinctrl-1 = <&sde_dsi_suspend &sde_te_suspend>;
qcom,platform-te-gpio = <&tlmm 40 0>;
qcom,panel-te-source = <0>;
vddio-supply = <&L15A>;
};
&mdss_mdp {
connectors = <&smmu_sde_unsec &sde_dsi>;
};

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arch/arm64/boot/dts/vendor/qcom/display/scuba-sde.dtsi vendored Normal file
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#include "scuba-sde-common.dtsi"
#include <dt-bindings/clock/mdss-14nm-pll-clk.h>
&soc {
smmu_sde_unsec: qcom,smmu_sde_unsec_cb {
compatible = "qcom,smmu_sde_unsec";
iommus = <&apps_smmu 0x420 0x2>;
qcom,iommu-dma-addr-pool = <0x00020000 0xfffe0000>;
qcom,iommu-faults = "non-fatal";
qcom,iommu-earlymap; /* for cont-splash */
};
smmu_sde_sec: qcom,smmu_sde_sec_cb {
compatible = "qcom,smmu_sde_sec";
iommus = <&apps_smmu 0x421 0x0>;
qcom,iommu-dma-addr-pool = <0x00020000 0xfffe0000>;
qcom,iommu-faults = "non-fatal";
qcom,iommu-vmid = <0xa>;
};
};
&mdss_mdp {
clocks =
<&gcc GCC_DISP_HF_AXI_CLK>,
<&gcc GCC_DISP_THROTTLE_CORE_CLK>,
<&dispcc DISP_CC_MDSS_AHB_CLK>,
<&dispcc DISP_CC_MDSS_MDP_CLK>,
<&dispcc DISP_CC_MDSS_VSYNC_CLK>,
<&dispcc DISP_CC_MDSS_MDP_LUT_CLK>;
clock-names = "gcc_bus", "throttle_clk", "iface_clk",
"core_clk", "vsync_clk", "lut_clk";
/* data and reg bus scale settings */
interconnects = <&mmrt_virt MASTER_MDP_PORT0 &bimc SLAVE_EBI_CH0>,
<&bimc MASTER_AMPSS_M0 &config_noc SLAVE_DISPLAY_CFG>;
interconnect-names = "qcom,sde-data-bus0", "qcom,sde-reg-bus";
};
&mdss_dsi0 {
vdda-1p2-supply = <&L5A>;
clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>,
<&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>,
<&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>,
<&dispcc DISP_CC_MDSS_PCLK0_CLK>,
<&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>,
<&dispcc DISP_CC_MDSS_ESC0_CLK>;
clock-names = "byte_clk", "byte_clk_rcg", "byte_intf_clk",
"pixel_clk", "pixel_clk_rcg", "esc_clk";
};
&mdss_dsi_phy0 {
vdda-0p9-supply = <&VDD_MX_LEVEL>;
qcom,panel-allow-phy-poweroff;
qcom,dsi-pll-ssc-en;
qcom,dsi-pll-ssc-mode = "down-spread";
memory-region = <&dfps_data_memory>;
};

2
arch/arm64/boot/dts/vendor/qcom/display/sdxlemur-qpic-display.dtsi vendored
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@ -5,7 +5,7 @@
reg = <0x1b00000 0x24000>;
reg-names = "qpic_base";
interrupts = <0 75 0>;
interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "qpic_irq";
interconnect-names = "qpic-display-data-bus";

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arch/arm64/boot/dts/vendor/qcom/display/sm6150-sde-display.dtsi vendored Normal file
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#include <dt-bindings/clock/mdss-14nm-pll-clk.h>
#include "dsi-panel-ili988c-dual-video.dtsi"
#include "dsi-panel-ext-bridge-1080p.dtsi"
&soc {
dsi_panel_pwr_supply: dsi_panel_pwr_supply {
#address-cells = <1>;
#size-cells = <0>;
qcom,panel-supply-entry@0 {
reg = <0>;
qcom,supply-name = "vddio";
qcom,supply-min-voltage = <1800000>;
qcom,supply-max-voltage = <1800000>;
qcom,supply-enable-load = <62000>;
qcom,supply-disable-load = <80>;
qcom,supply-post-on-sleep = <20>;
};
qcom,panel-supply-entry@1 {
reg = <1>;
qcom,supply-name = "lab";
qcom,supply-min-voltage = <4600000>;
qcom,supply-max-voltage = <6000000>;
qcom,supply-enable-load = <100000>;
qcom,supply-disable-load = <100>;
};
qcom,panel-supply-entry@2 {
reg = <2>;
qcom,supply-name = "ibb";
qcom,supply-min-voltage = <4600000>;
qcom,supply-max-voltage = <6000000>;
qcom,supply-enable-load = <100000>;
qcom,supply-disable-load = <100>;
qcom,supply-post-on-sleep = <20>;
};
};
dsi_panel_pwr_supply_no_labibb: dsi_panel_pwr_supply_no_labibb {
#address-cells = <1>;
#size-cells = <0>;
qcom,panel-supply-entry@0 {
reg = <0>;
qcom,supply-name = "vddio";
qcom,supply-min-voltage = <1800000>;
qcom,supply-max-voltage = <1800000>;
qcom,supply-enable-load = <62000>;
qcom,supply-disable-load = <80>;
qcom,supply-post-on-sleep = <20>;
};
};
dsi_panel_pwr_supply_labibb_amoled: dsi_panel_pwr_supply_labibb_amoled {
#address-cells = <1>;
#size-cells = <0>;
qcom,panel-supply-entry@0 {
reg = <0>;
qcom,supply-name = "vddio";
qcom,supply-min-voltage = <1800000>;
qcom,supply-max-voltage = <1800000>;
qcom,supply-enable-load = <62000>;
qcom,supply-disable-load = <80>;
qcom,supply-post-on-sleep = <20>;
};
qcom,panel-supply-entry@1 {
reg = <1>;
qcom,supply-name = "vdda-3p3";
qcom,supply-min-voltage = <3000000>;
qcom,supply-max-voltage = <3000000>;
qcom,supply-enable-load = <13200>;
qcom,supply-disable-load = <80>;
};
};
sde_dsi: qcom,dsi-display {
compatible = "qcom,dsi-display";
label = "primary";
qcom,dsi-ctrl = <&mdss_dsi0>;
qcom,dsi-phy = <&mdss_dsi_phy0>;
clocks = <&mdss_dsi_phy0 BYTE0_MUX_CLK>,
<&mdss_dsi_phy0 PIX0_MUX_CLK>,
<&mdss_dsi_phy0 BYTE0_SRC_CLK>,
<&mdss_dsi_phy0 PIX0_SRC_CLK>,
<&mdss_dsi_phy0 SHADOW_BYTE0_SRC_CLK>,
<&mdss_dsi_phy0 SHADOW_PIX0_SRC_CLK>;
clock-names = "mux_byte_clk0", "mux_pixel_clk0",
"src_byte_clk0", "src_pixel_clk0",
"shadow_byte_clk0", "shadow_pixel_clk0";
pinctrl-names = "panel_active", "panel_suspend";
pinctrl-0 = <&sde_dsi_active &sde_te_active>;
pinctrl-1 = <&sde_dsi_suspend &sde_te_suspend>;
qcom,platform-te-gpio = <&tlmm 90 0>;
qcom,panel-te-source = <0>;
vddio-supply = <&pm6150_l13>;
vdda-3p3-supply = <&pm6150_l18>;
lab-supply = <&lcdb_ldo_vreg>;
ibb-supply = <&lcdb_ncp_vreg>;
qcom,dsi-default-panel = <&dsi_ili9881c_720p_video>;
qcom,mdp = <&mdss_mdp>;
};
sde_wb: qcom,wb-display@0 {
compatible = "qcom,wb-display";
cell-index = <0>;
label = "wb_display";
};
};
&sde_dp {
qcom,dp-usbpd-detection = <&pm6150_pdphy>;
hpd-pwr-supply = <&pm6150_l17>;
qcom,phy-supply-entries {
#address-cells = <1>;
#size-cells = <0>;
qcom,phy-supply-entry@0 {
reg = <0>;
qcom,supply-name = "vdda-0p9";
qcom,supply-min-voltage = <880000>;
qcom,supply-max-voltage = <975000>;
qcom,supply-enable-load = <36000>;
qcom,supply-disable-load = <0>;
};
qcom,phy-supply-entry@1 {
reg = <1>;
qcom,supply-name = "hpd-pwr";
qcom,supply-min-voltage = <3000000>;
qcom,supply-max-voltage = <3230000>;
qcom,supply-enable-load = <30000>;
qcom,supply-disable-load = <0>;
};
};
};
&mdss_mdp {
connectors = <&smmu_sde_unsec &smmu_sde_sec &sde_rscc &sde_wb &sde_dp &sde_dsi>;
};
&dsi_ili9881c_720p_video {
qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0",
"src_byte_clk0", "src_pixel_clk0",
"shadow_byte_clk0", "shadow_pixel_clk0";
qcom,mdss-dsi-t-clk-post = <0x0a>;
qcom,mdss-dsi-t-clk-pre = <0x21>;
qcom,mdss-dsi-display-timings {
timing@0 {
qcom,mdss-dsi-panel-timings =
[1F 1C 04 06 03 02 0a
1F 1C 04 06 03 02 0a
1F 1C 04 06 03 02 0a
1F 1C 04 06 03 02 0a
1F 10 04 06 03 02 0a];
qcom,display-topology = <1 0 1>;
qcom,default-topology-index = <0>;
};
};
};
&dsi_ext_bridge_1080p {
qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0",
"src_byte_clk0", "src_pixel_clk0",
"shadow_byte_clk0", "shadow_pixel_clk0";
qcom,mdss-dsi-display-timings {
timing@0{
qcom,mdss-dsi-panel-phy-timings =
[24 1f 08 09 05 03 04 a0
24 1f 08 09 05 03 04 a0
24 1f 08 09 05 03 04 a0
24 1f 08 09 05 03 04 a0
24 1b 08 09 05 03 04 a0];
qcom,display-topology = <1 0 1>;
qcom,default-topology-index = <0>;
};
};
};

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arch/arm64/boot/dts/vendor/qcom/display/sm6150-sde-pll.dtsi vendored Normal file
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&soc {
mdss_dsi0_pll: qcom,mdss_dsi_pll@ae94400 {
status = "disabled";
compatible = "qcom,dsi-phy-v2.0";
};
mdss_dp_pll: qcom,mdss_dp_pll@88e9000 {
status = "disabled";
compatible = "qcom,dp-display";
};
};

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arch/arm64/boot/dts/vendor/qcom/display/sm6150-sde.dtsi vendored Normal file
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#include <dt-bindings/clock/mdss-14nm-pll-clk.h>
&soc {
mdss_mdp: qcom,mdss_mdp@ae00000 {
compatible = "qcom,sde-kms";
reg = <0x0ae00000 0x84208>,
<0x0aeb0000 0x2008>,
<0x0aeac000 0x214>;
reg-names = "mdp_phys",
"vbif_phys",
"regdma_phys";
clocks =
<&gcc GCC_DISP_AHB_CLK>,
<&gcc GCC_DISP_HF_AXI_CLK>,
<&dispcc DISP_CC_MDSS_AHB_CLK>,
<&dispcc DISP_CC_MDSS_MDP_CLK>,
<&dispcc DISP_CC_MDSS_VSYNC_CLK>,
<&dispcc DISP_CC_MDSS_MDP_LUT_CLK>,
<&dispcc DISP_CC_MDSS_ROT_CLK>;
clock-names = "gcc_iface", "gcc_bus",
"iface_clk", "core_clk", "vsync_clk",
"lut_clk", "rot_clk";
clock-rate = <0 0 0 256000000 19200000 192000000>;
clock-max-rate = <0 0 0 307000000 19200000 307000000>;
/* Enable thermal cooling device */
#cooling-cells = <2>;
/* interrupt config */
interrupts = <0 83 IRQ_TYPE_LEVEL_HIGH>;
interrupt-controller;
#interrupt-cells = <1>;
/* hw blocks */
qcom,sde-off = <0x1000>;
qcom,sde-len = <0x45c>;
qcom,sde-ctl-off = <0x2000 0x2200 0x2400
0x0 0x0 0x0>;
qcom,sde-ctl-size = <0x1e0>;
qcom,sde-ctl-display-pref = "primary", "none", "none",
"none", "none", "none";
qcom,sde-mixer-off = <0x45000 0x46000 0x47000
0x0 0x0 0x0>;
qcom,sde-mixer-size = <0x320>;
qcom,sde-mixer-display-pref = "primary", "none", "none",
"none", "none", "none";
qcom,sde-mixer-cwb-pref = "none", "none", "cwb",
"none", "none", "none";
qcom,sde-dspp-top-off = <0x1300>;
qcom,sde-dspp-top-size = <0x80>;
qcom,sde-dspp-off = <0x55000>;
qcom,sde-dspp-size = <0x1800>;
qcom,sde-wb-off = <0x66000>;
qcom,sde-wb-size = <0x2c8>;
qcom,sde-wb-xin-id = <6>;
qcom,sde-wb-id = <2>;
qcom,sde-wb-clk-ctrl = <0x3b8 24>;
qcom,sde-intf-off = <0x6b000 0x6b800 0x6c000
0x6c800>;
qcom,sde-intf-size = <0x2b8>;
qcom,sde-intf-type = "dp", "dsi","none", "dp";
qcom,sde-pp-off = <0x71000 0x71800
0x72000>;
qcom,sde-pp-slave = <0x0 0x0 0x0>;
qcom,sde-pp-size = <0xd4>;
qcom,sde-te2-off = <0x2000 0x2000 0x0>;
qcom,sde-cdm-off = <0x7a200>;
qcom,sde-cdm-size = <0x224>;
qcom,sde-dither-off = <0x30e0 0x30e0 0x30e0 0x30e0>;
qcom,sde-dither-version = <0x00010000>;
qcom,sde-dither-size = <0x20>;
qcom,sde-sspp-type = "vig", "dma", "dma", "dma", "dma";
qcom,sde-sspp-off = <0x5000 0x25000 0x27000 0x29000
0x2b000>;
qcom,sde-sspp-src-size = <0x1f0>;
qcom,sde-sspp-xin-id = <0 1 5 9 13>;
qcom,sde-sspp-excl-rect = <1 1 1 1 1>;
qcom,sde-sspp-smart-dma-priority = <5 1 2 3 4>;
qcom,sde-smart-dma-rev = "smart_dma_v2p5";
qcom,sde-mixer-pair-mask = <3 0 1 0 0 0>;
qcom,sde-mixer-blend-op-off = <0x20 0x38 0x50 0x68 0x80 0x98
0xb0 0xc8 0xe0 0xf8 0x110>;
qcom,sde-max-per-pipe-bw-kbps = <4500000
4500000 4500000
4500000 4500000>;
/* offsets are relative to "mdp_phys + qcom,sde-off */
qcom,sde-sspp-clk-ctrl =
<0x2ac 0>, <0x2ac 8>, <0x2b4 8>, <0x2bc 8>,
<0x2c4 8>;
qcom,sde-sspp-csc-off = <0x1a00>;
qcom,sde-csc-type = "csc-10bit";
qcom,sde-qseed-type = "qseedv3lite";
qcom,sde-sspp-qseed-off = <0xa00>;
qcom,sde-mixer-linewidth = <2560>;
qcom,sde-sspp-linewidth = <2160>;
qcom,sde-wb-linewidth = <2160>;
qcom,sde-mixer-blendstages = <0x9>;
qcom,sde-highest-bank-bit = <0x1>;
qcom,sde-ubwc-version = <0x200>;
qcom,sde-panic-per-pipe;
qcom,sde-has-cdp;
qcom,sde-has-dim-layer;
qcom,sde-has-idle-pc;
qcom,sde-max-bw-low-kbps = <4800000>;
qcom,sde-max-bw-high-kbps = <4800000>;
qcom,sde-min-core-ib-kbps = <2400000>;
qcom,sde-min-llcc-ib-kbps = <800000>;
qcom,sde-min-dram-ib-kbps = <800000>;
qcom,sde-dram-channels = <2>;
qcom,sde-num-nrt-paths = <0>;
qcom,sde-vbif-off = <0>;
qcom,sde-vbif-size = <0x1040>;
qcom,sde-vbif-id = <0>;
qcom,sde-vbif-memtype-0 = <3 3 3 3 3 3 3 3>;
qcom,sde-vbif-memtype-1 = <3 3 3 3 3 3>;
qcom,sde-vbif-qos-rt-remap = <3 3 4 4 5 5 6 6>;
qcom,sde-vbif-qos-nrt-remap = <3 3 3 3 3 3 3 3>;
/* macrotile & macrotile-qseed has the same configs */
qcom,sde-danger-lut = <0x0000000f 0x0000ffff
0x00000000 0x00000000 0x0000ffff>;
qcom,sde-safe-lut-linear = <0 0xfff8>;
qcom,sde-safe-lut-macrotile = <0 0xf000>;
/* same as safe-lut-macrotile */
qcom,sde-safe-lut-macrotile-qseed = <0 0xf000>;
qcom,sde-safe-lut-nrt = <0 0xffff>;
qcom,sde-safe-lut-cwb = <0 0xffff>;
qcom,sde-qos-lut-linear = <0 0x00112222 0x22223357>;
qcom,sde-qos-lut-macrotile = <0 0x00112233 0x44556677>;
qcom,sde-qos-lut-macrotile-qseed = <0 0x00112233 0x66777777>;
qcom,sde-qos-lut-nrt = <0 0x00000000 0x00000000>;
qcom,sde-qos-lut-cwb = <0 0x75300000 0x00000000>;
qcom,sde-cdp-setting = <1 1>, <1 0>;
qcom,sde-qos-cpu-mask = <0x3>;
qcom,sde-qos-cpu-dma-latency = <300>;
/* offsets are relative to "mdp_phys + qcom,sde-off */
qcom,sde-reg-dma-off = <0>;
qcom,sde-reg-dma-version = <0x00010001>;
qcom,sde-reg-dma-trigger-off = <0x119c>;
qcom,sde-secure-sid-mask = <0x0000801>;
/* data and reg bus scale settings */
interconnects =
<&mmss_noc MASTER_MDP0 &mc_virt SLAVE_EBI1>,
<&gem_noc MASTER_APPSS_PROC
&config_noc SLAVE_DISPLAY_CFG>;
interconnect-names = "qcom,sde-data-bus0",
"qcom,sde-reg-bus";
qcom,sde-reg-bus,vectors-KBps = <0 0>,
<0 76800>,
<0 150000>,
<0 300000>;
qcom,sde-sspp-vig-blocks {
qcom,sde-vig-csc-off = <0x1a00>;
qcom,sde-vig-qseed-off = <0xa00>;
qcom,sde-vig-qseed-size = <0xa0>;
qcom,sde-vig-inverse-pma;
};
qcom,sde-dspp-blocks {
qcom,sde-dspp-igc = <0x0 0x00030001>;
qcom,sde-dspp-hsic = <0x800 0x00010007>;
qcom,sde-dspp-memcolor = <0x880 0x00010007>;
qcom,sde-dspp-hist = <0x800 0x00010007>;
qcom,sde-dspp-sixzone= <0x900 0x00010007>;
qcom,sde-dspp-vlut = <0xa00 0x00010008>;
qcom,sde-dspp-gamut = <0x1000 0x00040001>;
qcom,sde-dspp-pcc = <0x1700 0x00040000>;
qcom,sde-dspp-gc = <0x17c0 0x00010008>;
qcom,sde-dspp-dither = <0x82c 0x00010007>;
};
};
sde_rscc: qcom,sde_rscc@af20000 {
cell-index = <0>;
compatible = "qcom,sde-rsc";
reg = <0xaf20000 0x1c44>,
<0xaf30000 0x3fd4>;
reg-names = "drv", "wrapper";
qcom,sde-rsc-version = <2>;
vdd-supply = <&mdss_core_gdsc>;
clocks = <&dispcc DISP_CC_MDSS_RSCC_VSYNC_CLK>,
<&dispcc DISP_CC_MDSS_NON_GDSC_AHB_CLK>,
<&dispcc DISP_CC_MDSS_RSCC_AHB_CLK>;
clock-names = "vsync_clk", "gdsc_clk", "iface_clk";
clock-rate = <0 0 0>;
qcom,sde-dram-channels = <2>;
mboxes = <&disp_rsc 0>;
mbox-names = "disp_rsc";
qcom,msm-bus,active-only;
interconnects =
<&mmss_noc MASTER_MDP0_DISP &gem_noc SLAVE_LLCC_DISP>,
<&mc_virt MASTER_LLCC_DISP &mc_virt SLAVE_EBI1_DISP>;
interconnect-names = "qcom,sde-data-bus0",
"qcom,sde-ebi-bus";
};
mdss_rotator: qcom,mdss_rotator@ae00000 {
compatible = "qcom,sde_rotator";
reg = <0x0ae00000 0xac000>,
<0x0aeb8000 0x3000>;
reg-names = "mdp_phys",
"rot_vbif_phys";
#list-cells = <1>;
qcom,mdss-rot-mode = <1>;
qcom,mdss-highest-bank-bit = <0x1>;
interconnects =
<&mmss_noc MASTER_ROTATOR &mc_virt SLAVE_EBI1>,
<&gem_noc MASTER_APPSS_PROC
&config_noc SLAVE_DISPLAY_CFG>;
interconnect-names = "qcom,rot-data-bus0",
"qcom,sde-reg-bus";
qcom,msm-bus,active-only;
rot-vdd-supply = <&mdss_core_gdsc>;
qcom,supply-names = "rot-vdd";
clocks =
<&gcc GCC_DISP_AHB_CLK>,
<&dispcc DISP_CC_MDSS_AHB_CLK>,
<&dispcc DISP_CC_MDSS_ROT_CLK>;
clock-names = "gcc_iface",
"iface_clk", "rot_clk";
interrupt-parent = <&mdss_mdp>;
interrupts = <2 0>;
power-domains = <&mdss_mdp>;
/* Offline rotator QoS setting */
qcom,mdss-rot-vbif-qos-setting = <3 3 3 3 3 3 3 3>;
qcom,mdss-rot-vbif-memtype = <3 3>;
qcom,mdss-rot-cdp-setting = <1 1>;
qcom,mdss-rot-qos-lut = <0x0 0x0 0x0 0x0>;
qcom,mdss-rot-danger-lut = <0x0 0x0>;
qcom,mdss-rot-safe-lut = <0x0000ffff 0x0000ffff>;
qcom,mdss-rot-qos-cpu-mask = <0xf>;
qcom,mdss-rot-qos-cpu-dma-latency = <75>;
qcom,mdss-default-ot-rd-limit = <32>;
qcom,mdss-default-ot-wr-limit = <32>;
qcom,mdss-sbuf-headroom = <20>;
cache-slice-names = "rotator";
/* reg bus scale settings */
rot_reg: qcom,rot-reg-bus {
qcom,msm-bus,name = "mdss_rot_reg";
qcom,msm-bus,num-cases = <2>;
qcom,msm-bus,num-paths = <1>;
qcom,msm-bus,vectors-KBps =
<1 590 0 0>,
<1 590 0 76800>;
};
smmu_rot_unsec: qcom,smmu_rot_unsec_cb {
compatible = "qcom,smmu_sde_rot_unsec";
iommus = <&apps_smmu 0xc40 0x0>;
};
smmu_rot_sec: qcom,smmu_rot_sec_cb {
compatible = "qcom,smmu_sde_rot_sec";
iommus = <&apps_smmu 0xc41 0x0>;
};
};
mdss_dsi0: qcom,mdss_dsi_ctrl0@ae94000 {
compatible = "qcom,dsi-ctrl-hw-v2.3";
label = "dsi-ctrl-0";
cell-index = <0>;
reg = <0xae94000 0x400>,
<0xaf08000 0x4>;
reg-names = "dsi_ctrl", "disp_cc_base";
interrupt-parent = <&mdss_mdp>;
interrupts = <4 0>;
vdda-1p2-supply = <&pm6150l_l3>;
clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>,
<&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>,
<&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>,
<&dispcc DISP_CC_MDSS_PCLK0_CLK>,
<&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>,
<&dispcc DISP_CC_MDSS_ESC0_CLK>;
clock-names = "byte_clk", "byte_clk_rcg", "byte_intf_clk",
"pixel_clk", "pixel_clk_rcg",
"esc_clk";
qcom,split-link-supported;
qcom,ctrl-supply-entries {
#address-cells = <1>;
#size-cells = <0>;
qcom,ctrl-supply-entry@0 {
reg = <0>;
qcom,supply-name = "vdda-1p2";
qcom,supply-min-voltage = <1232000>;
qcom,supply-max-voltage = <1232000>;
qcom,supply-enable-load = <21800>;
qcom,supply-disable-load = <0>;
};
};
qcom,core-supply-entries {
#address-cells = <1>;
#size-cells = <0>;
qcom,core-supply-entry@0 {
reg = <0>;
qcom,supply-name = "refgen";
qcom,supply-min-voltage = <0>;
qcom,supply-max-voltage = <0>;
qcom,supply-enable-load = <0>;
qcom,supply-disable-load = <0>;
};
};
};
mdss_dsi_phy0: qcom,mdss_dsi_phy0@ae94400 {
compatible = "qcom,dsi-phy-v2.0";
label = "dsi-phy-0";
cell-index = <0>;
#clock-cells = <1>;
reg = <0xae94400 0x588>,
<0xae01400 0x100>,
<0xae94200 0x100>,
<0xae94400 0x588>,
<0xaf03000 0x8>;
reg-names = "dsi_phy", "phy_clamp_base",
"dyn_refresh_base", "pll_base", "gdsc_base";
pll-label = "dsi_pll_14nm";
memory-region = <&dfps_data_memory>;
vdda-0p9-supply = <&pm6150_l4>;
qcom,platform-strength-ctrl = [ff 06
ff 06
ff 06
ff 06
ff 00];
qcom,platform-lane-config = [00 00 10 0f
00 00 10 0f
00 00 10 0f
00 00 10 0f
00 00 10 8f];
qcom,platform-regulator-settings = [1d 1d 1d 1d 1d];
qcom,dsi-pll-ssc-en;
qcom,dsi-pll-ssc-mode = "down-spread";
qcom,phy-supply-entries {
#address-cells = <1>;
#size-cells = <0>;
qcom,phy-supply-entry@0 {
reg = <0>;
qcom,supply-name = "vdda-0p9";
qcom,supply-min-voltage = <880000>;
qcom,supply-max-voltage = <975000>;
qcom,supply-enable-load = <36000>;
qcom,supply-disable-load = <0>;
};
};
};
ext_disp: qcom,msm-ext-disp {
compatible = "qcom,msm-ext-disp";
ext_disp_audio_codec: qcom,msm-ext-disp-audio-codec-rx {
compatible = "qcom,msm-ext-disp-audio-codec-rx";
};
};
qcom_msmhdcp: qcom,msm_hdcp {
compatible = "qcom,msm-hdcp";
cell-index = <0>;
};
sde_dp: qcom,dp_display@ae90000 {
cell-index = <0>;
compatible = "qcom,dp-display";
vdda-1p2-supply = <&pm6150l_l3>;
vdda-0p9-supply = <&pm6150_l4>;
reg = <0xae90000 0x0f4>,
<0xae90200 0x0c0>,
<0xae90400 0x5e0>,
<0xae90a00 0x098>,
<0x88e9000 0x17c>,
<0x88e9400 0x10c>,
<0x88e9800 0x10c>,
<0xaf02130 0x8>,
<0x780000 0x621c>,
<0x88e9c30 0x10>,
<0xaee1000 0x34>,
<0x1fcb24c 0x4>,
<0xae91000 0x098>;
/* dp_ctrl: dp_ahb, dp_aux, dp_link, dp_p0 */
reg-names = "dp_ahb", "dp_aux", "dp_link",
"dp_p0", "dp_phy", "dp_ln_tx0", "dp_ln_tx1",
"dp_pixel_mn", "qfprom_physical", "dp_pll",
"hdcp_physical", "dp_tcsr","dp_p1";
interrupt-parent = <&mdss_mdp>;
interrupts = <12 0>;
clocks = <&dispcc DISP_CC_MDSS_DP_AUX_CLK>,
<&rpmhcc RPMH_CXO_CLK>,
<&gcc GCC_AHB2PHY_WEST_CLK>,
<&gcc GCC_USB3_SEC_CLKREF_CLK>,
<&dispcc DISP_CC_MDSS_DP_LINK_CLK>,
<&dispcc DISP_CC_MDSS_DP_LINK_INTF_CLK>,
<&dispcc DISP_CC_MDSS_DP_PIXEL_CLK>,
<&dispcc DISP_CC_MDSS_DP_PIXEL1_CLK>,
<&dispcc DISP_CC_MDSS_DP_CRYPTO_CLK>,
<&dispcc DISP_CC_MDSS_DP_PIXEL_CLK_SRC>,
<&sde_dp DP_PHY_PLL_VCO_DIV_CLK>,
<&dispcc DISP_CC_MDSS_DP_PIXEL1_CLK_SRC>,
<&sde_dp DP_PHY_PLL_VCO_DIV_CLK>;
clock-names = "core_aux_clk", "core_usb_ref_clk_src",
"core_usb_ahb_clk", "core_usb_sec_ref_clk",
"link_clk", "link_iface_clk",
"strm0_pixel_clk","strm1_pixel_clk", "crypto_clk",
"pixel_clk_rcg", "pixel_parent","pixel1_clk_rcg",
"pixel1_parent";
qcom,phy-version = <0x200>;
qcom,aux-cfg0-settings = [20 00];
qcom,aux-cfg1-settings = [24 13 23 1d];
qcom,aux-cfg2-settings = [28 00];
qcom,aux-cfg3-settings = [2c 00];
qcom,aux-cfg4-settings = [30 0a];
qcom,aux-cfg5-settings = [34 26];
qcom,aux-cfg6-settings = [38 0a];
qcom,aux-cfg7-settings = [3c 03];
qcom,aux-cfg8-settings = [40 bb];
qcom,aux-cfg9-settings = [44 03];
qcom,logical2physical-lane-map = [03 02 00 01];
qcom,max-lclk-frequency-khz = <540000>;
qcom,max-pclk-frequency-khz = <195000>;
qcom,max-hdisplay = <1920>;
qcom,max-vdisplay = <1200>;
qcom,ext-disp = <&ext_disp>;
qcom,dp-aux-switch = <&fsa4480>;
qcom,mux-sel-gpio = <&tlmm 49 0>;
qcom,usbplug-cc-gpio = <&tlmm 104 0>;
pinctrl-names = "mdss_dp_active", "mdss_dp_sleep",
"mdss_dp_hpd_active", "mdss_dp_hpd_tlmm",
"mdss_dp_hpd_ctrl";
pinctrl-0 = <&sde_dp_usbplug_cc_active &sde_dp_switch_active>;
pinctrl-1 = <&sde_dp_usbplug_cc_suspend &sde_dp_switch_suspend>;
pinctrl-2 = <&sde_dp_connector_enable &sde_dp_switch_suspend
&sde_dp_hotplug_tlmm>;
pinctrl-3 = <&sde_dp_hotplug_tlmm>;
pinctrl-4 = <&sde_dp_hotplug_ctrl>;
qcom,msm-hdcp = <&qcom_msmhdcp>;
qcom,ctrl-supply-entries {
#address-cells = <1>;
#size-cells = <0>;
qcom,ctrl-supply-entry@0 {
reg = <0>;
qcom,supply-name = "vdda-1p2";
qcom,supply-min-voltage = <1232000>;
qcom,supply-max-voltage = <1232000>;
qcom,supply-enable-load = <21800>;
qcom,supply-disable-load = <0>;
};
};
qcom,core-supply-entries {
#address-cells = <1>;
#size-cells = <0>;
qcom,core-supply-entry@0 {
reg = <0>;
qcom,supply-name = "refgen";
qcom,supply-min-voltage = <0>;
qcom,supply-max-voltage = <0>;
qcom,supply-enable-load = <0>;
qcom,supply-disable-load = <0>;
};
};
};
smmu_sde_sec: qcom,smmu_sde_sec_cb {
compatible = "qcom,smmu_sde_sec";
iommus = <&apps_smmu 0x801 0x0>;
qcom,iommu-dma-addr-pool = <0x00020000 0xfffe0000>;
qcom,iommu-vmid = <0xa>;
};
smmu_sde_unsec:qcom,smmu_sde_unsec_cb {
compatible = "qcom,smmu_sde_unsec";
iommus = <&apps_smmu 0x800 0x0>;
qcom,iommu-dma-addr-pool = <0x00020000 0xfffe0000>;
qcom,iommu-earlymap; /* for cont-splash */
};
};

59
arch/arm64/boot/dts/vendor/qcom/display/yupik-sde-display-idp-nopmi.dtsi vendored Normal file
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@ -0,0 +1,59 @@
#include "yupik-sde-display.dtsi"
&pm8350c_gpios {
lcd_backlight_ctrl {
lcd_backlight_ctrl_default: lcd_backlight_ctrl_default {
pins = "gpio8";
function = "func1";
input-disable;
output-low;
bias-disable;
power-source = <0>;
qcom,drive-strength = <3>;
};
};
};
&sde_dsi {
/delete-property/ lab-supply;
/delete-property/ ibb-supply;
pinctrl-names = "panel_active", "panel_suspend", "pwm_pin";
pinctrl-2 = <&lcd_backlight_ctrl_default>;
qcom,dsi-default-panel = <&dsi_nt36672e_fhd_plus_120_video>;
};
&dsi_nt36672e_fhd_plus_60_video {
qcom,panel-supply-entries = <&dsi_panel_pwr_supply_no_labibb>;
qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_pwm";
pwms = <&pm8350c_pwm_2 0 0>;
qcom,bl-pmic-pwm-period-usecs = <100>;
qcom,mdss-dsi-bl-min-level = <1>;
qcom,mdss-dsi-bl-max-level = <4095>;
qcom,platform-reset-gpio = <&tlmm 44 0>;
qcom,platform-bklight-en-gpio = <&pm8350c_gpios 7 0>;
};
&dsi_nt36672e_fhd_plus_120_video {
qcom,panel-supply-entries = <&dsi_panel_pwr_supply_no_labibb>;
qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_pwm";
pwms = <&pm8350c_pwm_2 0 0>;
qcom,bl-pmic-pwm-period-usecs = <100>;
qcom,mdss-dsi-bl-min-level = <1>;
qcom,mdss-dsi-bl-max-level = <4095>;
qcom,platform-reset-gpio = <&tlmm 44 0>;
qcom,platform-bklight-en-gpio = <&pm8350c_gpios 7 0>;
};
&dsi_nt36672e_fhd_plus_144_video {
qcom,panel-supply-entries = <&dsi_panel_pwr_supply_no_labibb>;
qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_pwm";
pwms = <&pm8350c_pwm_2 0 0>;
qcom,bl-pmic-pwm-period-usecs = <100>;
qcom,mdss-dsi-bl-min-level = <1>;
qcom,mdss-dsi-bl-max-level = <4095>;
qcom,platform-reset-gpio = <&tlmm 44 0>;
qcom,platform-bklight-en-gpio = <&pm8350c_gpios 7 0>;
};