Revert "asoc: lahaina: add 16 channel support on tdm interface"
This reverts commit 782c8273ed.
Change-Id: I5cd459439e51d6d3b8f3418b2a82966969817e8f
This commit is contained in:
Giovanni Ricca
parent
c21f70e076
commit
eaf3532cc1
1 changed files with 78 additions and 651 deletions
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@ -1,7 +1,7 @@
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// SPDX-License-Identifier: GPL-2.0-only
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/*
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* Copyright (c) 2016-2021, The Linux Foundation. All rights reserved.
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* Copyright (c) 2022-2023 Qualcomm Innovation Center, Inc. All rights reserved.
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* Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved.
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*/
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#include <linux/clk.h>
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@ -76,7 +76,6 @@
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#define WCD_MBHC_HS_V_MAX 1600
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#define TDM_CHANNEL_MAX 8
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#define TDM_SLOT_OFFSET_MAX 32
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#define MI2S_NUM_CHANNELS 2
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@ -108,7 +107,7 @@ enum {
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TDM_PORT_MAX,
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};
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#define TDM_MAX_SLOTS 16
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#define TDM_MAX_SLOTS 8
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#define TDM_SLOT_WIDTH_BITS 32
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#define TDM_SLOT_WIDTH_BYTES TDM_SLOT_WIDTH_BITS/8
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@ -722,59 +721,6 @@ static struct dev_config afe_loopback_tx_cfg[] = {
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[AFE_LOOPBACK_TX_IDX] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
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};
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/* TDM default slot config */
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struct tdm_slot_cfg {
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u32 width;
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u32 num;
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};
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static struct tdm_slot_cfg tdm_slot[TDM_INTERFACE_MAX] = {
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/* PRI TDM */
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{32, 8},
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/* SEC TDM */
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{32, 8},
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/* TERT TDM */
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{32, 8},
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/* QUAT TDM */
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{32, 8},
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/* QUIN TDM */
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{32, 8},
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/* SEN TDM*/
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{32, 8}
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};
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static unsigned int tdm_rx_slot_offset
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[TDM_INTERFACE_MAX][TDM_SLOT_OFFSET_MAX] = {
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/* PRI TDM */
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{0, 4, 8, 12, 16, 20, 24, 0xFFFF},
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/* SEC TDM */
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{0, 4, 8, 12, 16, 20, 24, 0xFFFF},
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/* TERT TDM */
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{0, 4, 8, 12, 16, 20, 24, 0xFFFF},
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/* QUAT TDM */
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{0, 4, 8, 12, 16, 20, 24, 0xFFFF},
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/* QUIN TDM */
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{0, 4, 8, 12, 16, 20, 24, 0xFFFF},
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/* SEN TDM */
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{0, 4, 8, 12, 16, 20, 24, 0xFFFF}
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};
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static unsigned int tdm_tx_slot_offset
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[TDM_INTERFACE_MAX][TDM_SLOT_OFFSET_MAX] = {
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/* PRI TDM */
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{0, 4, 8, 12, 16, 20, 24, 0xFFFF},
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/* SEC TDM */
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{0, 4, 8, 12, 16, 20, 24, 0xFFFF},
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/* TERT TDM */
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{0, 4, 8, 12, 16, 20, 24, 0xFFFF},
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/* QUAT TDM */
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{0, 4, 8, 12, 16, 20, 24, 0xFFFF},
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/* QUIN TDM */
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{0, 4, 8, 12, 16, 20, 24, 0xFFFF},
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/* SEN TDM */
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{0, 4, 8, 12, 16, 20, 24, 0xFFFF}
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};
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static int msm_vi_feed_tx_ch = 2;
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static const char *const vi_feed_ch_text[] = {"One", "Two"};
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static char const *bit_format_text[] = {"S16_LE", "S24_LE", "S24_3LE",
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@ -790,23 +736,12 @@ static char const *usb_sample_rate_text[] = {"KHZ_8", "KHZ_11P025",
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static const char *const usb_ch_text[] = {"One", "Two", "Three", "Four",
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"Five", "Six", "Seven",
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"Eight"};
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static char const *tdm_sample_rate_text[] = {"KHZ_8", "KHZ_11P025",
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"KHZ_16", "KHZ_22P05",
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"KHZ_32", "KHZ_44P1", "KHZ_48",
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"KHZ_88P2", "KHZ_96", "KHZ_176P4",
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"KHZ_192", "KHZ_352P8", "KHZ_384"};
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static const char *const tdm_slot_num_text[] = {"One", "Two", "Four",
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"Eight", "Sixteen", "ThirtyTwo"};
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static const char *const tdm_slot_width_text[] = {"16", "24", "32"};
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static char const *tdm_sample_rate_text[] = {"KHZ_8", "KHZ_16", "KHZ_32",
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"KHZ_48", "KHZ_176P4",
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"KHZ_352P8"};
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static char const *tdm_bit_format_text[] = {"S16_LE", "S24_LE", "S32_LE"};
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static char const *tdm_ch_text[] = {
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"One", "Two", "Three", "Four", "Five", "Six", "Seven",
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"Eight", "Nine", "Ten", "Eleven", "Twelve", "Thirteen",
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"Fourteen", "Fifteen", "Sixteen", "Seventeen", "Eighteen",
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"Nineteen", "Twenty", "TwentyOne", "TwentyTwo", "TwentyThree",
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"TwentyFour", "TwentyFive", "TwentySix", "TwentySeven",
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"TwentyEight", "TwentyNine", "Thirty", "ThirtyOne", "ThirtyTwo"
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};
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static char const *tdm_ch_text[] = {"One", "Two", "Three", "Four",
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"Five", "Six", "Seven", "Eight"};
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static const char *const auxpcm_rate_text[] = {"KHZ_8", "KHZ_16"};
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static char const *mi2s_rate_text[] = {"KHZ_8", "KHZ_11P025", "KHZ_16",
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"KHZ_22P05", "KHZ_32", "KHZ_44P1",
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@ -858,8 +793,6 @@ static SOC_ENUM_SINGLE_EXT_DECL(vi_feed_tx_chs, vi_feed_ch_text);
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static SOC_ENUM_SINGLE_EXT_DECL(proxy_rx_chs, ch_text);
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static SOC_ENUM_SINGLE_EXT_DECL(tdm_rx_sample_rate, tdm_sample_rate_text);
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static SOC_ENUM_SINGLE_EXT_DECL(tdm_tx_sample_rate, tdm_sample_rate_text);
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static SOC_ENUM_SINGLE_EXT_DECL(tdm_slot_num, tdm_slot_num_text);
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static SOC_ENUM_SINGLE_EXT_DECL(tdm_slot_width, tdm_slot_width_text);
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static SOC_ENUM_SINGLE_EXT_DECL(tdm_rx_format, tdm_bit_format_text);
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static SOC_ENUM_SINGLE_EXT_DECL(tdm_tx_format, tdm_bit_format_text);
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static SOC_ENUM_SINGLE_EXT_DECL(tdm_tx_chs, tdm_ch_text);
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@ -1978,43 +1911,34 @@ static int proxy_rx_ch_put(struct snd_kcontrol *kcontrol,
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return 1;
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}
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static int tdm_get_mode(struct snd_kcontrol *kcontrol)
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{
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int mode;
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if (strnstr(kcontrol->id.name, "PRI",
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sizeof(kcontrol->id.name))) {
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mode = TDM_PRI;
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} else if (strnstr(kcontrol->id.name, "SEC",
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sizeof(kcontrol->id.name))) {
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mode = TDM_SEC;
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} else if (strnstr(kcontrol->id.name, "TERT",
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sizeof(kcontrol->id.name))) {
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mode = TDM_TERT;
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} else if (strnstr(kcontrol->id.name, "QUAT",
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sizeof(kcontrol->id.name))) {
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mode = TDM_QUAT;
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} else if (strnstr(kcontrol->id.name, "QUIN",
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sizeof(kcontrol->id.name))) {
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mode = TDM_QUIN;
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} else if (strnstr(kcontrol->id.name, "SEN",
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sizeof(kcontrol->id.name))) {
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mode = TDM_SEN;
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} else {
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pr_err("%s: unsupported mode in: %s",
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__func__, kcontrol->id.name);
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return -EINVAL;
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}
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return mode;
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}
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static int tdm_get_port_idx(struct snd_kcontrol *kcontrol,
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struct tdm_port *port)
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{
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if (port) {
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port->mode = tdm_get_mode(kcontrol);
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if (port->mode < 0)
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return port->mode;
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if (strnstr(kcontrol->id.name, "PRI",
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sizeof(kcontrol->id.name))) {
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port->mode = TDM_PRI;
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} else if (strnstr(kcontrol->id.name, "SEC",
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sizeof(kcontrol->id.name))) {
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port->mode = TDM_SEC;
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} else if (strnstr(kcontrol->id.name, "TERT",
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sizeof(kcontrol->id.name))) {
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port->mode = TDM_TERT;
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} else if (strnstr(kcontrol->id.name, "QUAT",
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sizeof(kcontrol->id.name))) {
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port->mode = TDM_QUAT;
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} else if (strnstr(kcontrol->id.name, "QUIN",
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sizeof(kcontrol->id.name))) {
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port->mode = TDM_QUIN;
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} else if (strnstr(kcontrol->id.name, "SEN",
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sizeof(kcontrol->id.name))) {
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port->mode = TDM_SEN;
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} else {
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pr_err("%s: unsupported mode in: %s\n",
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__func__, kcontrol->id.name);
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return -EINVAL;
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}
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if (strnstr(kcontrol->id.name, "RX_0",
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sizeof(kcontrol->id.name)) ||
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strnstr(kcontrol->id.name, "TX_0",
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@ -2409,263 +2333,6 @@ static int tdm_tx_ch_put(struct snd_kcontrol *kcontrol,
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return ret;
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}
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static int tdm_get_slot_num_val(int slot_num)
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{
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int slot_num_val;
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switch (slot_num) {
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case 1:
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slot_num_val = 0;
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break;
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case 2:
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slot_num_val = 1;
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break;
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case 4:
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slot_num_val = 2;
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break;
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case 8:
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slot_num_val = 3;
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break;
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case 16:
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slot_num_val = 4;
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break;
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case 32:
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slot_num_val = 5;
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break;
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default:
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slot_num_val = 5;
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break;
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}
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return slot_num_val;
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}
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static int tdm_get_slot_num(int value)
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{
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int slot_num;
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switch (value) {
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case 0:
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slot_num = 1;
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break;
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case 1:
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slot_num = 2;
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break;
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case 2:
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slot_num = 4;
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break;
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case 3:
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slot_num = 8;
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break;
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case 4:
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slot_num = 16;
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break;
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case 5:
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slot_num = 32;
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break;
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default:
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slot_num = 8;
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break;
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}
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return slot_num;
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}
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static int tdm_slot_num_get(struct snd_kcontrol *kcontrol,
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struct snd_ctl_elem_value *ucontrol)
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{
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int mode = tdm_get_mode(kcontrol);
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if (mode < 0) {
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pr_err("%s: unsupported control: %s",
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__func__, kcontrol->id.name);
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return mode;
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}
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ucontrol->value.enumerated.item[0] =
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tdm_get_slot_num_val(tdm_slot[mode].num);
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pr_debug("%s: mode = %d, tdm_slot_num = %d, item = %d\n", __func__,
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mode, tdm_slot[mode].num,
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ucontrol->value.enumerated.item[0]);
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return 0;
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}
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static int tdm_slot_num_put(struct snd_kcontrol *kcontrol,
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struct snd_ctl_elem_value *ucontrol)
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{
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int mode = tdm_get_mode(kcontrol);
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if (mode < 0) {
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pr_err("%s: unsupported control: %s",
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__func__, kcontrol->id.name);
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return mode;
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}
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tdm_slot[mode].num =
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tdm_get_slot_num(ucontrol->value.enumerated.item[0]);
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pr_debug("%s: mode = %d, tdm_slot_num = %d, item = %d\n", __func__,
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mode, tdm_slot[mode].num,
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ucontrol->value.enumerated.item[0]);
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return 0;
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}
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static int tdm_get_slot_width_val(int slot_width)
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{
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int slot_width_val;
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switch (slot_width) {
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case 16:
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slot_width_val = 0;
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break;
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case 24:
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slot_width_val = 1;
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break;
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case 32:
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slot_width_val = 2;
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break;
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default:
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slot_width_val = 2;
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break;
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}
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return slot_width_val;
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}
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static int tdm_slot_width_get(struct snd_kcontrol *kcontrol,
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struct snd_ctl_elem_value *ucontrol)
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{
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int mode = tdm_get_mode(kcontrol);
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if (mode < 0) {
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pr_err("%s: unsupported control: %s",
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__func__, kcontrol->id.name);
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return mode;
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}
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ucontrol->value.enumerated.item[0] =
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tdm_get_slot_width_val(tdm_slot[mode].width);
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pr_debug("%s: mode = %d, tdm_slot_width = %d, item = %d\n", __func__,
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mode, tdm_slot[mode].width,
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ucontrol->value.enumerated.item[0]);
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return 0;
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}
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static int tdm_get_slot_width(int value)
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{
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int slot_width;
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switch (value) {
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case 0:
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slot_width = 16;
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break;
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case 1:
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slot_width = 24;
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break;
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case 2:
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slot_width = 32;
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break;
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default:
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slot_width = 32;
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break;
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}
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return slot_width;
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}
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static int tdm_slot_width_put(struct snd_kcontrol *kcontrol,
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struct snd_ctl_elem_value *ucontrol)
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{
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int mode = tdm_get_mode(kcontrol);
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if (mode < 0) {
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pr_err("%s: unsupported control: %s",
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__func__, kcontrol->id.name);
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return mode;
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}
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tdm_slot[mode].width =
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tdm_get_slot_width(ucontrol->value.enumerated.item[0]);
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pr_debug("%s: mode = %d, tdm_slot_width = %d, item = %d\n", __func__,
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mode, tdm_slot[mode].width,
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ucontrol->value.enumerated.item[0]);
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return 0;
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}
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static int tdm_rx_slot_mapping_get(struct snd_kcontrol *kcontrol,
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struct snd_ctl_elem_value *ucontrol)
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{
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unsigned int *slot_offset;
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int i;
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int mode = tdm_get_mode(kcontrol);
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if (mode < 0) {
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pr_err("%s: unsupported control: %s",
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__func__, kcontrol->id.name);
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return mode;
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}
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slot_offset = tdm_rx_slot_offset[mode];
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for (i = 0; i < TDM_SLOT_OFFSET_MAX; i++) {
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ucontrol->value.integer.value[i] = slot_offset[i];
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pr_debug("%s: offset %d, value %d\n",
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__func__, i, slot_offset[i]);
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}
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return 0;
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}
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static int tdm_rx_slot_mapping_put(struct snd_kcontrol *kcontrol,
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struct snd_ctl_elem_value *ucontrol)
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{
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unsigned int *slot_offset;
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int i;
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int mode = tdm_get_mode(kcontrol);
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if (mode < 0) {
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pr_err("%s: unsupported control: %s",
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__func__, kcontrol->id.name);
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return mode;
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}
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slot_offset = tdm_rx_slot_offset[mode];
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for (i = 0; i < TDM_SLOT_OFFSET_MAX; i++) {
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slot_offset[i] = ucontrol->value.integer.value[i];
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pr_debug("%s: offset %d, value %d\n",
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__func__, i, slot_offset[i]);
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}
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return 0;
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}
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static int tdm_tx_slot_mapping_get(struct snd_kcontrol *kcontrol,
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struct snd_ctl_elem_value *ucontrol)
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{
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unsigned int *slot_offset;
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int i;
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int mode = tdm_get_mode(kcontrol);
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if (mode < 0) {
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pr_err("%s: unsupported control: %s",
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__func__, kcontrol->id.name);
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return mode;
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}
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slot_offset = tdm_tx_slot_offset[mode];
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for (i = 0; i < TDM_SLOT_OFFSET_MAX; i++) {
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ucontrol->value.integer.value[i] = slot_offset[i];
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pr_debug("%s: offset %d, value %d\n",
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__func__, i, slot_offset[i]);
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}
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return 0;
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}
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static int tdm_tx_slot_mapping_put(struct snd_kcontrol *kcontrol,
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struct snd_ctl_elem_value *ucontrol)
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{
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unsigned int *slot_offset;
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int i;
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int mode = tdm_get_mode(kcontrol);
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if (mode < 0) {
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pr_err("%s: unsupported control: %s",
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__func__, kcontrol->id.name);
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return mode;
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}
|
||||
slot_offset = tdm_tx_slot_offset[mode];
|
||||
for (i = 0; i < TDM_SLOT_OFFSET_MAX; i++) {
|
||||
slot_offset[i] = ucontrol->value.integer.value[i];
|
||||
pr_debug("%s: offset %d, value %d\n",
|
||||
__func__, i, slot_offset[i]);
|
||||
}
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int tdm_slot_map_put(struct snd_kcontrol *kcontrol,
|
||||
struct snd_ctl_elem_value *ucontrol)
|
||||
{
|
||||
|
|
@ -3493,112 +3160,6 @@ err:
|
|||
return ret;
|
||||
}
|
||||
|
||||
static int lahaina_tdm_be_hw_params_fixup(struct snd_soc_pcm_runtime *rtd,
|
||||
struct snd_pcm_hw_params *params)
|
||||
{
|
||||
struct snd_soc_dai *cpu_dai = rtd->cpu_dai;
|
||||
struct snd_interval *rate = hw_param_interval(params,
|
||||
SNDRV_PCM_HW_PARAM_RATE);
|
||||
struct snd_interval *channels = hw_param_interval(params,
|
||||
SNDRV_PCM_HW_PARAM_CHANNELS);
|
||||
|
||||
if (cpu_dai->id == AFE_PORT_ID_PRIMARY_TDM_RX) {
|
||||
channels->min = channels->max =
|
||||
tdm_rx_cfg[TDM_PRI][TDM_0].channels;
|
||||
param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
|
||||
tdm_rx_cfg[TDM_PRI][TDM_0].bit_format);
|
||||
rate->min = rate->max =
|
||||
tdm_rx_cfg[TDM_PRI][TDM_0].sample_rate;
|
||||
} else if (cpu_dai->id == AFE_PORT_ID_PRIMARY_TDM_TX) {
|
||||
channels->min = channels->max =
|
||||
tdm_tx_cfg[TDM_PRI][TDM_0].channels;
|
||||
param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
|
||||
tdm_tx_cfg[TDM_PRI][TDM_0].bit_format);
|
||||
rate->min = rate->max =
|
||||
tdm_tx_cfg[TDM_PRI][TDM_0].sample_rate;
|
||||
} else if (cpu_dai->id == AFE_PORT_ID_SECONDARY_TDM_RX) {
|
||||
channels->min = channels->max =
|
||||
tdm_rx_cfg[TDM_SEC][TDM_0].channels;
|
||||
param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
|
||||
tdm_rx_cfg[TDM_SEC][TDM_0].bit_format);
|
||||
rate->min = rate->max =
|
||||
tdm_rx_cfg[TDM_SEC][TDM_0].sample_rate;
|
||||
} else if (cpu_dai->id == AFE_PORT_ID_SECONDARY_TDM_TX) {
|
||||
channels->min = channels->max =
|
||||
tdm_tx_cfg[TDM_SEC][TDM_0].channels;
|
||||
param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
|
||||
tdm_tx_cfg[TDM_SEC][TDM_0].bit_format);
|
||||
rate->min = rate->max =
|
||||
tdm_tx_cfg[TDM_SEC][TDM_0].sample_rate;
|
||||
} else if (cpu_dai->id == AFE_PORT_ID_TERTIARY_TDM_RX) {
|
||||
channels->min = channels->max =
|
||||
tdm_rx_cfg[TDM_TERT][TDM_0].channels;
|
||||
param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
|
||||
tdm_rx_cfg[TDM_TERT][TDM_0].bit_format);
|
||||
rate->min = rate->max =
|
||||
tdm_rx_cfg[TDM_TERT][TDM_0].sample_rate;
|
||||
} else if (cpu_dai->id == AFE_PORT_ID_TERTIARY_TDM_TX) {
|
||||
channels->min = channels->max =
|
||||
tdm_tx_cfg[TDM_TERT][TDM_0].channels;
|
||||
param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
|
||||
tdm_tx_cfg[TDM_TERT][TDM_0].bit_format);
|
||||
rate->min = rate->max =
|
||||
tdm_tx_cfg[TDM_TERT][TDM_0].sample_rate;
|
||||
} else if (cpu_dai->id == AFE_PORT_ID_QUATERNARY_TDM_RX) {
|
||||
channels->min = channels->max =
|
||||
tdm_rx_cfg[TDM_QUAT][TDM_0].channels;
|
||||
param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
|
||||
tdm_rx_cfg[TDM_QUAT][TDM_0].bit_format);
|
||||
rate->min = rate->max =
|
||||
tdm_rx_cfg[TDM_QUAT][TDM_0].sample_rate;
|
||||
} else if (cpu_dai->id == AFE_PORT_ID_QUATERNARY_TDM_TX) {
|
||||
channels->min = channels->max =
|
||||
tdm_tx_cfg[TDM_QUAT][TDM_0].channels;
|
||||
param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
|
||||
tdm_tx_cfg[TDM_QUAT][TDM_0].bit_format);
|
||||
rate->min = rate->max =
|
||||
tdm_tx_cfg[TDM_QUAT][TDM_0].sample_rate;
|
||||
} else if (cpu_dai->id == AFE_PORT_ID_QUINARY_TDM_RX) {
|
||||
channels->min = channels->max =
|
||||
tdm_rx_cfg[TDM_QUIN][TDM_0].channels;
|
||||
param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
|
||||
tdm_rx_cfg[TDM_QUIN][TDM_0].bit_format);
|
||||
rate->min = rate->max =
|
||||
tdm_rx_cfg[TDM_QUIN][TDM_0].sample_rate;
|
||||
} else if (cpu_dai->id == AFE_PORT_ID_QUINARY_TDM_TX) {
|
||||
channels->min = channels->max =
|
||||
tdm_tx_cfg[TDM_QUIN][TDM_0].channels;
|
||||
param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
|
||||
tdm_tx_cfg[TDM_QUIN][TDM_0].bit_format);
|
||||
rate->min = rate->max =
|
||||
tdm_tx_cfg[TDM_QUIN][TDM_0].sample_rate;
|
||||
} else if (cpu_dai->id == AFE_PORT_ID_SENARY_TDM_RX) {
|
||||
channels->min = channels->max =
|
||||
tdm_rx_cfg[TDM_SEN][TDM_0].channels;
|
||||
param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
|
||||
tdm_rx_cfg[TDM_SEN][TDM_0].bit_format);
|
||||
rate->min = rate->max =
|
||||
tdm_rx_cfg[TDM_SEN][TDM_0].sample_rate;
|
||||
} else if (cpu_dai->id == AFE_PORT_ID_SENARY_TDM_TX) {
|
||||
channels->min = channels->max =
|
||||
tdm_tx_cfg[TDM_SEN][TDM_0].channels;
|
||||
param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
|
||||
tdm_tx_cfg[TDM_SEN][TDM_0].bit_format);
|
||||
rate->min = rate->max =
|
||||
tdm_tx_cfg[TDM_SEN][TDM_0].sample_rate;
|
||||
} else {
|
||||
pr_err("%s: dai id 0x%x not supported\n",
|
||||
__func__, cpu_dai->id);
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
pr_debug("%s: dai id = 0x%x channels = %d rate = %d format = 0x%x\n",
|
||||
__func__, cpu_dai->id, channels->max, rate->max,
|
||||
params_format(params));
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int cdc_dma_get_port_idx(struct snd_kcontrol *kcontrol)
|
||||
{
|
||||
int idx = 0;
|
||||
|
|
@ -4875,30 +4436,6 @@ static const struct snd_kcontrol_new msm_common_snd_controls[] = {
|
|||
SOC_ENUM_EXT("SEN_TDM_TX_0 Channels", tdm_tx_chs,
|
||||
tdm_tx_ch_get,
|
||||
tdm_tx_ch_put),
|
||||
SOC_ENUM_EXT("PRI_TDM SlotNumber", tdm_slot_num,
|
||||
tdm_slot_num_get, tdm_slot_num_put),
|
||||
SOC_ENUM_EXT("SEC_TDM SlotNumber", tdm_slot_num,
|
||||
tdm_slot_num_get, tdm_slot_num_put),
|
||||
SOC_ENUM_EXT("TERT_TDM SlotNumber", tdm_slot_num,
|
||||
tdm_slot_num_get, tdm_slot_num_put),
|
||||
SOC_ENUM_EXT("QUAT_TDM SlotNumber", tdm_slot_num,
|
||||
tdm_slot_num_get, tdm_slot_num_put),
|
||||
SOC_ENUM_EXT("QUIN_TDM SlotNumber", tdm_slot_num,
|
||||
tdm_slot_num_get, tdm_slot_num_put),
|
||||
SOC_ENUM_EXT("SEN_TDM SlotNumber", tdm_slot_num,
|
||||
tdm_slot_num_get, tdm_slot_num_put),
|
||||
SOC_ENUM_EXT("PRI_TDM SlotWidth", tdm_slot_width,
|
||||
tdm_slot_width_get, tdm_slot_width_put),
|
||||
SOC_ENUM_EXT("SEC_TDM SlotWidth", tdm_slot_width,
|
||||
tdm_slot_width_get, tdm_slot_width_put),
|
||||
SOC_ENUM_EXT("TERT_TDM SlotWidth", tdm_slot_width,
|
||||
tdm_slot_width_get, tdm_slot_width_put),
|
||||
SOC_ENUM_EXT("QUAT_TDM SlotWidth", tdm_slot_width,
|
||||
tdm_slot_width_get, tdm_slot_width_put),
|
||||
SOC_ENUM_EXT("QUIN_TDM SlotWidth", tdm_slot_width,
|
||||
tdm_slot_width_get, tdm_slot_width_put),
|
||||
SOC_ENUM_EXT("SEN_TDM SlotWidth", tdm_slot_width,
|
||||
tdm_slot_width_get, tdm_slot_width_put),
|
||||
SOC_ENUM_EXT("PRIM_MI2S_RX Channels", prim_mi2s_rx_chs,
|
||||
msm_mi2s_rx_ch_get, msm_mi2s_rx_ch_put),
|
||||
SOC_ENUM_EXT("SEC_MI2S_RX Channels", sec_mi2s_rx_chs,
|
||||
|
|
@ -4952,42 +4489,6 @@ static const struct snd_kcontrol_new msm_common_snd_controls[] = {
|
|||
msm_vi_feed_tx_ch_get, msm_vi_feed_tx_ch_put),
|
||||
SOC_SINGLE_MULTI_EXT("TDM Slot Map", SND_SOC_NOPM, 0, 255, 0,
|
||||
TDM_MAX_SLOTS + MAX_PATH, NULL, tdm_slot_map_put),
|
||||
SOC_SINGLE_MULTI_EXT("PRI_TDM_TX SlotMapping",
|
||||
SND_SOC_NOPM, 0, 0xFFFF, 0, TDM_SLOT_OFFSET_MAX,
|
||||
tdm_tx_slot_mapping_get, tdm_tx_slot_mapping_put),
|
||||
SOC_SINGLE_MULTI_EXT("PRI_TDM_RX SlotMapping",
|
||||
SND_SOC_NOPM, 0, 0xFFFF, 0, TDM_SLOT_OFFSET_MAX,
|
||||
tdm_rx_slot_mapping_get, tdm_rx_slot_mapping_put),
|
||||
SOC_SINGLE_MULTI_EXT("SEC_TDM_TX SlotMapping",
|
||||
SND_SOC_NOPM, 0, 0xFFFF, 0, TDM_SLOT_OFFSET_MAX,
|
||||
tdm_tx_slot_mapping_get, tdm_tx_slot_mapping_put),
|
||||
SOC_SINGLE_MULTI_EXT("SEC_TDM_RX SlotMapping",
|
||||
SND_SOC_NOPM, 0, 0xFFFF, 0, TDM_SLOT_OFFSET_MAX,
|
||||
tdm_rx_slot_mapping_get, tdm_rx_slot_mapping_put),
|
||||
SOC_SINGLE_MULTI_EXT("TERT_TDM_TX SlotMapping",
|
||||
SND_SOC_NOPM, 0, 0xFFFF, 0, TDM_SLOT_OFFSET_MAX,
|
||||
tdm_tx_slot_mapping_get, tdm_tx_slot_mapping_put),
|
||||
SOC_SINGLE_MULTI_EXT("TERT_TDM_RX SlotMapping",
|
||||
SND_SOC_NOPM, 0, 0xFFFF, 0, TDM_SLOT_OFFSET_MAX,
|
||||
tdm_rx_slot_mapping_get, tdm_rx_slot_mapping_put),
|
||||
SOC_SINGLE_MULTI_EXT("QUAT_TDM_TX SlotMapping",
|
||||
SND_SOC_NOPM, 0, 0xFFFF, 0, TDM_SLOT_OFFSET_MAX,
|
||||
tdm_tx_slot_mapping_get, tdm_tx_slot_mapping_put),
|
||||
SOC_SINGLE_MULTI_EXT("QUAT_TDM_RX SlotMapping",
|
||||
SND_SOC_NOPM, 0, 0xFFFF, 0, TDM_SLOT_OFFSET_MAX,
|
||||
tdm_rx_slot_mapping_get, tdm_rx_slot_mapping_put),
|
||||
SOC_SINGLE_MULTI_EXT("QUIN_TDM_TX SlotMapping",
|
||||
SND_SOC_NOPM, 0, 0xFFFF, 0, TDM_SLOT_OFFSET_MAX,
|
||||
tdm_tx_slot_mapping_get, tdm_tx_slot_mapping_put),
|
||||
SOC_SINGLE_MULTI_EXT("QUIN_TDM_RX SlotMapping",
|
||||
SND_SOC_NOPM, 0, 0xFFFF, 0, TDM_SLOT_OFFSET_MAX,
|
||||
tdm_rx_slot_mapping_get, tdm_rx_slot_mapping_put),
|
||||
SOC_SINGLE_MULTI_EXT("SEN_TDM_TX SlotMapping",
|
||||
SND_SOC_NOPM, 0, 0xFFFF, 0, TDM_SLOT_OFFSET_MAX,
|
||||
tdm_tx_slot_mapping_get, tdm_tx_slot_mapping_put),
|
||||
SOC_SINGLE_MULTI_EXT("SEN_TDM_RX SlotMapping",
|
||||
SND_SOC_NOPM, 0, 0xFFFF, 0, TDM_SLOT_OFFSET_MAX,
|
||||
tdm_rx_slot_mapping_get, tdm_rx_slot_mapping_put),
|
||||
};
|
||||
|
||||
static const struct snd_kcontrol_new msm_snd_controls[] = {
|
||||
|
|
@ -5585,113 +5086,55 @@ static int lahaina_tdm_snd_hw_params(struct snd_pcm_substream *substream,
|
|||
int channels, slots;
|
||||
unsigned int slot_mask, rate, clk_freq;
|
||||
unsigned int *slot_offset;
|
||||
int offset_channels = 0;
|
||||
int i;
|
||||
struct tdm_dev_config *config;
|
||||
unsigned int path_dir = 0, interface = 0, channel_interface = 0;
|
||||
struct msm_asoc_mach_data *pdata = NULL;
|
||||
|
||||
pr_debug("%s: dai id = 0x%x\n", __func__, cpu_dai->id);
|
||||
|
||||
/* currently only supporting TDM_RX_0 and TDM_TX_0 */
|
||||
switch (cpu_dai->id) {
|
||||
case AFE_PORT_ID_PRIMARY_TDM_RX:
|
||||
channels = tdm_rx_cfg[TDM_PRI][TDM_0].channels;
|
||||
slots = tdm_slot[TDM_PRI].num;
|
||||
slot_width = tdm_slot[TDM_PRI].width;
|
||||
slot_offset = tdm_rx_slot_offset[TDM_PRI];
|
||||
break;
|
||||
case AFE_PORT_ID_SECONDARY_TDM_RX:
|
||||
channels = tdm_rx_cfg[TDM_SEC][TDM_0].channels;
|
||||
slots = tdm_slot[TDM_SEC].num;
|
||||
slot_width = tdm_slot[TDM_SEC].width;
|
||||
slot_offset = tdm_rx_slot_offset[TDM_SEC];
|
||||
break;
|
||||
case AFE_PORT_ID_TERTIARY_TDM_RX:
|
||||
channels = tdm_rx_cfg[TDM_TERT][TDM_0].channels;
|
||||
slots = tdm_slot[TDM_TERT].num;
|
||||
slot_width = tdm_slot[TDM_TERT].width;
|
||||
slot_offset = tdm_rx_slot_offset[TDM_TERT];
|
||||
break;
|
||||
case AFE_PORT_ID_QUATERNARY_TDM_RX:
|
||||
channels = tdm_rx_cfg[TDM_QUAT][TDM_0].channels;
|
||||
slots = tdm_slot[TDM_QUAT].num;
|
||||
slot_width = tdm_slot[TDM_QUAT].width;
|
||||
slot_offset = tdm_rx_slot_offset[TDM_QUAT];
|
||||
break;
|
||||
case AFE_PORT_ID_QUINARY_TDM_RX:
|
||||
channels = tdm_rx_cfg[TDM_QUIN][TDM_0].channels;
|
||||
slots = tdm_slot[TDM_QUIN].num;
|
||||
slot_width = tdm_slot[TDM_QUIN].width;
|
||||
slot_offset = tdm_rx_slot_offset[TDM_QUIN];
|
||||
break;
|
||||
case AFE_PORT_ID_SENARY_TDM_RX:
|
||||
channels = tdm_rx_cfg[TDM_SEN][TDM_0].channels;
|
||||
slots = tdm_slot[TDM_SEN].num;
|
||||
slot_width = tdm_slot[TDM_SEN].width;
|
||||
slot_offset = tdm_rx_slot_offset[TDM_SEN];
|
||||
break;
|
||||
case AFE_PORT_ID_PRIMARY_TDM_TX:
|
||||
channels = tdm_tx_cfg[TDM_PRI][TDM_0].channels;
|
||||
slots = tdm_slot[TDM_PRI].num;
|
||||
slot_width = tdm_slot[TDM_PRI].width;
|
||||
slot_offset = tdm_tx_slot_offset[TDM_PRI];
|
||||
break;
|
||||
case AFE_PORT_ID_SECONDARY_TDM_TX:
|
||||
channels = tdm_tx_cfg[TDM_SEC][TDM_0].channels;
|
||||
slots = tdm_slot[TDM_SEC].num;
|
||||
slot_width = tdm_slot[TDM_SEC].width;
|
||||
slot_offset = tdm_tx_slot_offset[TDM_SEC];
|
||||
break;
|
||||
case AFE_PORT_ID_TERTIARY_TDM_TX:
|
||||
channels = tdm_tx_cfg[TDM_TERT][TDM_0].channels;
|
||||
slots = tdm_slot[TDM_TERT].num;
|
||||
slot_width = tdm_slot[TDM_TERT].width;
|
||||
slot_offset = tdm_tx_slot_offset[TDM_TERT];
|
||||
break;
|
||||
case AFE_PORT_ID_QUATERNARY_TDM_TX:
|
||||
channels = tdm_tx_cfg[TDM_QUAT][TDM_0].channels;
|
||||
slots = tdm_slot[TDM_QUAT].num;
|
||||
slot_width = tdm_slot[TDM_QUAT].width;
|
||||
slot_offset = tdm_tx_slot_offset[TDM_QUAT];
|
||||
break;
|
||||
case AFE_PORT_ID_QUINARY_TDM_TX:
|
||||
channels = tdm_tx_cfg[TDM_QUIN][TDM_0].channels;
|
||||
slots = tdm_slot[TDM_QUIN].num;
|
||||
slot_width = tdm_slot[TDM_QUIN].width;
|
||||
slot_offset = tdm_tx_slot_offset[TDM_QUIN];
|
||||
break;
|
||||
case AFE_PORT_ID_SENARY_TDM_TX:
|
||||
channels = tdm_tx_cfg[TDM_SEN][TDM_0].channels;
|
||||
slots = tdm_slot[TDM_SEN].num;
|
||||
slot_width = tdm_slot[TDM_SEN].width;
|
||||
slot_offset = tdm_tx_slot_offset[TDM_SEN];
|
||||
break;
|
||||
default:
|
||||
pdata = snd_soc_card_get_drvdata(rtd->card);
|
||||
slots = pdata->tdm_max_slots;
|
||||
if (cpu_dai->id < AFE_PORT_ID_TDM_PORT_RANGE_START) {
|
||||
pr_err("%s: dai id 0x%x not supported\n",
|
||||
__func__, cpu_dai->id);
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
for (i = 0; i < TDM_SLOT_OFFSET_MAX; i++) {
|
||||
if (slot_offset[i] != AFE_SLOT_MAPPING_OFFSET_INVALID)
|
||||
offset_channels++;
|
||||
else
|
||||
break;
|
||||
}
|
||||
/* RX or TX */
|
||||
path_dir = cpu_dai->id % MAX_PATH;
|
||||
|
||||
if (offset_channels == 0) {
|
||||
pr_err("%s: invalid offset_channels %d\n",
|
||||
__func__, offset_channels);
|
||||
/* PRI, SEC, TERT, QUAT, QUIN, ... */
|
||||
interface = (cpu_dai->id - AFE_PORT_ID_TDM_PORT_RANGE_START)
|
||||
/ (MAX_PATH * TDM_PORT_MAX);
|
||||
|
||||
/* 0, 1, 2, .. 7 */
|
||||
channel_interface =
|
||||
((cpu_dai->id - AFE_PORT_ID_TDM_PORT_RANGE_START) / MAX_PATH)
|
||||
% TDM_PORT_MAX;
|
||||
|
||||
pr_debug("%s: path dir: %u, interface %u, channel interface %u\n",
|
||||
__func__, path_dir, interface, channel_interface);
|
||||
|
||||
config = ((struct tdm_dev_config *) tdm_cfg[interface]) +
|
||||
(path_dir * TDM_PORT_MAX) + channel_interface;
|
||||
if (!config) {
|
||||
pr_err("%s: tdm config is NULL\n", __func__);
|
||||
return -EINVAL;
|
||||
}
|
||||
slot_offset = config->tdm_slot_offset;
|
||||
if (!slot_offset) {
|
||||
pr_err("%s: slot offset is NULL\n", __func__);
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
if (channels > offset_channels) {
|
||||
pr_err("%s: channels %d exceed offset_channels %d\n",
|
||||
__func__, channels, offset_channels);
|
||||
return -EINVAL;
|
||||
}
|
||||
if (path_dir)
|
||||
channels = tdm_tx_cfg[interface][channel_interface].channels;
|
||||
else
|
||||
channels = tdm_rx_cfg[interface][channel_interface].channels;
|
||||
|
||||
if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
|
||||
/*2 slot config - bits 0 and 1 set for the first two slots */
|
||||
slot_mask = 0xFFFFFFFF >> (32-channels);
|
||||
slot_mask = 0x0000FFFF >> (16 - slots);
|
||||
|
||||
pr_debug("%s: tdm rx slot_width %d slots %d slot_mask %x\n",
|
||||
__func__, slot_width, slots, slot_mask);
|
||||
|
|
@ -5715,7 +5158,7 @@ static int lahaina_tdm_snd_hw_params(struct snd_pcm_substream *substream,
|
|||
}
|
||||
} else if (substream->stream == SNDRV_PCM_STREAM_CAPTURE) {
|
||||
/*2 slot config - bits 0 and 1 set for the first two slots */
|
||||
slot_mask = 0xFFFFFFFF >> (32-channels);
|
||||
slot_mask = 0x0000FFFF >> (16 - slots);
|
||||
|
||||
pr_debug("%s: tdm tx slot_width %d slots %d slot_mask %x\n",
|
||||
__func__, slot_width, slots, slot_mask);
|
||||
|
|
@ -5746,12 +5189,6 @@ static int lahaina_tdm_snd_hw_params(struct snd_pcm_substream *substream,
|
|||
|
||||
rate = params_rate(params);
|
||||
clk_freq = rate * slot_width * slots;
|
||||
if (clk_freq > 24576000) {
|
||||
ret = -EINVAL;
|
||||
pr_err("%s: clk frequency > 24.576MHz %d\n",
|
||||
__func__, clk_freq);
|
||||
goto end;
|
||||
}
|
||||
ret = snd_soc_dai_set_sysclk(cpu_dai, 0, clk_freq, SND_SOC_CLOCK_OUT);
|
||||
if (ret < 0)
|
||||
pr_err("%s: failed to set tdm clk, err:%d\n",
|
||||
|
|
@ -7383,17 +6820,13 @@ static struct snd_soc_dai_link msm_common_be_dai_links[] = {
|
|||
.ignore_suspend = 1,
|
||||
SND_SOC_DAILINK_REG(usb_audio_tx),
|
||||
},
|
||||
};
|
||||
|
||||
|
||||
static struct snd_soc_dai_link msm_tdm_be_dai_links[] = {
|
||||
{
|
||||
.name = LPASS_BE_PRI_TDM_RX_0,
|
||||
.stream_name = "Primary TDM0 Playback",
|
||||
.no_pcm = 1,
|
||||
.dpcm_playback = 1,
|
||||
.id = MSM_BACKEND_DAI_PRI_TDM_RX_0,
|
||||
.be_hw_params_fixup = lahaina_tdm_be_hw_params_fixup,
|
||||
.be_hw_params_fixup = msm_be_hw_params_fixup,
|
||||
.ops = &lahaina_tdm_be_ops,
|
||||
.ignore_suspend = 1,
|
||||
.ignore_pmdown_time = 1,
|
||||
|
|
@ -7405,7 +6838,7 @@ static struct snd_soc_dai_link msm_tdm_be_dai_links[] = {
|
|||
.no_pcm = 1,
|
||||
.dpcm_capture = 1,
|
||||
.id = MSM_BACKEND_DAI_PRI_TDM_TX_0,
|
||||
.be_hw_params_fixup = lahaina_tdm_be_hw_params_fixup,
|
||||
.be_hw_params_fixup = msm_be_hw_params_fixup,
|
||||
.ops = &lahaina_tdm_be_ops,
|
||||
.ignore_suspend = 1,
|
||||
SND_SOC_DAILINK_REG(pri_tdm_tx_0),
|
||||
|
|
@ -7416,7 +6849,7 @@ static struct snd_soc_dai_link msm_tdm_be_dai_links[] = {
|
|||
.no_pcm = 1,
|
||||
.dpcm_playback = 1,
|
||||
.id = MSM_BACKEND_DAI_SEC_TDM_RX_0,
|
||||
.be_hw_params_fixup = lahaina_tdm_be_hw_params_fixup,
|
||||
.be_hw_params_fixup = msm_be_hw_params_fixup,
|
||||
.ops = &lahaina_tdm_be_ops,
|
||||
.ignore_suspend = 1,
|
||||
.ignore_pmdown_time = 1,
|
||||
|
|
@ -7428,7 +6861,7 @@ static struct snd_soc_dai_link msm_tdm_be_dai_links[] = {
|
|||
.no_pcm = 1,
|
||||
.dpcm_capture = 1,
|
||||
.id = MSM_BACKEND_DAI_SEC_TDM_TX_0,
|
||||
.be_hw_params_fixup = lahaina_tdm_be_hw_params_fixup,
|
||||
.be_hw_params_fixup = msm_be_hw_params_fixup,
|
||||
.ops = &lahaina_tdm_be_ops,
|
||||
.ignore_suspend = 1,
|
||||
SND_SOC_DAILINK_REG(sec_tdm_tx_0),
|
||||
|
|
@ -7439,7 +6872,7 @@ static struct snd_soc_dai_link msm_tdm_be_dai_links[] = {
|
|||
.no_pcm = 1,
|
||||
.dpcm_playback = 1,
|
||||
.id = MSM_BACKEND_DAI_TERT_TDM_RX_0,
|
||||
.be_hw_params_fixup = lahaina_tdm_be_hw_params_fixup,
|
||||
.be_hw_params_fixup = msm_be_hw_params_fixup,
|
||||
.ops = &lahaina_tdm_be_ops,
|
||||
.ignore_suspend = 1,
|
||||
.ignore_pmdown_time = 1,
|
||||
|
|
@ -7451,7 +6884,7 @@ static struct snd_soc_dai_link msm_tdm_be_dai_links[] = {
|
|||
.no_pcm = 1,
|
||||
.dpcm_capture = 1,
|
||||
.id = MSM_BACKEND_DAI_TERT_TDM_TX_0,
|
||||
.be_hw_params_fixup = lahaina_tdm_be_hw_params_fixup,
|
||||
.be_hw_params_fixup = msm_be_hw_params_fixup,
|
||||
.ops = &lahaina_tdm_be_ops,
|
||||
.ignore_suspend = 1,
|
||||
SND_SOC_DAILINK_REG(tert_tdm_tx_0),
|
||||
|
|
@ -7462,7 +6895,7 @@ static struct snd_soc_dai_link msm_tdm_be_dai_links[] = {
|
|||
.no_pcm = 1,
|
||||
.dpcm_playback = 1,
|
||||
.id = MSM_BACKEND_DAI_QUAT_TDM_RX_0,
|
||||
.be_hw_params_fixup = lahaina_tdm_be_hw_params_fixup,
|
||||
.be_hw_params_fixup = msm_be_hw_params_fixup,
|
||||
.ops = &lahaina_tdm_be_ops,
|
||||
.ignore_suspend = 1,
|
||||
.ignore_pmdown_time = 1,
|
||||
|
|
@ -7474,7 +6907,7 @@ static struct snd_soc_dai_link msm_tdm_be_dai_links[] = {
|
|||
.no_pcm = 1,
|
||||
.dpcm_capture = 1,
|
||||
.id = MSM_BACKEND_DAI_QUAT_TDM_TX_0,
|
||||
.be_hw_params_fixup = lahaina_tdm_be_hw_params_fixup,
|
||||
.be_hw_params_fixup = msm_be_hw_params_fixup,
|
||||
.ops = &lahaina_tdm_be_ops,
|
||||
.ignore_suspend = 1,
|
||||
SND_SOC_DAILINK_REG(quat_tdm_tx_0),
|
||||
|
|
@ -7485,7 +6918,7 @@ static struct snd_soc_dai_link msm_tdm_be_dai_links[] = {
|
|||
.no_pcm = 1,
|
||||
.dpcm_playback = 1,
|
||||
.id = MSM_BACKEND_DAI_QUIN_TDM_RX_0,
|
||||
.be_hw_params_fixup = lahaina_tdm_be_hw_params_fixup,
|
||||
.be_hw_params_fixup = msm_be_hw_params_fixup,
|
||||
.ops = &lahaina_tdm_be_ops,
|
||||
.ignore_suspend = 1,
|
||||
.ignore_pmdown_time = 1,
|
||||
|
|
@ -7497,7 +6930,7 @@ static struct snd_soc_dai_link msm_tdm_be_dai_links[] = {
|
|||
.no_pcm = 1,
|
||||
.dpcm_capture = 1,
|
||||
.id = MSM_BACKEND_DAI_QUIN_TDM_TX_0,
|
||||
.be_hw_params_fixup = lahaina_tdm_be_hw_params_fixup,
|
||||
.be_hw_params_fixup = msm_be_hw_params_fixup,
|
||||
.ops = &lahaina_tdm_be_ops,
|
||||
.ignore_suspend = 1,
|
||||
SND_SOC_DAILINK_REG(quin_tdm_tx_0),
|
||||
|
|
@ -7508,7 +6941,7 @@ static struct snd_soc_dai_link msm_tdm_be_dai_links[] = {
|
|||
.no_pcm = 1,
|
||||
.dpcm_playback = 1,
|
||||
.id = MSM_BACKEND_DAI_SEN_TDM_RX_0,
|
||||
.be_hw_params_fixup = lahaina_tdm_be_hw_params_fixup,
|
||||
.be_hw_params_fixup = msm_be_hw_params_fixup,
|
||||
.ops = &lahaina_tdm_be_ops,
|
||||
.ignore_suspend = 1,
|
||||
.ignore_pmdown_time = 1,
|
||||
|
|
@ -7520,7 +6953,7 @@ static struct snd_soc_dai_link msm_tdm_be_dai_links[] = {
|
|||
.no_pcm = 1,
|
||||
.dpcm_capture = 1,
|
||||
.id = MSM_BACKEND_DAI_SEN_TDM_TX_0,
|
||||
.be_hw_params_fixup = lahaina_tdm_be_hw_params_fixup,
|
||||
.be_hw_params_fixup = msm_be_hw_params_fixup,
|
||||
.ops = &lahaina_tdm_be_ops,
|
||||
.ignore_suspend = 1,
|
||||
SND_SOC_DAILINK_REG(sen_tdm_tx_0),
|
||||
|
|
@ -8133,7 +7566,6 @@ static struct snd_soc_dai_link msm_lahaina_dai_links[
|
|||
ARRAY_SIZE(msm_bolero_fe_dai_links) +
|
||||
ARRAY_SIZE(msm_common_misc_fe_dai_links) +
|
||||
ARRAY_SIZE(msm_common_be_dai_links) +
|
||||
ARRAY_SIZE(msm_tdm_be_dai_links) +
|
||||
ARRAY_SIZE(msm_mi2s_be_dai_links) +
|
||||
#ifndef CONFIG_AUXPCM_DISABLE
|
||||
ARRAY_SIZE(msm_auxpcm_be_dai_links) +
|
||||
|
|
@ -8504,11 +7936,6 @@ static struct snd_soc_card *populate_snd_card_dailinks(struct device *dev)
|
|||
sizeof(msm_common_be_dai_links));
|
||||
total_links += ARRAY_SIZE(msm_common_be_dai_links);
|
||||
|
||||
memcpy(msm_lahaina_dai_links + total_links,
|
||||
msm_tdm_be_dai_links,
|
||||
sizeof(msm_tdm_be_dai_links));
|
||||
total_links += ARRAY_SIZE(msm_tdm_be_dai_links);
|
||||
|
||||
memcpy(msm_lahaina_dai_links + total_links,
|
||||
msm_rx_tx_cdc_dma_be_dai_links,
|
||||
sizeof(msm_rx_tx_cdc_dma_be_dai_links));
|
||||
|
|
|
|||
Loading…
Add table
Reference in a new issue