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audio: asoc: Import tfa98xx codec

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From branch: redwood-s-oss

Change-Id: I72d6f9c1d583b413d1209fc9a5bf61eb58b1c06b
This commit is contained in:
Giovanni Ricca 2023-01-29 02:33:34 +05:30
parent 122c028ba3
commit f34760d67e
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36 changed files with 34636 additions and 0 deletions
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54
techpack/audio/asoc/codecs/tfa98xx/Android.mk Executable file
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# Android makefile for audio kernel modules
# Assume no targets will be supported
# Check if this driver needs be built for current target
ifeq ($(call is-board-platform,msmnile),true)
AUDIO_SELECT := CONFIG_SND_SOC_SM8150=m
endif
ifeq ($(call is-board-platform,$(MSMSTEPPE)),true)
AUDIO_SELECT := CONFIG_SND_SOC_SM6150=m
endif
AUDIO_CHIPSET := audio
# Build/Package only in case of supported target
ifeq ($(call is-board-platform-in-list,msmnile $(MSMSTEPPE)),true)
LOCAL_PATH := $(call my-dir)
# This makefile is only for DLKM
ifneq ($(findstring vendor,$(LOCAL_PATH)),)
ifneq ($(findstring opensource,$(LOCAL_PATH)),)
AUDIO_BLD_DIR := $(shell pwd)/vendor/qcom/opensource/audio-kernel
endif # opensource
DLKM_DIR := $(TOP)/device/qcom/common/dlkm
# Build audio.ko as $(AUDIO_CHIPSET)_audio.ko
###########################################################
# This is set once per LOCAL_PATH, not per (kernel) module
KBUILD_OPTIONS := AUDIO_ROOT=$(AUDIO_BLD_DIR)
# We are actually building audio.ko here, as per the
# requirement we are specifying <chipset>_audio.ko as LOCAL_MODULE.
# This means we need to rename the module to <chipset>_audio.ko
# after audio.ko is built.
KBUILD_OPTIONS += MODNAME=tfa98xx_dlkm
KBUILD_OPTIONS += BOARD_PLATFORM=$(TARGET_BOARD_PLATFORM)
KBUILD_OPTIONS += $(AUDIO_SELECT)
###########################################################
include $(CLEAR_VARS)
LOCAL_MODULE := $(AUDIO_CHIPSET)_tfa98xx.ko
LOCAL_MODULE_KBUILD_NAME := tfa98xx_dlkm.ko
LOCAL_MODULE_TAGS := optional
LOCAL_MODULE_DEBUG_ENABLE := true
LOCAL_MODULE_PATH := $(KERNEL_MODULES_OUT)
include $(DLKM_DIR)/AndroidKernelModule.mk
###########################################################
###########################################################
endif # DLKM check
endif # supported target check

123
techpack/audio/asoc/codecs/tfa98xx/Kbuild Executable file
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# We can build either as part of a standalone Kernel build or as
# an external module. Determine which mechanism is being used
ifeq ($(MODNAME),)
KERNEL_BUILD := 1
else
KERNEL_BUILD := 0
endif
ifeq ($(KERNEL_BUILD), 1)
# These are configurable via Kconfig for kernel-based builds
# Need to explicitly configure for Android-based builds
AUDIO_BLD_DIR := $(srctree)
AUDIO_ROOT := $(AUDIO_BLD_DIR)/techpack/audio
endif
ifeq ($(KERNEL_BUILD), 0)
ifeq ($(CONFIG_ARCH_SM8150), y)
include $(AUDIO_ROOT)/config/sm8150auto.conf
export
INCS += -include $(AUDIO_ROOT)/config/sm8150autoconf.h
endif
ifeq ($(CONFIG_ARCH_SM6150), y)
include $(AUDIO_ROOT)/config/sm8150auto.conf
export
INCS += -include $(AUDIO_ROOT)/config/sm8150autoconf.h
endif
ifeq ($(CONFIG_ARCH_SDMSHRIKE), y)
include $(AUDIO_ROOT)/config/sm8150auto.conf
export
INCS += -include $(AUDIO_ROOT)/config/sm8150autoconf.h
endif
endif
# As per target team, build is done as follows:
# Defconfig : build with default flags
# Slub : defconfig + CONFIG_SLUB_DEBUG := y +
# CONFIG_SLUB_DEBUG_ON := y + CONFIG_PAGE_POISONING := y
# Perf : Using appropriate msmXXXX-perf_defconfig
#
# Shipment builds (user variants) should not have any debug feature
# enabled. This is identified using 'TARGET_BUILD_VARIANT'. Slub builds
# are identified using the CONFIG_SLUB_DEBUG_ON configuration. Since
# there is no other way to identify defconfig builds, QTI internal
# representation of perf builds (identified using the string 'perf'),
# is used to identify if the build is a slub or defconfig one. This
# way no critical debug feature will be enabled for perf and shipment
# builds. Other OEMs are also protected using the TARGET_BUILD_VARIANT
# config.
############ UAPI ############
UAPI_DIR := uapi
UAPI_INC := -I$(AUDIO_ROOT)/include/$(UAPI_DIR)
############ COMMON ############
COMMON_DIR := include
COMMON_INC := -I$(AUDIO_ROOT)/$(COMMON_DIR)
TFA_INC := -I$(AUDIO_ROOT)/asoc/codecs/tfa98xx/inc
# for TFA9874 Amplifer
ifdef CONFIG_SND_SOC_TFA9874
#CDEFINES += -DTFA_NON_DSP_SOLUTION
TFA98XX_OBJS += src/tfa98xx.o
TFA98XX_OBJS += src/tfa_container.o
TFA98XX_OBJS += src/tfa_dsp.o
TFA98XX_OBJS += src/tfa_init.o
endif
LINUX_INC += -Iinclude/linux
INCS += $(COMMON_INC) \
$(UAPI_INC) \
$(TFA_INC)
EXTRA_CFLAGS += $(INCS)
CDEFINES += -DANI_LITTLE_BYTE_ENDIAN \
-DANI_LITTLE_BIT_ENDIAN \
-DDOT11F_LITTLE_ENDIAN_HOST \
-DANI_COMPILER_TYPE_GCC \
-DANI_OS_TYPE_ANDROID=6 \
-DPTT_SOCK_SVC_ENABLE \
-Wall\
-Werror\
-D__linux__ \
-DDEBUG
ifeq ($(TARGET_PRODUCT), $(filter $(TARGET_PRODUCT),renoir))
CDEFINES += -DCONFIG_TARGET_PRODUCT_RENOIR
endif
KBUILD_CPPFLAGS += $(CDEFINES)
# Currently, for versions of gcc which support it, the kernel Makefile
# is disabling the maybe-uninitialized warning. Re-enable it for the
# AUDIO driver. Note that we must use EXTRA_CFLAGS here so that it
# will override the kernel settings.
ifeq ($(call cc-option-yn, -Wmaybe-uninitialized),y)
EXTRA_CFLAGS += -Wmaybe-uninitialized
endif
#EXTRA_CFLAGS += -Wmissing-prototypes
ifeq ($(call cc-option-yn, -Wheader-guard),y)
EXTRA_CFLAGS += -Wheader-guard
endif
ifeq ($(KERNEL_BUILD), 0)
KBUILD_EXTRA_SYMBOLS +=$(OUT)/obj/vendor/qcom/opensource/audio-kernel/ipc/Module.symvers
KBUILD_EXTRA_SYMBOLS +=$(OUT)/obj/vendor/qcom/opensource/audio-kernel/dsp/Module.symvers
KBUILD_EXTRA_SYMBOLS +=$(OUT)/obj/vendor/qcom/opensource/audio-kernel/asoc/Module.symvers
KBUILD_EXTRA_SYMBOLS +=$(OUT)/obj/vendor/qcom/opensource/audio-kernel/asoc/codecs/Module.symvers
KBUILD_EXTRA_SYMBOLS +=$(OUT)/obj/vendor/qcom/opensource/audio-kernel/soc/Module.symvers
endif
# Module information used by KBuild framework
obj-$(CONFIG_SND_SOC_TFA9874) += tfa98xx_dlkm.o
tfa98xx_dlkm-y := $(TFA98XX_OBJS)
# inject some build related information
DEFINES += -DBUILD_TIMESTAMP=\"$(shell date -u +'%Y-%m-%dT%H:%M:%SZ')\"

37
techpack/audio/asoc/codecs/tfa98xx/inc/config.h Executable file
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/*
* Copyright (C) 2014-2020 NXP Semiconductors, All Rights Reserved.
* Copyright 2020 GOODIX
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
*/
/*
Linux kernel specific definitions used by code shared with
Linux/Windows user space.
*/
#ifndef __CONFIG_LINUX_KERNEL_INC__
#define __CONFIG_LINUX_KERNEL_INC__
#include <linux/ctype.h>
#include <linux/delay.h>
#include <linux/slab.h>
#include <linux/crc32.h>
#include <linux/ftrace.h>
#define _ASSERT(e)
#define PRINT_ASSERT(e)if ((e)) printk(KERN_ERR "PrintAssert:%s (%s:%d) error code:%d\n",__FUNCTION__,__FILE__,__LINE__, e)
#if defined(CONFIG_TRACING) && defined(DEBUG)
#define tfa98xx_trace_printk(...) trace_printk(__VA_ARGS__)
#else
#define tfa98xx_trace_printk(...)
#endif
#endif /* __CONFIG_LINUX_KERNEL_INC__ */

160
techpack/audio/asoc/codecs/tfa98xx/inc/dbgprint.h Executable file
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/*
* Copyright (C) 2014-2020 NXP Semiconductors, All Rights Reserved.
* Copyright 2020 GOODIX
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
*/
#ifndef _DBGPRINT_H
# define _DBGPRINT_H
/* Debugging macro's. */
# ifndef DEBUG
# define DEBUG
# endif
# ifndef ASSERT
//#define ASSERT
# endif
//TODO wwwim
# ifndef _ASSERT
#define _ASSERT(e)
# endif
# ifndef PREFIX
# define PREFIX "tfa98xx: "
# define DRIVER_NAME "tfa98xx"
# endif
#ifdef __KERNEL__
# ifdef DEBUG
# define _DEBUG(level,fmt,va...) do {\
if (unlikely(debug >= (level))) \
printk(KERN_INFO PREFIX "%s:%d: "fmt,__func__,__LINE__,##va); \
} while (0)
# else
# define _DEBUG(level,fmt,va...) do {} while(0)
# endif
# define MSG(fmt,va...) printk(KERN_INFO PREFIX "%s:%d: "fmt,__func__,__LINE__,##va)
# define _ERRORMSG(fmt,va...) printk(KERN_ERR PREFIX "ERROR %s:%d: "fmt,__func__,__LINE__, ##va)
# define DEBUG0(x...) MSG(x)
# define DEBUG1(x...) _DEBUG(1,x)
# define DEBUG2(x...) _DEBUG(2,x)
# define DEBUG3(x...) _DEBUG(3,x)
# define ERRORMSG(x...) _ERRORMSG(x)
# define PRINT(x...) printk(x)
# define PRINT_ERROR(x...) printk(KERN_INFO PREFIX " **ERROR** " x)
# define PRINT_ASSERT(e)if ((e)) printk(KERN_ERR "PrintAssert:%s (%s:%d) error code:%d\n",__FUNCTION__,__FILE__,__LINE__, e)
# define PRINT_ENTRY DEBUG2("+[%s]\n", __func__)
# define PRINT_EXIT DEBUG2("-[%s]\n", __func__)
# ifdef ASSERT
# define assert(cond,action) do { if (unlikely(!(cond))) { DEBUG0("Assert: %s\n",#cond); action; }} while(0)
# else
# define assert(cond,action) do { } while (0)
# endif
#else /* __KERNEL__ */
#if defined(WIN32) || defined(_X64)
#include <stdio.h>
/* user mode */
# ifdef DEBUG
# define _DEBUGMSG(level,fmt,...) printf(PREFIX "%s:%d: "fmt,__FUNCTION__,__LINE__,__VA_ARGS__);
# else
# define _DEBUGMSG(level,fmt,...) do {} while(0)
# endif
# define _ERRORMSG(fmt,...) printf(PREFIX "%s:%s:%d: "fmt,__FILE__,__FUNCTION__,__LINE__,__VA_ARGS__)
# define DEBUG0(...) MSG(__VA_ARGS__)
# define DEBUG1(...) _DEBUGMSG(1,__VA_ARGS__)
# define DEBUG2(...) _DEBUGMSG(2,__VA_ARGS__)
# define DEBUG3(...) _DEBUGMSG(3,__VA_ARGS__)
# define ERRORMSG(fmt,...) _ERRORMSG(fmt,__VA_ARGS__)
# define PRINT(...) printf(__VA_ARGS__)
/*
# define PRINT(...) { FILE *stream; \
if((stream = freopen("tfa_tfa.txt", "ab+", stdout)) == NULL) exit(-1); \
printf(__VA_ARGS__); \
freopen( "CON", "ab+", stdout ); \
}
*/
# define PRINT_ERROR(...) fprintf(stderr,__VA_ARGS__)
# define PRINT_FILE(file,...) fprintf(file,__VA_ARGS__)
# define PRINT_ASSERT(e)if ((e)) fprintf(stderr, "PrintAssert:%s (%s:%d) error code:%d\n",__FUNCTION__,__FILE__,__LINE__, e)
//# define PRINT_ASSERT(e) if ((e)) fprintf(stderr, "PrintAssert:%s (%s:%d) %s\n",__FUNCTION__,__FILE__,__LINE__, Tfa98xx_GetErrorString(e))
#elif defined(__CODE_RED)
#include "app_global.h"
# ifdef DEBUG
# define _DEBUG(level,fmt,va...) TB_TRACE_INF(TbTracePfx2("tfa",TB_FUNC,va))
//printf(PREFIX "%s:%d: "fmt,__func__,__LINE__,##va);
# else
# define _DEBUG(level,fmt,va...) do {} while(0)
# endif
# define MSG(fmt,...) TB_TRACE_INF(TbTracePfx2("tfa",TB_FUNC,__VA_ARGS__))
//printf(PREFIX "%s:%s:%d: "fmt,__FILE__,__func__,__LINE__,##va)
//TB_TRACE_INF(TbTracePfx2(APP_PFX,TB_FUNC,"path=%s, chan=%u, muted=%s, vol=%d\n",
// path->isRecording ? "recording" : "playback",
// i,
// channelVol.currentMuteValue ? "YES" : "NO",
// channelVol.currentVolumeValue
// ));
//# define _ERRORMSG(fmt,va...) TB_TRACE_INF(TbTracePfx2("tfa",TB_FUNC,va))
# define ERRORMSG(...) TB_TRACE_INF(TbTracePfx2("tfa",TB_FUNC,__VA_ARGS__))
//fprintf(stderr, PREFIX "ERROR %s:%s:%d: "fmt,__FILE__,__func__,__LINE__, ##va)
# define DEBUG0(x...) MSG(x)
# define DEBUG1(x...) _DEBUG(1,x)
# define DEBUG2(x...) _DEBUG(2,x)
# define DEBUG3(x...) _DEBUG(3,x)
//# define ERRORMSG(x...) _ERRORMSG(x)
# define PRINT(x...) TB_TRACE_INF(TbTracePfx2("tfa",TB_FUNC,x))
//printf(x)
# define PRINT_ERROR(x...) TB_TRACE_INF(TbTracePfx2("tfa",TB_FUNC,x))
//fprintf(stderr,__VA_ARGS__)
# define PRINT_FILE(file,x...) TB_TRACE_INF(TbTracePfx2("tfa",TB_FUNC,x))
//fprintf(file,__VA_ARGS__)
# define PRINT_ASSERT(e)
//TB_TRACE_INF(TbTracePfx2("tfa",TB_FUNC,Tfa98xx_GetErrorString(e)))
//if ((e)) fprintf(stderr, "PrintAssert:%s (%s:%d) %s\n",__FUNCTION__,__FILE__,__LINE__, Tfa98xx_GetErrorString(e))
#else
#include <stdio.h>
/* user mode */
# ifdef DEBUG
# define _DEBUG(level,fmt,va...) printf(PREFIX "%s:%d: "fmt,__func__,__LINE__,##va);
# else
# define _DEBUG(level,fmt,va...) do {} while(0)
# endif
# define MSG(fmt,va...) printf(PREFIX "%s:%s:%d: "fmt,__FILE__,__func__,__LINE__,##va)
# define _ERRORMSG(fmt,va...) fprintf(stderr, PREFIX "ERROR %s:%s:%d: "fmt,__FILE__,__func__,__LINE__, ##va)
# define DEBUG0(x...) MSG(x)
# define DEBUG1(x...) _DEBUG(1,x)
# define DEBUG2(x...) _DEBUG(2,x)
# define DEBUG3(x...) _DEBUG(3,x)
# define ERRORMSG(x...) _ERRORMSG(x)
# define PRINT(x...) printf(x)
# define PRINT_ERROR(...) fprintf(stderr,__VA_ARGS__)
# define PRINT_FILE(file,...) fprintf(file,__VA_ARGS__)
# define PRINT_ASSERT(e)if ((e)) fprintf(stderr, "PrintAssert:%s (%s:%d) error code:%d\n",__FUNCTION__,__FILE__,__LINE__, e)
//# define PRINT_ASSERT(e) if ((e)) fprintf(stderr, "PrintAssert:%s (%s:%d) %s\n",__FUNCTION__,__FILE__,__LINE__, Tfa98xx_GetErrorString(e))
#endif /* WIN32 */
#endif /* user */
#endif /* _DBGPRINT_H --------------- */

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techpack/audio/asoc/codecs/tfa98xx/inc/tfa.h Executable file
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/*
* Copyright (C) 2014-2020 NXP Semiconductors, All Rights Reserved.
* Copyright 2020 GOODIX
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
*/
#ifndef TFA_H_
#define TFA_H_
/* set the limit for the container file length */
#define TFA_MAX_CNT_LENGTH (256*1024)
extern struct tfa_device **devs;
/**
* tfa error return codes
*/
enum tfa_error {
tfa_error_ok, /**< no error */
tfa_error_device, /**< no response from device */
tfa_error_bad_param,/**< parameter no accepted */
tfa_error_noclock, /**< required clock not present */
tfa_error_timeout, /**< a timeout occurred */
tfa_error_dsp, /**< a DSP error was returned */
tfa_error_container,/**< no or wrong container file */
tfa_error_max /**< impossible value, max enum */
};
enum Tfa98xx_Error tfa_write_filters(struct tfa_device *tfa, int prof_idx);
struct tfa_device ** tfa_devs_create(int count);
void tfa_devs_destroy(int count);
struct tfa_device ** tfa_get_device_struct(void);
int tfa_plop_noise_interrupt(struct tfa_device *tfa, int profile, int vstep);
void tfa_lp_mode_interrupt(struct tfa_device *tfa);
void tfa_adapt_noisemode(struct tfa_device *tfa);
#endif /* TFA_H_ */

911
techpack/audio/asoc/codecs/tfa98xx/inc/tfa1_tfafieldnames.h Executable file
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/*
* Copyright (C) 2014-2020 NXP Semiconductors, All Rights Reserved.
* Copyright 2020 GOODIX
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
*/
/** Filename: Tfa1_TfaFieldnames.h
* This file was generated automatically on 03/20/2015 at 01:55:46 PM.
* Source file: TFA9897N1B_I2C_list_URT_Source_v34.xls
*/
#define TFA9897_I2CVERSION 34
typedef enum Tfa1BfEnumList {
TFA1_BF_VDDS = 0x0000, /*!< Power-on-reset flag */
TFA1_BF_PLLS = 0x0010, /*!< PLL lock */
TFA1_BF_OTDS = 0x0020, /*!< Over Temperature Protection alarm */
TFA1_BF_OVDS = 0x0030, /*!< Over Voltage Protection alarm */
TFA1_BF_UVDS = 0x0040, /*!< Under Voltage Protection alarm */
TFA1_BF_OCDS = 0x0050, /*!< Over Current Protection alarm */
TFA1_BF_CLKS = 0x0060, /*!< Clocks stable flag */
TFA1_BF_CLIPS = 0x0070, /*!< Amplifier clipping */
TFA1_BF_MTPB = 0x0080, /*!< MTP busy */
TFA1_BF_NOCLK = 0x0090, /*!< Flag lost clock from clock generation unit */
TFA1_BF_SPKS = 0x00a0, /*!< Speaker error flag */
TFA1_BF_ACS = 0x00b0, /*!< Cold Start flag */
TFA1_BF_SWS = 0x00c0, /*!< Flag Engage */
TFA1_BF_WDS = 0x00d0, /*!< Flag watchdog reset */
TFA1_BF_AMPS = 0x00e0, /*!< Amplifier is enabled by manager */
TFA1_BF_AREFS = 0x00f0, /*!< References are enabled by manager */
TFA1_BF_BATS = 0x0109, /*!< Battery voltage readout; 0 .. 5.5 [V] */
TFA1_BF_TEMPS = 0x0208, /*!< Temperature readout from the temperature sensor */
TFA1_BF_REV = 0x030b, /*!< Device type number is B97 */
TFA1_BF_RCV = 0x0420, /*!< Enable Receiver Mode */
TFA1_BF_CHS12 = 0x0431, /*!< Channel Selection TDM input for Coolflux */
TFA1_BF_INPLVL= 0x0450, /*!< Input level selection control */
TFA1_BF_CHSA = 0x0461, /*!< Input selection for amplifier */
TFA1_BF_I2SDOE= 0x04b0, /*!< Enable data output */
TFA1_BF_AUDFS = 0x04c3, /*!< Audio sample rate setting */
TFA1_BF_BSSCR = 0x0501, /*!< Protection Attack Time */
TFA1_BF_BSST = 0x0523, /*!< ProtectionThreshold */
TFA1_BF_BSSRL = 0x0561, /*!< Protection Maximum Reduction */
TFA1_BF_BSSRR = 0x0582, /*!< Battery Protection Release Time */
TFA1_BF_BSSHY = 0x05b1, /*!< Battery Protection Hysteresis */
TFA1_BF_BSSR = 0x05e0, /*!< battery voltage for I2C read out only */
TFA1_BF_BSSBY = 0x05f0, /*!< bypass clipper battery protection */
TFA1_BF_DPSA = 0x0600, /*!< Enable dynamic powerstage activation */
TFA1_BF_CFSM = 0x0650, /*!< Soft mute in CoolFlux */
TFA1_BF_BSSS = 0x0670, /*!< BatSenseSteepness */
TFA1_BF_VOL = 0x0687, /*!< volume control (in CoolFlux) */
TFA1_BF_DCVO = 0x0702, /*!< Boost Voltage */
TFA1_BF_DCMCC = 0x0733, /*!< Max boost coil current - step of 175 mA */
TFA1_BF_DCIE = 0x07a0, /*!< Adaptive boost mode */
TFA1_BF_DCSR = 0x07b0, /*!< Soft RampUp/Down mode for DCDC controller */
TFA1_BF_DCPAVG= 0x07c0, /*!< ctrl_peak2avg for analog part of DCDC */
TFA1_BF_TROS = 0x0800, /*!< Select external temperature also the ext_temp will be put on the temp read out */
TFA1_BF_EXTTS = 0x0818, /*!< external temperature setting to be given by host */
TFA1_BF_PWDN = 0x0900, /*!< Device Mode */
TFA1_BF_I2CR = 0x0910, /*!< I2C Reset */
TFA1_BF_CFE = 0x0920, /*!< Enable CoolFlux */
TFA1_BF_AMPE = 0x0930, /*!< Enable Amplifier */
TFA1_BF_DCA = 0x0940, /*!< EnableBoost */
TFA1_BF_SBSL = 0x0950, /*!< Coolflux configured */
TFA1_BF_AMPC = 0x0960, /*!< Selection on how Amplifier is enabled */
TFA1_BF_DCDIS = 0x0970, /*!< DCDC not connected */
TFA1_BF_PSDR = 0x0980, /*!< IDDQ test amplifier */
TFA1_BF_DCCV = 0x0991, /*!< Coil Value */
TFA1_BF_CCFD = 0x09b0, /*!< Selection CoolFlux Clock */
TFA1_BF_INTPAD= 0x09c1, /*!< INT pad configuration control */
TFA1_BF_IPLL = 0x09e0, /*!< PLL input reference clock selection */
TFA1_BF_MTPK = 0x0b07, /*!< 5Ah, 90d To access KEY1_Protected registers (Default for engineering) */
TFA1_BF_CVFDLY= 0x0c25, /*!< Fractional delay adjustment between current and voltage sense */
TFA1_BF_TDMPRF= 0x1011, /*!< TDM_usecase */
TFA1_BF_TDMEN = 0x1030, /*!< TDM interface control */
TFA1_BF_TDMCKINV= 0x1040, /*!< TDM clock inversion */
TFA1_BF_TDMFSLN= 0x1053, /*!< TDM FS length */
TFA1_BF_TDMFSPOL= 0x1090, /*!< TDM FS polarity */
TFA1_BF_TDMSAMSZ= 0x10a4, /*!< TDM Sample Size for all tdm sinks/sources */
TFA1_BF_TDMSLOTS= 0x1103, /*!< Number of slots */
TFA1_BF_TDMSLLN= 0x1144, /*!< Slot length */
TFA1_BF_TDMBRMG= 0x1194, /*!< Bits remaining */
TFA1_BF_TDMDDEL= 0x11e0, /*!< Data delay */
TFA1_BF_TDMDADJ= 0x11f0, /*!< Data adjustment */
TFA1_BF_TDMTXFRM= 0x1201, /*!< TXDATA format */
TFA1_BF_TDMUUS0= 0x1221, /*!< TXDATA format unused slot sd0 */
TFA1_BF_TDMUUS1= 0x1241, /*!< TXDATA format unused slot sd1 */
TFA1_BF_TDMSI0EN= 0x1270, /*!< TDM sink0 enable */
TFA1_BF_TDMSI1EN= 0x1280, /*!< TDM sink1 enable */
TFA1_BF_TDMSI2EN= 0x1290, /*!< TDM sink2 enable */
TFA1_BF_TDMSO0EN= 0x12a0, /*!< TDM source0 enable */
TFA1_BF_TDMSO1EN= 0x12b0, /*!< TDM source1 enable */
TFA1_BF_TDMSO2EN= 0x12c0, /*!< TDM source2 enable */
TFA1_BF_TDMSI0IO= 0x12d0, /*!< tdm_sink0_io */
TFA1_BF_TDMSI1IO= 0x12e0, /*!< tdm_sink1_io */
TFA1_BF_TDMSI2IO= 0x12f0, /*!< tdm_sink2_io */
TFA1_BF_TDMSO0IO= 0x1300, /*!< tdm_source0_io */
TFA1_BF_TDMSO1IO= 0x1310, /*!< tdm_source1_io */
TFA1_BF_TDMSO2IO= 0x1320, /*!< tdm_source2_io */
TFA1_BF_TDMSI0SL= 0x1333, /*!< sink0_slot [GAIN IN] */
TFA1_BF_TDMSI1SL= 0x1373, /*!< sink1_slot [CH1 IN] */
TFA1_BF_TDMSI2SL= 0x13b3, /*!< sink2_slot [CH2 IN] */
TFA1_BF_TDMSO0SL= 0x1403, /*!< source0_slot [GAIN OUT] */
TFA1_BF_TDMSO1SL= 0x1443, /*!< source1_slot [Voltage Sense] */
TFA1_BF_TDMSO2SL= 0x1483, /*!< source2_slot [Current Sense] */
TFA1_BF_NBCK = 0x14c3, /*!< NBCK */
TFA1_BF_INTOVDDS= 0x2000, /*!< flag_por_int_out */
TFA1_BF_INTOPLLS= 0x2010, /*!< flag_pll_lock_int_out */
TFA1_BF_INTOOTDS= 0x2020, /*!< flag_otpok_int_out */
TFA1_BF_INTOOVDS= 0x2030, /*!< flag_ovpok_int_out */
TFA1_BF_INTOUVDS= 0x2040, /*!< flag_uvpok_int_out */
TFA1_BF_INTOOCDS= 0x2050, /*!< flag_ocp_alarm_int_out */
TFA1_BF_INTOCLKS= 0x2060, /*!< flag_clocks_stable_int_out */
TFA1_BF_INTOCLIPS= 0x2070, /*!< flag_clip_int_out */
TFA1_BF_INTOMTPB= 0x2080, /*!< mtp_busy_int_out */
TFA1_BF_INTONOCLK= 0x2090, /*!< flag_lost_clk_int_out */
TFA1_BF_INTOSPKS= 0x20a0, /*!< flag_cf_speakererror_int_out */
TFA1_BF_INTOACS= 0x20b0, /*!< flag_cold_started_int_out */
TFA1_BF_INTOSWS= 0x20c0, /*!< flag_engage_int_out */
TFA1_BF_INTOWDS= 0x20d0, /*!< flag_watchdog_reset_int_out */
TFA1_BF_INTOAMPS= 0x20e0, /*!< flag_enbl_amp_int_out */
TFA1_BF_INTOAREFS= 0x20f0, /*!< flag_enbl_ref_int_out */
TFA1_BF_INTOACK= 0x2201, /*!< Interrupt status register output - Corresponding flag */
TFA1_BF_INTIVDDS= 0x2300, /*!< flag_por_int_in */
TFA1_BF_INTIPLLS= 0x2310, /*!< flag_pll_lock_int_in */
TFA1_BF_INTIOTDS= 0x2320, /*!< flag_otpok_int_in */
TFA1_BF_INTIOVDS= 0x2330, /*!< flag_ovpok_int_in */
TFA1_BF_INTIUVDS= 0x2340, /*!< flag_uvpok_int_in */
TFA1_BF_INTIOCDS= 0x2350, /*!< flag_ocp_alarm_int_in */
TFA1_BF_INTICLKS= 0x2360, /*!< flag_clocks_stable_int_in */
TFA1_BF_INTICLIPS= 0x2370, /*!< flag_clip_int_in */
TFA1_BF_INTIMTPB= 0x2380, /*!< mtp_busy_int_in */
TFA1_BF_INTINOCLK= 0x2390, /*!< flag_lost_clk_int_in */
TFA1_BF_INTISPKS= 0x23a0, /*!< flag_cf_speakererror_int_in */
TFA1_BF_INTIACS= 0x23b0, /*!< flag_cold_started_int_in */
TFA1_BF_INTISWS= 0x23c0, /*!< flag_engage_int_in */
TFA1_BF_INTIWDS= 0x23d0, /*!< flag_watchdog_reset_int_in */
TFA1_BF_INTIAMPS= 0x23e0, /*!< flag_enbl_amp_int_in */
TFA1_BF_INTIAREFS= 0x23f0, /*!< flag_enbl_ref_int_in */
TFA1_BF_INTIACK= 0x2501, /*!< Interrupt register input */
TFA1_BF_INTENVDDS= 0x2600, /*!< flag_por_int_enable */
TFA1_BF_INTENPLLS= 0x2610, /*!< flag_pll_lock_int_enable */
TFA1_BF_INTENOTDS= 0x2620, /*!< flag_otpok_int_enable */
TFA1_BF_INTENOVDS= 0x2630, /*!< flag_ovpok_int_enable */
TFA1_BF_INTENUVDS= 0x2640, /*!< flag_uvpok_int_enable */
TFA1_BF_INTENOCDS= 0x2650, /*!< flag_ocp_alarm_int_enable */
TFA1_BF_INTENCLKS= 0x2660, /*!< flag_clocks_stable_int_enable */
TFA1_BF_INTENCLIPS= 0x2670, /*!< flag_clip_int_enable */
TFA1_BF_INTENMTPB= 0x2680, /*!< mtp_busy_int_enable */
TFA1_BF_INTENNOCLK= 0x2690, /*!< flag_lost_clk_int_enable */
TFA1_BF_INTENSPKS= 0x26a0, /*!< flag_cf_speakererror_int_enable */
TFA1_BF_INTENACS= 0x26b0, /*!< flag_cold_started_int_enable */
TFA1_BF_INTENSWS= 0x26c0, /*!< flag_engage_int_enable */
TFA1_BF_INTENWDS= 0x26d0, /*!< flag_watchdog_reset_int_enable */
TFA1_BF_INTENAMPS= 0x26e0, /*!< flag_enbl_amp_int_enable */
TFA1_BF_INTENAREFS= 0x26f0, /*!< flag_enbl_ref_int_enable */
TFA1_BF_INTENACK= 0x2801, /*!< Interrupt enable register */
TFA1_BF_INTPOLVDDS= 0x2900, /*!< flag_por_int_pol */
TFA1_BF_INTPOLPLLS= 0x2910, /*!< flag_pll_lock_int_pol */
TFA1_BF_INTPOLOTDS= 0x2920, /*!< flag_otpok_int_pol */
TFA1_BF_INTPOLOVDS= 0x2930, /*!< flag_ovpok_int_pol */
TFA1_BF_INTPOLUVDS= 0x2940, /*!< flag_uvpok_int_pol */
TFA1_BF_INTPOLOCDS= 0x2950, /*!< flag_ocp_alarm_int_pol */
TFA1_BF_INTPOLCLKS= 0x2960, /*!< flag_clocks_stable_int_pol */
TFA1_BF_INTPOLCLIPS= 0x2970, /*!< flag_clip_int_pol */
TFA1_BF_INTPOLMTPB= 0x2980, /*!< mtp_busy_int_pol */
TFA1_BF_INTPOLNOCLK= 0x2990, /*!< flag_lost_clk_int_pol */
TFA1_BF_INTPOLSPKS= 0x29a0, /*!< flag_cf_speakererror_int_pol */
TFA1_BF_INTPOLACS= 0x29b0, /*!< flag_cold_started_int_pol */
TFA1_BF_INTPOLSWS= 0x29c0, /*!< flag_engage_int_pol */
TFA1_BF_INTPOLWDS= 0x29d0, /*!< flag_watchdog_reset_int_pol */
TFA1_BF_INTPOLAMPS= 0x29e0, /*!< flag_enbl_amp_int_pol */
TFA1_BF_INTPOLAREFS= 0x29f0, /*!< flag_enbl_ref_int_pol */
TFA1_BF_INTPOLACK= 0x2b01, /*!< Interrupt status flags polarity register */
TFA1_BF_CLIP = 0x4900, /*!< Bypass clip control */
TFA1_BF_CIMTP = 0x62b0, /*!< start copying all the data from i2cregs_mtp to mtp [Key 2 protected] */
TFA1_BF_RST = 0x7000, /*!< Reset CoolFlux DSP */
TFA1_BF_DMEM = 0x7011, /*!< Target memory for access */
TFA1_BF_AIF = 0x7030, /*!< Autoincrement-flag for memory-address */
TFA1_BF_CFINT = 0x7040, /*!< Interrupt CoolFlux DSP */
TFA1_BF_REQ = 0x7087, /*!< request for access (8 channels) */
TFA1_BF_REQCMD= 0x7080, /*!< Firmware event request rpc command */
TFA1_BF_REQRST= 0x7090, /*!< Firmware event request reset restart */
TFA1_BF_REQMIPS= 0x70a0, /*!< Firmware event request short on mips */
TFA1_BF_REQMUTED= 0x70b0, /*!< Firmware event request mute sequence ready */
TFA1_BF_REQVOL= 0x70c0, /*!< Firmware event request volume ready */
TFA1_BF_REQDMG= 0x70d0, /*!< Firmware event request speaker damage detected */
TFA1_BF_REQCAL= 0x70e0, /*!< Firmware event request calibration completed */
TFA1_BF_REQRSV= 0x70f0, /*!< Firmware event request reserved */
TFA1_BF_MADD = 0x710f, /*!< memory-address to be accessed */
TFA1_BF_MEMA = 0x720f, /*!< activate memory access (24- or 32-bits data is written/read to/from memory */
TFA1_BF_ERR = 0x7307, /*!< Coolflux error flags */
TFA1_BF_ACK = 0x7387, /*!< acknowledge of requests (8 channels) */
TFA1_BF_MTPOTC= 0x8000, /*!< Calibration schedule (key2 protected) */
TFA1_BF_MTPEX = 0x8010, /*!< (key2 protected) */
} Tfa1BfEnumList_t;
#define TFA1_NAMETABLE static tfaBfName_t Tfa1DatasheetNames[]= {\
{ 0x0, "VDDS"}, /* Power-on-reset flag , */\
{ 0x10, "PLLS"}, /* PLL lock , */\
{ 0x20, "OTDS"}, /* Over Temperature Protection alarm , */\
{ 0x30, "OVDS"}, /* Over Voltage Protection alarm , */\
{ 0x40, "UVDS"}, /* Under Voltage Protection alarm , */\
{ 0x50, "OCDS"}, /* Over Current Protection alarm , */\
{ 0x60, "CLKS"}, /* Clocks stable flag , */\
{ 0x70, "CLIPS"}, /* Amplifier clipping , */\
{ 0x80, "MTPB"}, /* MTP busy , */\
{ 0x90, "NOCLK"}, /* Flag lost clock from clock generation unit , */\
{ 0xa0, "SPKS"}, /* Speaker error flag , */\
{ 0xb0, "ACS"}, /* Cold Start flag , */\
{ 0xc0, "SWS"}, /* Flag Engage , */\
{ 0xd0, "WDS"}, /* Flag watchdog reset , */\
{ 0xe0, "AMPS"}, /* Amplifier is enabled by manager , */\
{ 0xf0, "AREFS"}, /* References are enabled by manager , */\
{ 0x109, "BATS"}, /* Battery voltage readout; 0 .. 5.5 [V] , */\
{ 0x208, "TEMPS"}, /* Temperature readout from the temperature sensor , */\
{ 0x30b, "REV"}, /* Device type number is B97 , */\
{ 0x420, "RCV"}, /* Enable Receiver Mode , */\
{ 0x431, "CHS12"}, /* Channel Selection TDM input for Coolflux , */\
{ 0x450, "INPLVL"}, /* Input level selection control , */\
{ 0x461, "CHSA"}, /* Input selection for amplifier , */\
{ 0x4b0, "I2SDOE"}, /* Enable data output , */\
{ 0x4c3, "AUDFS"}, /* Audio sample rate setting , */\
{ 0x501, "SSCR"}, /* Protection Attack Time , */\
{ 0x523, "SST"}, /* ProtectionThreshold , */\
{ 0x561, "SSRL"}, /* Protection Maximum Reduction , */\
{ 0x582, "SSRR"}, /* Battery Protection Release Time , */\
{ 0x5b1, "SSHY"}, /* Battery Protection Hysteresis , */\
{ 0x5e0, "SSR"}, /* battery voltage for I2C read out only , */\
{ 0x5f0, "SSBY"}, /* bypass clipper battery protection , */\
{ 0x600, "DPSA"}, /* Enable dynamic powerstage activation , */\
{ 0x650, "CFSM"}, /* Soft mute in CoolFlux , */\
{ 0x670, "SSS"}, /* BatSenseSteepness , */\
{ 0x687, "VOL"}, /* volume control (in CoolFlux) , */\
{ 0x702, "DCVO"}, /* Boost Voltage , */\
{ 0x733, "DCMCC"}, /* Max boost coil current - step of 175 mA , */\
{ 0x7a0, "DCIE"}, /* Adaptive boost mode , */\
{ 0x7b0, "DCSR"}, /* Soft RampUp/Down mode for DCDC controller , */\
{ 0x7c0, "DCPAVG"}, /* ctrl_peak2avg for analog part of DCDC , */\
{ 0x800, "TROS"}, /* Select external temperature also the ext_temp will be put on the temp read out , */\
{ 0x818, "EXTTS"}, /* external temperature setting to be given by host , */\
{ 0x900, "PWDN"}, /* Device Mode , */\
{ 0x910, "I2CR"}, /* I2C Reset , */\
{ 0x920, "CFE"}, /* Enable CoolFlux , */\
{ 0x930, "AMPE"}, /* Enable Amplifier , */\
{ 0x940, "DCA"}, /* EnableBoost , */\
{ 0x950, "SBSL"}, /* Coolflux configured , */\
{ 0x960, "AMPC"}, /* Selection on how Amplifier is enabled , */\
{ 0x970, "DCDIS"}, /* DCDC not connected , */\
{ 0x980, "PSDR"}, /* IDDQ test amplifier , */\
{ 0x991, "DCCV"}, /* Coil Value , */\
{ 0x9b0, "CCFD"}, /* Selection CoolFlux Clock , */\
{ 0x9c1, "INTPAD"}, /* INT pad configuration control , */\
{ 0x9e0, "IPLL"}, /* PLL input reference clock selection , */\
{ 0xb07, "MTPK"}, /* 5Ah, 90d To access KEY1_Protected registers (Default for engineering), */\
{ 0xc25, "CVFDLY"}, /* Fractional delay adjustment between current and voltage sense, */\
{ 0x1011, "TDMPRF"}, /* TDM_usecase , */\
{ 0x1030, "TDMEN"}, /* TDM interface control , */\
{ 0x1040, "TDMCKINV"}, /* TDM clock inversion , */\
{ 0x1053, "TDMFSLN"}, /* TDM FS length , */\
{ 0x1090, "TDMFSPOL"}, /* TDM FS polarity , */\
{ 0x10a4, "TDMSAMSZ"}, /* TDM Sample Size for all tdm sinks/sources , */\
{ 0x1103, "TDMSLOTS"}, /* Number of slots , */\
{ 0x1144, "TDMSLLN"}, /* Slot length , */\
{ 0x1194, "TDMBRMG"}, /* Bits remaining , */\
{ 0x11e0, "TDMDDEL"}, /* Data delay , */\
{ 0x11f0, "TDMDADJ"}, /* Data adjustment , */\
{ 0x1201, "TDMTXFRM"}, /* TXDATA format , */\
{ 0x1221, "TDMUUS0"}, /* TXDATA format unused slot sd0 , */\
{ 0x1241, "TDMUUS1"}, /* TXDATA format unused slot sd1 , */\
{ 0x1270, "TDMSI0EN"}, /* TDM sink0 enable , */\
{ 0x1280, "TDMSI1EN"}, /* TDM sink1 enable , */\
{ 0x1290, "TDMSI2EN"}, /* TDM sink2 enable , */\
{ 0x12a0, "TDMSO0EN"}, /* TDM source0 enable , */\
{ 0x12b0, "TDMSO1EN"}, /* TDM source1 enable , */\
{ 0x12c0, "TDMSO2EN"}, /* TDM source2 enable , */\
{ 0x12d0, "TDMSI0IO"}, /* tdm_sink0_io , */\
{ 0x12e0, "TDMSI1IO"}, /* tdm_sink1_io , */\
{ 0x12f0, "TDMSI2IO"}, /* tdm_sink2_io , */\
{ 0x1300, "TDMSO0IO"}, /* tdm_source0_io , */\
{ 0x1310, "TDMSO1IO"}, /* tdm_source1_io , */\
{ 0x1320, "TDMSO2IO"}, /* tdm_source2_io , */\
{ 0x1333, "TDMSI0SL"}, /* sink0_slot [GAIN IN] , */\
{ 0x1373, "TDMSI1SL"}, /* sink1_slot [CH1 IN] , */\
{ 0x13b3, "TDMSI2SL"}, /* sink2_slot [CH2 IN] , */\
{ 0x1403, "TDMSO0SL"}, /* source0_slot [GAIN OUT] , */\
{ 0x1443, "TDMSO1SL"}, /* source1_slot [Voltage Sense] , */\
{ 0x1483, "TDMSO2SL"}, /* source2_slot [Current Sense] , */\
{ 0x14c3, "NBCK"}, /* NBCK , */\
{ 0x2000, "INTOVDDS"}, /* flag_por_int_out , */\
{ 0x2010, "INTOPLLS"}, /* flag_pll_lock_int_out , */\
{ 0x2020, "INTOOTDS"}, /* flag_otpok_int_out , */\
{ 0x2030, "INTOOVDS"}, /* flag_ovpok_int_out , */\
{ 0x2040, "INTOUVDS"}, /* flag_uvpok_int_out , */\
{ 0x2050, "INTOOCDS"}, /* flag_ocp_alarm_int_out , */\
{ 0x2060, "INTOCLKS"}, /* flag_clocks_stable_int_out , */\
{ 0x2070, "INTOCLIPS"}, /* flag_clip_int_out , */\
{ 0x2080, "INTOMTPB"}, /* mtp_busy_int_out , */\
{ 0x2090, "INTONOCLK"}, /* flag_lost_clk_int_out , */\
{ 0x20a0, "INTOSPKS"}, /* flag_cf_speakererror_int_out , */\
{ 0x20b0, "INTOACS"}, /* flag_cold_started_int_out , */\
{ 0x20c0, "INTOSWS"}, /* flag_engage_int_out , */\
{ 0x20d0, "INTOWDS"}, /* flag_watchdog_reset_int_out , */\
{ 0x20e0, "INTOAMPS"}, /* flag_enbl_amp_int_out , */\
{ 0x20f0, "INTOAREFS"}, /* flag_enbl_ref_int_out , */\
{ 0x2201, "INTOACK"}, /* Interrupt status register output - Corresponding flag, */\
{ 0x2300, "INTIVDDS"}, /* flag_por_int_in , */\
{ 0x2310, "INTIPLLS"}, /* flag_pll_lock_int_in , */\
{ 0x2320, "INTIOTDS"}, /* flag_otpok_int_in , */\
{ 0x2330, "INTIOVDS"}, /* flag_ovpok_int_in , */\
{ 0x2340, "INTIUVDS"}, /* flag_uvpok_int_in , */\
{ 0x2350, "INTIOCDS"}, /* flag_ocp_alarm_int_in , */\
{ 0x2360, "INTICLKS"}, /* flag_clocks_stable_int_in , */\
{ 0x2370, "INTICLIPS"}, /* flag_clip_int_in , */\
{ 0x2380, "INTIMTPB"}, /* mtp_busy_int_in , */\
{ 0x2390, "INTINOCLK"}, /* flag_lost_clk_int_in , */\
{ 0x23a0, "INTISPKS"}, /* flag_cf_speakererror_int_in , */\
{ 0x23b0, "INTIACS"}, /* flag_cold_started_int_in , */\
{ 0x23c0, "INTISWS"}, /* flag_engage_int_in , */\
{ 0x23d0, "INTIWDS"}, /* flag_watchdog_reset_int_in , */\
{ 0x23e0, "INTIAMPS"}, /* flag_enbl_amp_int_in , */\
{ 0x23f0, "INTIAREFS"}, /* flag_enbl_ref_int_in , */\
{ 0x2501, "INTIACK"}, /* Interrupt register input , */\
{ 0x2600, "INTENVDDS"}, /* flag_por_int_enable , */\
{ 0x2610, "INTENPLLS"}, /* flag_pll_lock_int_enable , */\
{ 0x2620, "INTENOTDS"}, /* flag_otpok_int_enable , */\
{ 0x2630, "INTENOVDS"}, /* flag_ovpok_int_enable , */\
{ 0x2640, "INTENUVDS"}, /* flag_uvpok_int_enable , */\
{ 0x2650, "INTENOCDS"}, /* flag_ocp_alarm_int_enable , */\
{ 0x2660, "INTENCLKS"}, /* flag_clocks_stable_int_enable , */\
{ 0x2670, "INTENCLIPS"}, /* flag_clip_int_enable , */\
{ 0x2680, "INTENMTPB"}, /* mtp_busy_int_enable , */\
{ 0x2690, "INTENNOCLK"}, /* flag_lost_clk_int_enable , */\
{ 0x26a0, "INTENSPKS"}, /* flag_cf_speakererror_int_enable , */\
{ 0x26b0, "INTENACS"}, /* flag_cold_started_int_enable , */\
{ 0x26c0, "INTENSWS"}, /* flag_engage_int_enable , */\
{ 0x26d0, "INTENWDS"}, /* flag_watchdog_reset_int_enable , */\
{ 0x26e0, "INTENAMPS"}, /* flag_enbl_amp_int_enable , */\
{ 0x26f0, "INTENAREFS"}, /* flag_enbl_ref_int_enable , */\
{ 0x2801, "INTENACK"}, /* Interrupt enable register , */\
{ 0x2900, "INTPOLVDDS"}, /* flag_por_int_pol , */\
{ 0x2910, "INTPOLPLLS"}, /* flag_pll_lock_int_pol , */\
{ 0x2920, "INTPOLOTDS"}, /* flag_otpok_int_pol , */\
{ 0x2930, "INTPOLOVDS"}, /* flag_ovpok_int_pol , */\
{ 0x2940, "INTPOLUVDS"}, /* flag_uvpok_int_pol , */\
{ 0x2950, "INTPOLOCDS"}, /* flag_ocp_alarm_int_pol , */\
{ 0x2960, "INTPOLCLKS"}, /* flag_clocks_stable_int_pol , */\
{ 0x2970, "INTPOLCLIPS"}, /* flag_clip_int_pol , */\
{ 0x2980, "INTPOLMTPB"}, /* mtp_busy_int_pol , */\
{ 0x2990, "INTPOLNOCLK"}, /* flag_lost_clk_int_pol , */\
{ 0x29a0, "INTPOLSPKS"}, /* flag_cf_speakererror_int_pol , */\
{ 0x29b0, "INTPOLACS"}, /* flag_cold_started_int_pol , */\
{ 0x29c0, "INTPOLSWS"}, /* flag_engage_int_pol , */\
{ 0x29d0, "INTPOLWDS"}, /* flag_watchdog_reset_int_pol , */\
{ 0x29e0, "INTPOLAMPS"}, /* flag_enbl_amp_int_pol , */\
{ 0x29f0, "INTPOLAREFS"}, /* flag_enbl_ref_int_pol , */\
{ 0x2b01, "INTPOLACK"}, /* Interrupt status flags polarity register , */\
{ 0x4900, "CLIP"}, /* Bypass clip control , */\
{ 0x62b0, "CIMTP"}, /* start copying all the data from i2cregs_mtp to mtp [Key 2 protected], */\
{ 0x7000, "RST"}, /* Reset CoolFlux DSP , */\
{ 0x7011, "DMEM"}, /* Target memory for access , */\
{ 0x7030, "AIF"}, /* Autoincrement-flag for memory-address , */\
{ 0x7040, "CFINT"}, /* Interrupt CoolFlux DSP , */\
{ 0x7087, "REQ"}, /* request for access (8 channels) , */\
{ 0x7080, "REQCMD"}, /* Firmware event request rpc command , */\
{ 0x7090, "REQRST"}, /* Firmware event request reset restart , */\
{ 0x70a0, "REQMIPS"}, /* Firmware event request short on mips , */\
{ 0x70b0, "REQMUTED"}, /* Firmware event request mute sequence ready , */\
{ 0x70c0, "REQVOL"}, /* Firmware event request volume ready , */\
{ 0x70d0, "REQDMG"}, /* Firmware event request speaker damage detected , */\
{ 0x70e0, "REQCAL"}, /* Firmware event request calibration completed , */\
{ 0x70f0, "REQRSV"}, /* Firmware event request reserved , */\
{ 0x710f, "MADD"}, /* memory-address to be accessed , */\
{ 0x720f, "MEMA"}, /* activate memory access (24- or 32-bits data is written/read to/from memory, */\
{ 0x7307, "ERR"}, /* Coolflux error flags , */\
{ 0x7387, "ACK"}, /* acknowledge of requests (8 channels) , */\
{ 0x7380, "ACKCMD"}, /* Firmware event acknowledge rpc command , */\
{ 0x7390, "ACKRST"}, /* Firmware event acknowledge reset restart , */\
{ 0x73a0, "ACKMIPS"}, /* Firmware event acknowledge short on mips , */\
{ 0x73b0, "ACKMUTED"}, /* Firmware event acknowledge mute sequence ready , */\
{ 0x73c0, "ACKVOL"}, /* Firmware event acknowledge volume ready , */\
{ 0x73d0, "ACKDMG"}, /* Firmware event acknowledge speaker damage detected, */\
{ 0x73e0, "ACKCAL"}, /* Firmware event acknowledge calibration completed , */\
{ 0x73f0, "ACKRSV"}, /* Firmware event acknowledge reserved , */\
{ 0x8000, "MTPOTC"}, /* Calibration schedule (key2 protected) , */\
{ 0x8010, "MTPEX"}, /* (key2 protected) , */\
{ 0x8045, "SWPROFIL" },\
{ 0x80a5, "SWVSTEP" },\
{ 0xffff,"Unknown bitfield enum" } /* not found */\
};
#define TFA1_BITNAMETABLE static tfaBfName_t Tfa1BitNames[]= {\
{ 0x0, "flag_por"}, /* Power-on-reset flag , */\
{ 0x10, "flag_pll_lock"}, /* PLL lock , */\
{ 0x20, "flag_otpok"}, /* Over Temperature Protection alarm , */\
{ 0x30, "flag_ovpok"}, /* Over Voltage Protection alarm , */\
{ 0x40, "flag_uvpok"}, /* Under Voltage Protection alarm , */\
{ 0x50, "flag_ocp_alarm"}, /* Over Current Protection alarm , */\
{ 0x60, "flag_clocks_stable"}, /* Clocks stable flag , */\
{ 0x70, "flag_clip"}, /* Amplifier clipping , */\
{ 0x80, "mtp_busy"}, /* MTP busy , */\
{ 0x90, "flag_lost_clk"}, /* Flag lost clock from clock generation unit , */\
{ 0xa0, "flag_cf_speakererror"}, /* Speaker error flag , */\
{ 0xb0, "flag_cold_started"}, /* Cold Start flag , */\
{ 0xc0, "flag_engage"}, /* Flag Engage , */\
{ 0xd0, "flag_watchdog_reset"}, /* Flag watchdog reset , */\
{ 0xe0, "flag_enbl_amp"}, /* Amplifier is enabled by manager , */\
{ 0xf0, "flag_enbl_ref"}, /* References are enabled by manager , */\
{ 0x109, "bat_adc"}, /* Battery voltage readout; 0 .. 5.5 [V] , */\
{ 0x208, "temp_adc"}, /* Temperature readout from the temperature sensor , */\
{ 0x30b, "rev_reg"}, /* Device type number is B97 , */\
{ 0x420, "ctrl_rcv"}, /* Enable Receiver Mode , */\
{ 0x431, "chan_sel"}, /* Channel Selection TDM input for Coolflux , */\
{ 0x450, "input_level"}, /* Input level selection control , */\
{ 0x461, "vamp_sel"}, /* Input selection for amplifier , */\
{ 0x4c3, "audio_fs"}, /* Audio sample rate setting , */\
{ 0x501, "vbat_prot_attacktime"}, /* Protection Attack Time , */\
{ 0x523, "vbat_prot_thlevel"}, /* ProtectionThreshold , */\
{ 0x561, "vbat_prot_max_reduct"}, /* Protection Maximum Reduction , */\
{ 0x582, "vbat_prot_release_t"}, /* Battery Protection Release Time , */\
{ 0x5b1, "vbat_prot_hysterese"}, /* Battery Protection Hysteresis , */\
{ 0x5d0, "reset_min_vbat"}, /* reset clipper , */\
{ 0x5e0, "sel_vbat"}, /* battery voltage for I2C read out only , */\
{ 0x5f0, "bypass_clipper"}, /* bypass clipper battery protection , */\
{ 0x600, "dpsa"}, /* Enable dynamic powerstage activation , */\
{ 0x650, "cf_mute"}, /* Soft mute in CoolFlux , */\
{ 0x670, "batsense_steepness"}, /* BatSenseSteepness , */\
{ 0x687, "vol"}, /* volume control (in CoolFlux) , */\
{ 0x702, "boost_volt"}, /* Boost Voltage , */\
{ 0x733, "boost_cur"}, /* Max boost coil current - step of 175 mA , */\
{ 0x7a0, "boost_intel"}, /* Adaptive boost mode , */\
{ 0x7b0, "boost_speed"}, /* Soft RampUp/Down mode for DCDC controller , */\
{ 0x7c0, "boost_peak2avg"}, /* ctrl_peak2avg for analog part of DCDC , */\
{ 0x800, "ext_temp_sel"}, /* Select external temperature also the ext_temp will be put on the temp read out , */\
{ 0x818, "ext_temp"}, /* external temperature setting to be given by host , */\
{ 0x8b2, "dcdc_synchronisation"}, /* DCDC synchronisation off + 7 positions , */\
{ 0x900, "powerdown"}, /* Device Mode , */\
{ 0x910, "reset"}, /* I2C Reset , */\
{ 0x920, "enbl_coolflux"}, /* Enable CoolFlux , */\
{ 0x930, "enbl_amplifier"}, /* Enable Amplifier , */\
{ 0x940, "enbl_boost"}, /* EnableBoost , */\
{ 0x950, "coolflux_configured"}, /* Coolflux configured , */\
{ 0x960, "sel_enbl_amplifier"}, /* Selection on how Amplifier is enabled , */\
{ 0x970, "dcdcoff_mode"}, /* DCDC not connected , */\
{ 0x980, "iddqtest"}, /* IDDQ test amplifier , */\
{ 0x991, "coil_value"}, /* Coil Value , */\
{ 0x9b0, "sel_cf_clock"}, /* Selection CoolFlux Clock , */\
{ 0x9c1, "int_pad_io"}, /* INT pad configuration control , */\
{ 0x9e0, "sel_fs_bck"}, /* PLL input reference clock selection , */\
{ 0x9f0, "sel_scl_cf_clock"}, /* Coolflux sub-system clock , */\
{ 0xb07, "mtpkey2"}, /* 5Ah, 90d To access KEY1_Protected registers (Default for engineering), */\
{ 0xc00, "enbl_volt_sense"}, /* Voltage sense enabling control bit , */\
{ 0xc10, "vsense_pwm_sel"}, /* Voltage sense PWM source selection control , */\
{ 0xc25, "vi_frac_delay"}, /* Fractional delay adjustment between current and voltage sense, */\
{ 0xc80, "sel_voltsense_out"}, /* TDM output data selection control , */\
{ 0xc90, "vsense_bypass_avg"}, /* Voltage Sense Average Block Bypass , */\
{ 0xd05, "cf_frac_delay"}, /* Fractional delay adjustment between current and voltage sense by firmware, */\
{ 0xe00, "bypass_dcdc_curr_prot"}, /* Control to switch off dcdc current reduction with bat protection, */\
{ 0xe80, "disable_clock_sh_prot"}, /* disable clock_sh protection , */\
{ 0xe96, "reserve_reg_1_15_9"}, /* , */\
{ 0x1011, "tdm_usecase"}, /* TDM_usecase , */\
{ 0x1030, "tdm_enable"}, /* TDM interface control , */\
{ 0x1040, "tdm_clk_inversion"}, /* TDM clock inversion , */\
{ 0x1053, "tdm_fs_ws_length"}, /* TDM FS length , */\
{ 0x1090, "tdm_fs_ws_polarity"}, /* TDM FS polarity , */\
{ 0x10a4, "tdm_sample_size"}, /* TDM Sample Size for all tdm sinks/sources , */\
{ 0x1103, "tdm_nb_of_slots"}, /* Number of slots , */\
{ 0x1144, "tdm_slot_length"}, /* Slot length , */\
{ 0x1194, "tdm_bits_remaining"}, /* Bits remaining , */\
{ 0x11e0, "tdm_data_delay"}, /* Data delay , */\
{ 0x11f0, "tdm_data_adjustment"}, /* Data adjustment , */\
{ 0x1201, "tdm_txdata_format"}, /* TXDATA format , */\
{ 0x1221, "tdm_txdata_format_unused_slot_sd0"}, /* TXDATA format unused slot sd0 , */\
{ 0x1241, "tdm_txdata_format_unused_slot_sd1"}, /* TXDATA format unused slot sd1 , */\
{ 0x1270, "tdm_sink0_enable"}, /* TDM sink0 enable , */\
{ 0x1280, "tdm_sink1_enable"}, /* TDM sink1 enable , */\
{ 0x1290, "tdm_sink2_enable"}, /* TDM sink2 enable , */\
{ 0x12a0, "tdm_source0_enable"}, /* TDM source0 enable , */\
{ 0x12b0, "tdm_source1_enable"}, /* TDM source1 enable , */\
{ 0x12c0, "tdm_source2_enable"}, /* TDM source2 enable , */\
{ 0x12d0, "tdm_sink0_io"}, /* tdm_sink0_io , */\
{ 0x12e0, "tdm_sink1_io"}, /* tdm_sink1_io , */\
{ 0x12f0, "tdm_sink2_io"}, /* tdm_sink2_io , */\
{ 0x1300, "tdm_source0_io"}, /* tdm_source0_io , */\
{ 0x1310, "tdm_source1_io"}, /* tdm_source1_io , */\
{ 0x1320, "tdm_source2_io"}, /* tdm_source2_io , */\
{ 0x1333, "tdm_sink0_slot"}, /* sink0_slot [GAIN IN] , */\
{ 0x1373, "tdm_sink1_slot"}, /* sink1_slot [CH1 IN] , */\
{ 0x13b3, "tdm_sink2_slot"}, /* sink2_slot [CH2 IN] , */\
{ 0x1403, "tdm_source0_slot"}, /* source0_slot [GAIN OUT] , */\
{ 0x1443, "tdm_source1_slot"}, /* source1_slot [Voltage Sense] , */\
{ 0x1483, "tdm_source2_slot"}, /* source2_slot [Current Sense] , */\
{ 0x14c3, "tdm_nbck"}, /* NBCK , */\
{ 0x1500, "flag_tdm_lut_error"}, /* TDM LUT error flag , */\
{ 0x1512, "flag_tdm_status"}, /* TDM interface status bits , */\
{ 0x1540, "flag_tdm_error"}, /* TDM interface error indicator , */\
{ 0x2000, "flag_por_int_out"}, /* flag_por_int_out , */\
{ 0x2010, "flag_pll_lock_int_out"}, /* flag_pll_lock_int_out , */\
{ 0x2020, "flag_otpok_int_out"}, /* flag_otpok_int_out , */\
{ 0x2030, "flag_ovpok_int_out"}, /* flag_ovpok_int_out , */\
{ 0x2040, "flag_uvpok_int_out"}, /* flag_uvpok_int_out , */\
{ 0x2050, "flag_ocp_alarm_int_out"}, /* flag_ocp_alarm_int_out , */\
{ 0x2060, "flag_clocks_stable_int_out"}, /* flag_clocks_stable_int_out , */\
{ 0x2070, "flag_clip_int_out"}, /* flag_clip_int_out , */\
{ 0x2080, "mtp_busy_int_out"}, /* mtp_busy_int_out , */\
{ 0x2090, "flag_lost_clk_int_out"}, /* flag_lost_clk_int_out , */\
{ 0x20a0, "flag_cf_speakererror_int_out"}, /* flag_cf_speakererror_int_out , */\
{ 0x20b0, "flag_cold_started_int_out"}, /* flag_cold_started_int_out , */\
{ 0x20c0, "flag_engage_int_out"}, /* flag_engage_int_out , */\
{ 0x20d0, "flag_watchdog_reset_int_out"}, /* flag_watchdog_reset_int_out , */\
{ 0x20e0, "flag_enbl_amp_int_out"}, /* flag_enbl_amp_int_out , */\
{ 0x20f0, "flag_enbl_ref_int_out"}, /* flag_enbl_ref_int_out , */\
{ 0x2100, "flag_voutcomp_int_out"}, /* flag_voutcomp_int_out , */\
{ 0x2110, "flag_voutcomp93_int_out"}, /* flag_voutcomp93_int_out , */\
{ 0x2120, "flag_voutcomp86_int_out"}, /* flag_voutcomp86_int_out , */\
{ 0x2130, "flag_hiz_int_out"}, /* flag_hiz_int_out , */\
{ 0x2140, "flag_ocpokbst_int_out"}, /* flag_ocpokbst_int_out , */\
{ 0x2150, "flag_peakcur_int_out"}, /* flag_peakcur_int_out , */\
{ 0x2160, "flag_ocpokap_int_out"}, /* flag_ocpokap_int_out , */\
{ 0x2170, "flag_ocpokan_int_out"}, /* flag_ocpokan_int_out , */\
{ 0x2180, "flag_ocpokbp_int_out"}, /* flag_ocpokbp_int_out , */\
{ 0x2190, "flag_ocpokbn_int_out"}, /* flag_ocpokbn_int_out , */\
{ 0x21a0, "flag_adc10_ready_int_out"}, /* flag_adc10_ready_int_out , */\
{ 0x21b0, "flag_clipa_high_int_out"}, /* flag_clipa_high_int_out , */\
{ 0x21c0, "flag_clipa_low_int_out"}, /* flag_clipa_low_int_out , */\
{ 0x21d0, "flag_clipb_high_int_out"}, /* flag_clipb_high_int_out , */\
{ 0x21e0, "flag_clipb_low_int_out"}, /* flag_clipb_low_int_out , */\
{ 0x21f0, "flag_tdm_error_int_out"}, /* flag_tdm_error_int_out , */\
{ 0x2201, "interrupt_out3"}, /* Interrupt status register output - Corresponding flag, */\
{ 0x2300, "flag_por_int_in"}, /* flag_por_int_in , */\
{ 0x2310, "flag_pll_lock_int_in"}, /* flag_pll_lock_int_in , */\
{ 0x2320, "flag_otpok_int_in"}, /* flag_otpok_int_in , */\
{ 0x2330, "flag_ovpok_int_in"}, /* flag_ovpok_int_in , */\
{ 0x2340, "flag_uvpok_int_in"}, /* flag_uvpok_int_in , */\
{ 0x2350, "flag_ocp_alarm_int_in"}, /* flag_ocp_alarm_int_in , */\
{ 0x2360, "flag_clocks_stable_int_in"}, /* flag_clocks_stable_int_in , */\
{ 0x2370, "flag_clip_int_in"}, /* flag_clip_int_in , */\
{ 0x2380, "mtp_busy_int_in"}, /* mtp_busy_int_in , */\
{ 0x2390, "flag_lost_clk_int_in"}, /* flag_lost_clk_int_in , */\
{ 0x23a0, "flag_cf_speakererror_int_in"}, /* flag_cf_speakererror_int_in , */\
{ 0x23b0, "flag_cold_started_int_in"}, /* flag_cold_started_int_in , */\
{ 0x23c0, "flag_engage_int_in"}, /* flag_engage_int_in , */\
{ 0x23d0, "flag_watchdog_reset_int_in"}, /* flag_watchdog_reset_int_in , */\
{ 0x23e0, "flag_enbl_amp_int_in"}, /* flag_enbl_amp_int_in , */\
{ 0x23f0, "flag_enbl_ref_int_in"}, /* flag_enbl_ref_int_in , */\
{ 0x2400, "flag_voutcomp_int_in"}, /* flag_voutcomp_int_in , */\
{ 0x2410, "flag_voutcomp93_int_in"}, /* flag_voutcomp93_int_in , */\
{ 0x2420, "flag_voutcomp86_int_in"}, /* flag_voutcomp86_int_in , */\
{ 0x2430, "flag_hiz_int_in"}, /* flag_hiz_int_in , */\
{ 0x2440, "flag_ocpokbst_int_in"}, /* flag_ocpokbst_int_in , */\
{ 0x2450, "flag_peakcur_int_in"}, /* flag_peakcur_int_in , */\
{ 0x2460, "flag_ocpokap_int_in"}, /* flag_ocpokap_int_in , */\
{ 0x2470, "flag_ocpokan_int_in"}, /* flag_ocpokan_int_in , */\
{ 0x2480, "flag_ocpokbp_int_in"}, /* flag_ocpokbp_int_in , */\
{ 0x2490, "flag_ocpokbn_int_in"}, /* flag_ocpokbn_int_in , */\
{ 0x24a0, "flag_adc10_ready_int_in"}, /* flag_adc10_ready_int_in , */\
{ 0x24b0, "flag_clipa_high_int_in"}, /* flag_clipa_high_int_in , */\
{ 0x24c0, "flag_clipa_low_int_in"}, /* flag_clipa_low_int_in , */\
{ 0x24d0, "flag_clipb_high_int_in"}, /* flag_clipb_high_int_in , */\
{ 0x24e0, "flag_clipb_low_int_in"}, /* flag_clipb_low_int_in , */\
{ 0x24f0, "flag_tdm_error_int_in"}, /* flag_tdm_error_int_in , */\
{ 0x2501, "interrupt_in3"}, /* Interrupt register input , */\
{ 0x2600, "flag_por_int_enable"}, /* flag_por_int_enable , */\
{ 0x2610, "flag_pll_lock_int_enable"}, /* flag_pll_lock_int_enable , */\
{ 0x2620, "flag_otpok_int_enable"}, /* flag_otpok_int_enable , */\
{ 0x2630, "flag_ovpok_int_enable"}, /* flag_ovpok_int_enable , */\
{ 0x2640, "flag_uvpok_int_enable"}, /* flag_uvpok_int_enable , */\
{ 0x2650, "flag_ocp_alarm_int_enable"}, /* flag_ocp_alarm_int_enable , */\
{ 0x2660, "flag_clocks_stable_int_enable"}, /* flag_clocks_stable_int_enable , */\
{ 0x2670, "flag_clip_int_enable"}, /* flag_clip_int_enable , */\
{ 0x2680, "mtp_busy_int_enable"}, /* mtp_busy_int_enable , */\
{ 0x2690, "flag_lost_clk_int_enable"}, /* flag_lost_clk_int_enable , */\
{ 0x26a0, "flag_cf_speakererror_int_enable"}, /* flag_cf_speakererror_int_enable , */\
{ 0x26b0, "flag_cold_started_int_enable"}, /* flag_cold_started_int_enable , */\
{ 0x26c0, "flag_engage_int_enable"}, /* flag_engage_int_enable , */\
{ 0x26d0, "flag_watchdog_reset_int_enable"}, /* flag_watchdog_reset_int_enable , */\
{ 0x26e0, "flag_enbl_amp_int_enable"}, /* flag_enbl_amp_int_enable , */\
{ 0x26f0, "flag_enbl_ref_int_enable"}, /* flag_enbl_ref_int_enable , */\
{ 0x2700, "flag_voutcomp_int_enable"}, /* flag_voutcomp_int_enable , */\
{ 0x2710, "flag_voutcomp93_int_enable"}, /* flag_voutcomp93_int_enable , */\
{ 0x2720, "flag_voutcomp86_int_enable"}, /* flag_voutcomp86_int_enable , */\
{ 0x2730, "flag_hiz_int_enable"}, /* flag_hiz_int_enable , */\
{ 0x2740, "flag_ocpokbst_int_enable"}, /* flag_ocpokbst_int_enable , */\
{ 0x2750, "flag_peakcur_int_enable"}, /* flag_peakcur_int_enable , */\
{ 0x2760, "flag_ocpokap_int_enable"}, /* flag_ocpokap_int_enable , */\
{ 0x2770, "flag_ocpokan_int_enable"}, /* flag_ocpokan_int_enable , */\
{ 0x2780, "flag_ocpokbp_int_enable"}, /* flag_ocpokbp_int_enable , */\
{ 0x2790, "flag_ocpokbn_int_enable"}, /* flag_ocpokbn_int_enable , */\
{ 0x27a0, "flag_adc10_ready_int_enable"}, /* flag_adc10_ready_int_enable , */\
{ 0x27b0, "flag_clipa_high_int_enable"}, /* flag_clipa_high_int_enable , */\
{ 0x27c0, "flag_clipa_low_int_enable"}, /* flag_clipa_low_int_enable , */\
{ 0x27d0, "flag_clipb_high_int_enable"}, /* flag_clipb_high_int_enable , */\
{ 0x27e0, "flag_clipb_low_int_enable"}, /* flag_clipb_low_int_enable , */\
{ 0x27f0, "flag_tdm_error_int_enable"}, /* flag_tdm_error_int_enable , */\
{ 0x2801, "interrupt_enable3"}, /* Interrupt enable register , */\
{ 0x2900, "flag_por_int_pol"}, /* flag_por_int_pol , */\
{ 0x2910, "flag_pll_lock_int_pol"}, /* flag_pll_lock_int_pol , */\
{ 0x2920, "flag_otpok_int_pol"}, /* flag_otpok_int_pol , */\
{ 0x2930, "flag_ovpok_int_pol"}, /* flag_ovpok_int_pol , */\
{ 0x2940, "flag_uvpok_int_pol"}, /* flag_uvpok_int_pol , */\
{ 0x2950, "flag_ocp_alarm_int_pol"}, /* flag_ocp_alarm_int_pol , */\
{ 0x2960, "flag_clocks_stable_int_pol"}, /* flag_clocks_stable_int_pol , */\
{ 0x2970, "flag_clip_int_pol"}, /* flag_clip_int_pol , */\
{ 0x2980, "mtp_busy_int_pol"}, /* mtp_busy_int_pol , */\
{ 0x2990, "flag_lost_clk_int_pol"}, /* flag_lost_clk_int_pol , */\
{ 0x29a0, "flag_cf_speakererror_int_pol"}, /* flag_cf_speakererror_int_pol , */\
{ 0x29b0, "flag_cold_started_int_pol"}, /* flag_cold_started_int_pol , */\
{ 0x29c0, "flag_engage_int_pol"}, /* flag_engage_int_pol , */\
{ 0x29d0, "flag_watchdog_reset_int_pol"}, /* flag_watchdog_reset_int_pol , */\
{ 0x29e0, "flag_enbl_amp_int_pol"}, /* flag_enbl_amp_int_pol , */\
{ 0x29f0, "flag_enbl_ref_int_pol"}, /* flag_enbl_ref_int_pol , */\
{ 0x2a00, "flag_voutcomp_int_pol"}, /* flag_voutcomp_int_pol , */\
{ 0x2a10, "flag_voutcomp93_int_pol"}, /* flag_voutcomp93_int_pol , */\
{ 0x2a20, "flag_voutcomp86_int_pol"}, /* flag_voutcomp86_int_pol , */\
{ 0x2a30, "flag_hiz_int_pol"}, /* flag_hiz_int_pol , */\
{ 0x2a40, "flag_ocpokbst_int_pol"}, /* flag_ocpokbst_int_pol , */\
{ 0x2a50, "flag_peakcur_int_pol"}, /* flag_peakcur_int_pol , */\
{ 0x2a60, "flag_ocpokap_int_pol"}, /* flag_ocpokap_int_pol , */\
{ 0x2a70, "flag_ocpokan_int_pol"}, /* flag_ocpokan_int_pol , */\
{ 0x2a80, "flag_ocpokbp_int_pol"}, /* flag_ocpokbp_int_pol , */\
{ 0x2a90, "flag_ocpokbn_int_pol"}, /* flag_ocpokbn_int_pol , */\
{ 0x2aa0, "flag_adc10_ready_int_pol"}, /* flag_adc10_ready_int_pol , */\
{ 0x2ab0, "flag_clipa_high_int_pol"}, /* flag_clipa_high_int_pol , */\
{ 0x2ac0, "flag_clipa_low_int_pol"}, /* flag_clipa_low_int_pol , */\
{ 0x2ad0, "flag_clipb_high_int_pol"}, /* flag_clipb_high_int_pol , */\
{ 0x2ae0, "flag_clipb_low_int_pol"}, /* flag_clipb_low_int_pol , */\
{ 0x2af0, "flag_tdm_error_int_pol"}, /* flag_tdm_error_int_pol , */\
{ 0x2b01, "status_polarity3"}, /* Interrupt status flags polarity register , */\
{ 0x3000, "flag_voutcomp"}, /* flag_voutcomp, indication Vset is larger than Vbat, */\
{ 0x3010, "flag_voutcomp93"}, /* flag_voutcomp93, indication Vset is larger than 1.07* Vbat, */\
{ 0x3020, "flag_voutcomp86"}, /* flag_voutcomp86, indication Vset is larger than 1.14* Vbat, */\
{ 0x3030, "flag_hiz"}, /* flag_hiz, indication Vbst is larger than Vbat , */\
{ 0x3040, "flag_ocpokbst"}, /* flag_ocpokbst, indication no over current in boost converter pmos switch, */\
{ 0x3050, "flag_peakcur"}, /* flag_peakcur, indication current is max in dcdc converter, */\
{ 0x3060, "flag_ocpokap"}, /* flag_ocpokap, indication no over current in amplifier "a" pmos output stage, */\
{ 0x3070, "flag_ocpokan"}, /* flag_ocpokan, indication no over current in amplifier "a" nmos output stage, */\
{ 0x3080, "flag_ocpokbp"}, /* flag_ocpokbp, indication no over current in amplifier "b" pmos output stage, */\
{ 0x3090, "flag_ocpokbn"}, /* flag_ocpokbn, indication no over current in amplifier"b" nmos output stage, */\
{ 0x30a0, "flag_adc10_ready"}, /* flag_adc10_ready, indication adc10 is ready , */\
{ 0x30b0, "flag_clipa_high"}, /* flag_clipa_high, indication pmos amplifier "a" is clipping, */\
{ 0x30c0, "flag_clipa_low"}, /* flag_clipa_low, indication nmos amplifier "a" is clipping, */\
{ 0x30d0, "flag_clipb_high"}, /* flag_clipb_high, indication pmos amplifier "b" is clipping, */\
{ 0x30e0, "flag_clipb_low"}, /* flag_clipb_low, indication nmos amplifier "b" is clipping, */\
{ 0x310f, "mtp_man_data_out"}, /* single word read from MTP (manual copy) , */\
{ 0x3200, "key01_locked"}, /* key01_locked, indication key 1 is locked , */\
{ 0x3210, "key02_locked"}, /* key02_locked, indication key 2 is locked , */\
{ 0x3225, "mtp_ecc_tcout"}, /* mtp_ecc_tcout , */\
{ 0x3280, "mtpctrl_valid_test_rd"}, /* mtp test readout for read , */\
{ 0x3290, "mtpctrl_valid_test_wr"}, /* mtp test readout for write , */\
{ 0x32a0, "flag_in_alarm_state"}, /* Alarm state , */\
{ 0x32b0, "mtp_ecc_err2"}, /* two or more bit errors detected in MTP, can not reconstruct value, */\
{ 0x32c0, "mtp_ecc_err1"}, /* one bit error detected in MTP, reconstructed value, */\
{ 0x32d0, "mtp_mtp_hvf"}, /* high voltage ready flag for MTP , */\
{ 0x32f0, "mtp_zero_check_fail"}, /* zero check failed (tbd) for MTP , */\
{ 0x3309, "data_adc10_tempbat"}, /* data_adc10_tempbat[9;0], adc 10 data output for testing, */\
{ 0x400f, "hid_code"}, /* 5A6Bh, 23147d to access registers (Default for engineering), */\
{ 0x4100, "bypass_hp"}, /* Bypass_High Pass Filter , */\
{ 0x4110, "hard_mute"}, /* Hard Mute , */\
{ 0x4120, "soft_mute"}, /* Soft Mute , */\
{ 0x4134, "pwm_delay"}, /* PWM DelayBits to set the delay , */\
{ 0x4180, "pwm_shape"}, /* PWM Shape , */\
{ 0x4190, "pwm_bitlength"}, /* PWM Bitlength in noise shaper , */\
{ 0x4203, "drive"}, /* Drive bits to select amount of power stage amplifier, */\
{ 0x4240, "reclock_pwm"}, /* , */\
{ 0x4250, "reclock_voltsense"}, /* , */\
{ 0x4281, "dpsalevel"}, /* DPSA Threshold level , */\
{ 0x42a1, "dpsa_release"}, /* DPSA Release time , */\
{ 0x42c0, "coincidence"}, /* Prevent simultaneously switching of output stage , */\
{ 0x42d0, "kickback"}, /* Prevent double pulses of output stage , */\
{ 0x4306, "drivebst"}, /* Drive bits to select the powertransistor sections boost converter, */\
{ 0x43a0, "ocptestbst"}, /* Boost OCP. For old ocp (ctrl_reversebst is 0);For new ocp (ctrl_reversebst is 1);, */\
{ 0x43d0, "test_abistfft_enbl"}, /* FFT coolflux , */\
{ 0x43f0, "test_bcontrol"}, /* test _bcontrol , */\
{ 0x4400, "reversebst"}, /* OverCurrent Protection selection of power stage boost converter, */\
{ 0x4410, "sensetest"}, /* Test option for the sense NMOS in booster for current mode control., */\
{ 0x4420, "enbl_engagebst"}, /* Enable power stage dcdc controller , */\
{ 0x4470, "enbl_slopecur"}, /* Enable bit of max-current dac , */\
{ 0x4480, "enbl_voutcomp"}, /* Enable vout comparators , */\
{ 0x4490, "enbl_voutcomp93"}, /* Enable vout-93 comparators , */\
{ 0x44a0, "enbl_voutcomp86"}, /* Enable vout-86 comparators , */\
{ 0x44b0, "enbl_hizcom"}, /* Enable hiz comparator , */\
{ 0x44c0, "enbl_peakcur"}, /* Enable peak current , */\
{ 0x44d0, "bypass_ovpglitch"}, /* Bypass OVP Glitch Filter , */\
{ 0x44e0, "enbl_windac"}, /* Enable window dac , */\
{ 0x44f0, "enbl_powerbst"}, /* Enable line of the powerstage , */\
{ 0x4507, "ocp_thr"}, /* ocp_thr threshold level for OCP , */\
{ 0x4580, "bypass_glitchfilter"}, /* Bypass glitch filter , */\
{ 0x4590, "bypass_ovp"}, /* Bypass OVP , */\
{ 0x45a0, "bypass_uvp"}, /* Bypass UVP , */\
{ 0x45b0, "bypass_otp"}, /* Bypass OTP , */\
{ 0x45c0, "bypass_ocp"}, /* Bypass OCP , */\
{ 0x45d0, "bypass_ocpcounter"}, /* BypassOCPCounter , */\
{ 0x45e0, "bypass_lost_clk"}, /* Bypasslost_clk detector , */\
{ 0x45f0, "vpalarm"}, /* vpalarm (uvp ovp handling) , */\
{ 0x4600, "bypass_gc"}, /* bypass_gc, bypasses the CS gain correction , */\
{ 0x4610, "cs_gain_control"}, /* gain control by means of MTP or i2c; 0 is MTP , */\
{ 0x4627, "cs_gain"}, /* + / - 128 steps in steps of 1/4 percent 2's compliment, */\
{ 0x46a0, "bypass_lp"}, /* bypass Low-Pass filter in temperature sensor , */\
{ 0x46b0, "bypass_pwmcounter"}, /* bypass_pwmcounter , */\
{ 0x46c0, "cs_negfixed"}, /* does not switch to neg , */\
{ 0x46d2, "cs_neghyst"}, /* switches to neg depending on level , */\
{ 0x4700, "switch_fb"}, /* switch_fb , */\
{ 0x4713, "se_hyst"}, /* se_hyst , */\
{ 0x4754, "se_level"}, /* se_level , */\
{ 0x47a5, "ktemp"}, /* temperature compensation trimming , */\
{ 0x4800, "cs_negin"}, /* negin , */\
{ 0x4810, "cs_sein"}, /* cs_sein , */\
{ 0x4820, "cs_coincidence"}, /* Coincidence current sense , */\
{ 0x4830, "iddqtestbst"}, /* for iddq testing in powerstage of boost convertor , */\
{ 0x4840, "coincidencebst"}, /* Switch protection on to prevent simultaneously switching power stages bst and amp, */\
{ 0x4876, "delay_se_neg"}, /* delay of se and neg , */\
{ 0x48e1, "cs_ttrack"}, /* sample & hold track time , */\
{ 0x4900, "bypass_clip"}, /* Bypass clip control , */\
{ 0x4920, "cf_cgate_off"}, /* to disable clock gating in the coolflux , */\
{ 0x4940, "clipfast"}, /* clock switch for battery protection clipper, it switches back to old frequency, */\
{ 0x4950, "cs_8ohm"}, /* 8 ohm mode for current sense (gain mode) , */\
{ 0x4974, "delay_clock_sh"}, /* delay_sh, tunes S7H delay , */\
{ 0x49c0, "inv_clksh"}, /* Invert the sample/hold clock for current sense ADC, */\
{ 0x49d0, "inv_neg"}, /* Invert neg signal , */\
{ 0x49e0, "inv_se"}, /* Invert se signal , */\
{ 0x49f0, "setse"}, /* switches between Single Ende and differential mode; 1 is single ended, */\
{ 0x4a12, "adc10_sel"}, /* select the input to convert the 10b ADC , */\
{ 0x4a60, "adc10_reset"}, /* Global asynchronous reset (active HIGH) 10 bit ADC, */\
{ 0x4a81, "adc10_test"}, /* Test mode selection signal 10 bit ADC , */\
{ 0x4aa0, "bypass_lp_vbat"}, /* lp filter in batt sensor , */\
{ 0x4ae0, "dc_offset"}, /* switch offset control on/off, is decimator offset control, */\
{ 0x4af0, "tsense_hibias"}, /* bit to set the biasing in temp sensor to high , */\
{ 0x4b00, "adc13_iset"}, /* Micadc Setting of current consumption. Debug use only, */\
{ 0x4b14, "adc13_gain"}, /* Micadc gain setting (2-compl) , */\
{ 0x4b61, "adc13_slowdel"}, /* Micadc Delay setting for internal clock. Debug use only, */\
{ 0x4b83, "adc13_offset"}, /* Micadc ADC offset setting , */\
{ 0x4bc0, "adc13_bsoinv"}, /* Micadc bit stream output invert mode for test , */\
{ 0x4bd0, "adc13_resonator_enable"}, /* Micadc Give extra SNR with less stability. Debug use only, */\
{ 0x4be0, "testmicadc"}, /* Mux at input of MICADC for test purpose , */\
{ 0x4c0f, "abist_offset"}, /* offset control for ABIST testing , */\
{ 0x4d05, "windac"}, /* for testing direct control windac , */\
{ 0x4dc3, "pwm_dcc_cnt"}, /* control pwm duty cycle when enbl_pwm_dcc is 1 , */\
{ 0x4e04, "slopecur"}, /* for testing direct control slopecur , */\
{ 0x4e50, "ctrl_dem"}, /* dyn element matching control, rest of codes are optional, */\
{ 0x4ed0, "enbl_pwm_dcc"}, /* to enable direct control of pwm duty cycle , */\
{ 0x5007, "gain"}, /* Gain setting of the gain multiplier , */\
{ 0x5081, "sourceb"}, /* Set OUTB to , */\
{ 0x50a1, "sourcea"}, /* Set OUTA to , */\
{ 0x50c1, "sourcebst"}, /* Sets the source of the pwmbst output to boost converter input for testing, */\
{ 0x50e0, "tdm_enable_loopback"}, /* TDM loopback test , */\
{ 0x5104, "pulselengthbst"}, /* pulse length setting test input for boost converter, */\
{ 0x5150, "bypasslatchbst"}, /* bypass_latch in boost converter , */\
{ 0x5160, "invertbst"}, /* invert pwmbst test signal , */\
{ 0x5174, "pulselength"}, /* pulse length setting test input for amplifier , */\
{ 0x51c0, "bypasslatch"}, /* bypass_latch in PWM source selection module , */\
{ 0x51d0, "invertb"}, /* invert pwmb test signal , */\
{ 0x51e0, "inverta"}, /* invert pwma test signal , */\
{ 0x51f0, "bypass_ctrlloop"}, /* bypass_ctrlloop bypasses the control loop of the amplifier, */\
{ 0x5210, "test_rdsona"}, /* tbd for rdson testing , */\
{ 0x5220, "test_rdsonb"}, /* tbd for rdson testing , */\
{ 0x5230, "test_rdsonbst"}, /* tbd for rdson testing , */\
{ 0x5240, "test_cvia"}, /* tbd for rdson testing , */\
{ 0x5250, "test_cvib"}, /* tbd for rdson testing , */\
{ 0x5260, "test_cvibst"}, /* tbd for rdson testing , */\
{ 0x5306, "digimuxa_sel"}, /* DigimuxA input selection control (see Digimux list for details), */\
{ 0x5376, "digimuxb_sel"}, /* DigimuxB input selection control (see Digimux list for details), */\
{ 0x5400, "hs_mode"}, /* hs_mode, high speed mode I2C bus , */\
{ 0x5412, "test_parametric_io"}, /* test_parametric_io for testing pads , */\
{ 0x5440, "enbl_ringo"}, /* enbl_ringo, for test purpose to check with ringo , */\
{ 0x5456, "digimuxc_sel"}, /* DigimuxC input selection control (see Digimux list for details), */\
{ 0x54c0, "dio_ehs"}, /* Slew control for DIO in output mode , */\
{ 0x54d0, "gainio_ehs"}, /* Slew control for GAINIO in output mode , */\
{ 0x550d, "enbl_amp"}, /* enbl_amp for testing to enable all analoge blocks in amplifier, */\
{ 0x5600, "use_direct_ctrls"}, /* use_direct_ctrls, to overrule several functions direct for testing, */\
{ 0x5610, "rst_datapath"}, /* rst_datapath, datapath reset , */\
{ 0x5620, "rst_cgu"}, /* rst_cgu, cgu reset , */\
{ 0x5637, "enbl_ref"}, /* for testing to enable all analoge blocks in references, */\
{ 0x56b0, "enbl_engage"}, /* Enable output stage amplifier , */\
{ 0x56c0, "use_direct_clk_ctrl"}, /* use_direct_clk_ctrl, to overrule several functions direct for testing, */\
{ 0x56d0, "use_direct_pll_ctrl"}, /* use_direct_pll_ctrl, to overrule several functions direct for testing, */\
{ 0x56e0, "use_direct_ctrls_2"}, /* use_direct_sourseamp_ctrls, to overrule several functions direct for testing, */\
{ 0x5707, "anamux"}, /* Anamux control , */\
{ 0x57c0, "ocptest"}, /* ctrl_ocptest, deactivates the over current protection in the power stages of the amplifier. The ocp flag signals stay active., */\
{ 0x57e0, "otptest"}, /* otptest, test mode otp amplifier , */\
{ 0x57f0, "reverse"}, /* 1: Normal mode, slope is controlled , */\
{ 0x5813, "pll_selr"}, /* pll_selr , */\
{ 0x5854, "pll_selp"}, /* pll_selp , */\
{ 0x58a5, "pll_seli"}, /* pll_seli , */\
{ 0x5950, "pll_mdec_msb"}, /* most significant bits of pll_mdec[16] , */\
{ 0x5960, "pll_ndec_msb"}, /* most significant bits of pll_ndec[9] , */\
{ 0x5970, "pll_frm"}, /* pll_frm , */\
{ 0x5980, "pll_directi"}, /* pll_directi , */\
{ 0x5990, "pll_directo"}, /* pll_directo , */\
{ 0x59a0, "enbl_pll"}, /* enbl_pll , */\
{ 0x59f0, "pll_bypass"}, /* pll_bypass , */\
{ 0x5a0f, "tsig_freq"}, /* tsig_freq, internal sinus test generator, frequency control, */\
{ 0x5b02, "tsig_freq_msb"}, /* select internal sinus test generator, frequency control msb bits, */\
{ 0x5b30, "inject_tsig"}, /* inject_tsig, control bit to switch to internal sinus test generator, */\
{ 0x5b44, "adc10_prog_sample"}, /* control ADC10 , */\
{ 0x5c0f, "pll_mdec"}, /* bits 15..0 of pll_mdec[16;0] , */\
{ 0x5d06, "pll_pdec"}, /* pll_pdec , */\
{ 0x5d78, "pll_ndec"}, /* bits 8..0 of pll_ndec[9;0] , */\
{ 0x6007, "mtpkey1"}, /* 5Ah, 90d To access KEY1_Protected registers (Default for engineering), */\
{ 0x6185, "mtp_ecc_tcin"}, /* Mtp_ecc_tcin , */\
{ 0x6203, "mtp_man_address_in"}, /* address from I2C regs for writing one word single mtp, */\
{ 0x6260, "mtp_ecc_eeb"}, /* enable code bit generation (active low!) , */\
{ 0x6270, "mtp_ecc_ecb"}, /* enable correction signal (active low!) , */\
{ 0x6280, "man_copy_mtp_to_iic"}, /* start copying single word from mtp to i2cregs_mtp , */\
{ 0x6290, "man_copy_iic_to_mtp"}, /* start copying single word from i2cregs_mtp to mtp [Key 1 protected], */\
{ 0x62a0, "auto_copy_mtp_to_iic"}, /* start copying all the data from mtp to i2cregs_mtp, */\
{ 0x62b0, "auto_copy_iic_to_mtp"}, /* start copying all the data from i2cregs_mtp to mtp [Key 2 protected], */\
{ 0x62d2, "mtp_speed_mode"}, /* Speed mode , */\
{ 0x6340, "mtp_direct_enable"}, /* mtp_direct_enable (key1 protected) , */\
{ 0x6350, "mtp_direct_wr"}, /* mtp_direct_wr (key1 protected) , */\
{ 0x6360, "mtp_direct_rd"}, /* mtp_direct_rd (key1 protected) , */\
{ 0x6370, "mtp_direct_rst"}, /* mtp_direct_rst (key1 protected) , */\
{ 0x6380, "mtp_direct_ers"}, /* mtp_direct_ers (key1 protected) , */\
{ 0x6390, "mtp_direct_prg"}, /* mtp_direct_prg (key1 protected) , */\
{ 0x63a0, "mtp_direct_epp"}, /* mtp_direct_epp (key1 protected) , */\
{ 0x63b4, "mtp_direct_test"}, /* mtp_direct_test (key1 protected) , */\
{ 0x640f, "mtp_man_data_in"}, /* single word to be written to MTP (manual copy) , */\
{ 0x7000, "cf_rst_dsp"}, /* Reset CoolFlux DSP , */\
{ 0x7011, "cf_dmem"}, /* Target memory for access , */\
{ 0x7030, "cf_aif"}, /* Autoincrement-flag for memory-address , */\
{ 0x7040, "cf_int"}, /* Interrupt CoolFlux DSP , */\
{ 0x7087, "cf_req"}, /* request for access (8 channels) , */\
{ 0x710f, "cf_madd"}, /* memory-address to be accessed , */\
{ 0x720f, "cf_mema"}, /* activate memory access (24- or 32-bits data is written/read to/from memory, */\
{ 0x7307, "cf_err"}, /* Coolflux error flags , */\
{ 0x7387, "cf_ack"}, /* acknowledge of requests (8 channels) , */\
{ 0x8000, "calibration_onetime"}, /* Calibration schedule (key2 protected) , */\
{ 0x8010, "calibr_ron_done"}, /* (key2 protected) , */\
{ 0x8105, "calibr_vout_offset"}, /* calibr_vout_offset (DCDCoffset) 2's compliment (key1 protected), */\
{ 0x8163, "calibr_delta_gain"}, /* delta gain for vamp (alpha) 2's compliment (key1 protected), */\
{ 0x81a5, "calibr_offs_amp"}, /* offset for vamp (Ampoffset) 2's compliment (key1 protected), */\
{ 0x8207, "calibr_gain_cs"}, /* gain current sense (Imeasalpha) 2's compliment (key1 protected), */\
{ 0x8284, "calibr_temp_offset"}, /* temperature offset 2's compliment (key1 protected), */\
{ 0x82d2, "calibr_temp_gain"}, /* temperature gain 2's compliment (key1 protected) , */\
{ 0x830f, "calibr_ron"}, /* Ron resistance of coil (key1 protected) , */\
{ 0x8505, "type_bits_HW"}, /* Key1_Protected_MTP5 , */\
{ 0x8601, "type_bits_1_0_SW"}, /* MTP-control SW , */\
{ 0x8681, "type_bits_8_9_SW"}, /* MTP-control SW , */\
{ 0x870f, "type_bits2_SW"}, /* MTP-control SW2 , */\
{ 0x8806, "htol_iic_addr"}, /* 7-bit I2C address to be used during HTOL testing , */\
{ 0x8870, "htol_iic_addr_en"}, /* HTOL_I2C_Address_Enable , */\
{ 0x8881, "ctrl_ovp_response"}, /* OVP response control , */\
{ 0x88a0, "disable_ovp_alarm_state"}, /* OVP alarm state control , */\
{ 0x88b0, "enbl_stretch_ovp"}, /* OVP alram strech control , */\
{ 0x88c0, "cf_debug_mode"}, /* Coolflux debug mode , */\
{ 0x8a0f, "production_data1"}, /* (key1 protected) , */\
{ 0x8b0f, "production_data2"}, /* (key1 protected) , */\
{ 0x8c0f, "production_data3"}, /* (key1 protected) , */\
{ 0x8d0f, "production_data4"}, /* (key1 protected) , */\
{ 0x8e0f, "production_data5"}, /* (key1 protected) , */\
{ 0x8f0f, "production_data6"}, /* (key1 protected) , */\
{ 0xffff,"Unknown bitfield enum" } /* not found */\
};
enum tfa1_irq {
tfa1_irq_vdds = 0,
tfa1_irq_plls = 1,
tfa1_irq_ds = 2,
tfa1_irq_vds = 3,
tfa1_irq_uvds = 4,
tfa1_irq_cds = 5,
tfa1_irq_clks = 6,
tfa1_irq_clips = 7,
tfa1_irq_mtpb = 8,
tfa1_irq_clk = 9,
tfa1_irq_spks = 10,
tfa1_irq_acs = 11,
tfa1_irq_sws = 12,
tfa1_irq_wds = 13,
tfa1_irq_amps = 14,
tfa1_irq_arefs = 15,
tfa1_irq_ack = 32,
tfa1_irq_max = 33,
tfa1_irq_all = -1 /* all irqs */};
#define TFA1_IRQ_NAMETABLE static tfaIrqName_t Tfa1IrqNames[]= {\
{ 0, "VDDS"},\
{ 1, "PLLS"},\
{ 2, "DS"},\
{ 3, "VDS"},\
{ 4, "UVDS"},\
{ 5, "CDS"},\
{ 6, "CLKS"},\
{ 7, "CLIPS"},\
{ 8, "MTPB"},\
{ 9, "CLK"},\
{ 10, "SPKS"},\
{ 11, "ACS"},\
{ 12, "SWS"},\
{ 13, "WDS"},\
{ 14, "AMPS"},\
{ 15, "AREFS"},\
{ 16, "16"},\
{ 17, "17"},\
{ 18, "18"},\
{ 19, "19"},\
{ 20, "20"},\
{ 21, "21"},\
{ 22, "22"},\
{ 23, "23"},\
{ 24, "24"},\
{ 25, "25"},\
{ 26, "26"},\
{ 27, "27"},\
{ 28, "28"},\
{ 29, "29"},\
{ 30, "30"},\
{ 31, "31"},\
{ 32, "ACK"},\
{ 33, "33"},\
};

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/*
* Copyright (C) 2014-2020 NXP Semiconductors, All Rights Reserved.
* Copyright 2020 GOODIX
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
*/
/** Filename: tfa9873_tfaFieldnames.h
* This file was generated automatically on 10/21/19 at 17:03:34.
* Source file: TFA9873_PRB4_N1A0_I2C_RegisterMap.xlsx
*/
#ifndef _TFA9873_TFAFIELDNAMES_H
#define _TFA9873_TFAFIELDNAMES_H
#define TFA9873_I2CVERSION 28
typedef enum Tfa9873BfEnumList {
TFA9873_BF_PWDN = 0x0000, /*!< Powerdown selection */
TFA9873_BF_I2CR = 0x0010, /*!< I2C reset - auto clear */
TFA9873_BF_AMPE = 0x0030, /*!< Activate amplifier */
TFA9873_BF_DCA = 0x0040, /*!< Activate DC-to-DC converter */
TFA9873_BF_INTP = 0x0071, /*!< Interrupt config */
TFA9873_BF_FSSSEL= 0x0090, /*!< Audio sample reference */
TFA9873_BF_BYPOCP= 0x00b0, /*!< Bypass OCP */
TFA9873_BF_TSTOCP= 0x00c0, /*!< OCP testing control */
TFA9873_BF_ENPLLSYNC= 0x00e0, /*!< Manager control for enabling synchronisation with PLL FS */
TFA9873_BF_AMPINSEL= 0x0101, /*!< Amplifier input selection */
TFA9873_BF_MANSCONF= 0x0120, /*!< I2C configured */
TFA9873_BF_MUTETO= 0x0160, /*!< Time out SB mute sequence */
TFA9873_BF_OPENMTP= 0x01e0, /*!< Control for FAIM protection */
TFA9873_BF_DISFCRBST= 0x01f0, /*!< Disable boost control with FRCBST */
TFA9873_BF_AUDFS = 0x0203, /*!< Sample rate (fs) */
TFA9873_BF_INPLEV= 0x0240, /*!< TDM output attenuation */
TFA9873_BF_FRACTDEL= 0x0255, /*!< V/I Fractional delay */
TFA9873_BF_REV = 0x030f, /*!< Device revision information */
TFA9873_BF_REFCKEXT= 0x0401, /*!< PLL external ref clock */
TFA9873_BF_REFCKSEL= 0x0420, /*!< PLL internal ref clock */
TFA9873_BF_MANAOOSC= 0x0460, /*!< Internal osc off in power down mode */
TFA9873_BF_FSSYNCEN= 0x0480, /*!< Enable FS synchronisation for clock divider */
TFA9873_BF_CLKREFSYNCEN= 0x0490, /*!< Enable PLL reference clock synchronisation for clock divider */
TFA9873_BF_AUTOFROSEL= 0x04a0, /*!< Override automatic OSC selection mechanism */
TFA9873_BF_CGUSYNCDCG= 0x0500, /*!< Clock gating control for CGU synchronisation module */
TFA9873_BF_FRCCLKSPKR= 0x0510, /*!< Force active the speaker sub-system clock when in idle power */
TFA9873_BF_BSTCLKLP= 0x0520, /*!< Boost clock control in low power mode1 */
TFA9873_BF_SSFAIME= 0x05c0, /*!< Sub-system FAIM */
TFA9873_BF_CLKCHKLO= 0x0707, /*!< Clock check low threshold */
TFA9873_BF_CLKCHKHI= 0x0787, /*!< Clock check higher threshold */
TFA9873_BF_AMPOCRT= 0x0802, /*!< Amplifier on-off criteria for shutdown */
TFA9873_BF_VDDS = 0x1000, /*!< POR */
TFA9873_BF_DCOCPOK= 0x1010, /*!< DCDC OCP nmos (sticky register, clear on read) */
TFA9873_BF_OTDS = 0x1020, /*!< OTP alarm (sticky register, clear on read) */
TFA9873_BF_OCDS = 0x1030, /*!< OCP amplifier (sticky register, clear on read) */
TFA9873_BF_UVDS = 0x1040, /*!< UVP alarm (sticky register, clear on read) */
TFA9873_BF_MANALARM= 0x1050, /*!< Alarm state */
TFA9873_BF_CLKS = 0x1060, /*!< Clocks stable */
TFA9873_BF_MTPB = 0x1070, /*!< MTP busy */
TFA9873_BF_NOCLK = 0x1080, /*!< Lost clock (sticky register, clear on read) */
TFA9873_BF_TDMERR= 0x10a0, /*!< TDM error */
TFA9873_BF_DCIL = 0x1100, /*!< DCDC current limiting */
TFA9873_BF_DCDCA = 0x1110, /*!< DCDC active (sticky register, clear on read) */
TFA9873_BF_DCDCPC= 0x1120, /*!< Indicates current is max in DC-to-DC converter */
TFA9873_BF_DCHVBAT= 0x1130, /*!< DCDC level 1x */
TFA9873_BF_DCH114= 0x1140, /*!< DCDC level 1.14x */
TFA9873_BF_DCH107= 0x1150, /*!< DCDC level 1.07x */
TFA9873_BF_PLLS = 0x1160, /*!< PLL lock */
TFA9873_BF_TDMLUTER= 0x1180, /*!< TDM LUT error */
TFA9873_BF_CLKOOR= 0x11c0, /*!< External clock status */
TFA9873_BF_SWS = 0x11d0, /*!< Amplifier engage */
TFA9873_BF_AMPS = 0x11e0, /*!< Amplifier enable */
TFA9873_BF_AREFS = 0x11f0, /*!< References enable */
TFA9873_BF_OCPOAP= 0x1300, /*!< OCPOK pmos A */
TFA9873_BF_OCPOAN= 0x1310, /*!< OCPOK nmos A */
TFA9873_BF_OCPOBP= 0x1320, /*!< OCPOK pmos B */
TFA9873_BF_OCPOBN= 0x1330, /*!< OCPOK nmos B */
TFA9873_BF_OVDS = 0x1380, /*!< OVP alarm */
TFA9873_BF_CLIPS = 0x1390, /*!< Amplifier clipping */
TFA9873_BF_ADCCR = 0x13a0, /*!< Control ADC */
TFA9873_BF_MANWAIT1= 0x13c0, /*!< Wait HW I2C settings */
TFA9873_BF_MANMUTE= 0x13e0, /*!< Audio mute sequence */
TFA9873_BF_MANOPER= 0x13f0, /*!< Operating state */
TFA9873_BF_TDMSTAT= 0x1402, /*!< TDM status bits */
TFA9873_BF_MANSTATE= 0x1433, /*!< Device manager status */
TFA9873_BF_AMPSTE= 0x1473, /*!< Amplifier control status */
TFA9873_BF_DCMODE= 0x14b1, /*!< DCDC mode status bits */
TFA9873_BF_WAITSYNC= 0x14d0, /*!< CGU and PLL synchronisation status flag from CGU */
TFA9873_BF_BATS = 0x1509, /*!< Battery voltage (V) */
TFA9873_BF_TEMPS = 0x1608, /*!< IC Temperature (C) */
TFA9873_BF_VDDPS = 0x1709, /*!< IC VDDP voltage ( 1023*VDDP/13 V) */
TFA9873_BF_TDME = 0x2000, /*!< Enable interface */
TFA9873_BF_TDMSLOTS= 0x2013, /*!< N-slots in Frame */
TFA9873_BF_TDMCLINV= 0x2060, /*!< Reception data to BCK clock */
TFA9873_BF_TDMFSLN= 0x2073, /*!< FS length */
TFA9873_BF_TDMFSPOL= 0x20b0, /*!< FS polarity */
TFA9873_BF_TDMNBCK= 0x20c3, /*!< N-BCK's in FS */
TFA9873_BF_TDMSLLN= 0x2144, /*!< N-bits in slot */
TFA9873_BF_TDMBRMG= 0x2194, /*!< N-bits remaining */
TFA9873_BF_TDMDEL= 0x21e0, /*!< Data delay to FS */
TFA9873_BF_TDMADJ= 0x21f0, /*!< Data adjustment */
TFA9873_BF_TDMOOMP= 0x2201, /*!< Received audio compression */
TFA9873_BF_TDMSSIZE= 0x2224, /*!< Sample size per slot */
TFA9873_BF_TDMTXDFO= 0x2271, /*!< Format unused bits */
TFA9873_BF_TDMTXUS0= 0x2291, /*!< Format unused slots DATAO */
TFA9873_BF_TDMSPKE= 0x2300, /*!< Control audio TDM channel in 0 */
TFA9873_BF_TDMDCE= 0x2310, /*!< Control audio TDM channel in 1 */
TFA9873_BF_TDMCSE= 0x2330, /*!< current sense vbat temperature and vddp feedback */
TFA9873_BF_TDMVSE= 0x2340, /*!< Voltage sense vbat temperature and vddp feedback */
TFA9873_BF_TDMSPKS= 0x2603, /*!< TDM slot for sink 0 */
TFA9873_BF_TDMDCS= 0x2643, /*!< TDM slot for sink 1 */
TFA9873_BF_TDMCSS= 0x26c3, /*!< Slot Position of current sense vbat temperature and vddp feedback */
TFA9873_BF_TDMVSS= 0x2703, /*!< Slot Position of Voltage sense vbat temperature and vddp feedback */
TFA9873_BF_ISTVDDS= 0x4000, /*!< Status POR */
TFA9873_BF_ISTBSTOC= 0x4010, /*!< Status DCDC OCP */
TFA9873_BF_ISTOTDS= 0x4020, /*!< Status OTP alarm */
TFA9873_BF_ISTOCPR= 0x4030, /*!< Status OCP alarm */
TFA9873_BF_ISTUVDS= 0x4040, /*!< Status UVP alarm */
TFA9873_BF_ISTMANALARM= 0x4050, /*!< Status manager alarm state */
TFA9873_BF_ISTTDMER= 0x4060, /*!< Status TDM error */
TFA9873_BF_ISTNOCLK= 0x4070, /*!< Status lost clock */
TFA9873_BF_ICLVDDS= 0x4400, /*!< Clear POR */
TFA9873_BF_ICLBSTOC= 0x4410, /*!< Clear DCDC OCP */
TFA9873_BF_ICLOTDS= 0x4420, /*!< Clear OTP alarm */
TFA9873_BF_ICLOCPR= 0x4430, /*!< Clear OCP alarm */
TFA9873_BF_ICLUVDS= 0x4440, /*!< Clear UVP alarm */
TFA9873_BF_ICLMANALARM= 0x4450, /*!< Clear manager alarm state */
TFA9873_BF_ICLTDMER= 0x4460, /*!< Clear TDM error */
TFA9873_BF_ICLNOCLK= 0x4470, /*!< Clear lost clk */
TFA9873_BF_IEVDDS= 0x4800, /*!< Enable POR */
TFA9873_BF_IEBSTOC= 0x4810, /*!< Enable DCDC OCP */
TFA9873_BF_IEOTDS= 0x4820, /*!< Enable OTP alarm */
TFA9873_BF_IEOCPR= 0x4830, /*!< Enable OCP alarm */
TFA9873_BF_IEUVDS= 0x4840, /*!< Enable UVP alarm */
TFA9873_BF_IEMANALARM= 0x4850, /*!< Enable manager alarm state */
TFA9873_BF_IETDMER= 0x4860, /*!< Enable TDM error */
TFA9873_BF_IENOCLK= 0x4870, /*!< Enable lost clk */
TFA9873_BF_IPOVDDS= 0x4c00, /*!< Polarity POR */
TFA9873_BF_IPOBSTOC= 0x4c10, /*!< Polarity DCDC OCP */
TFA9873_BF_IPOOTDS= 0x4c20, /*!< Polarity OTP alarm */
TFA9873_BF_IPOOCPR= 0x4c30, /*!< Polarity OCP alarm */
TFA9873_BF_IPOUVDS= 0x4c40, /*!< Polarity UVP alarm */
TFA9873_BF_IPOMANALARM= 0x4c50, /*!< Polarity manager alarm state */
TFA9873_BF_IPOTDMER= 0x4c60, /*!< Polarity TDM error */
TFA9873_BF_IPONOCLK= 0x4c70, /*!< Polarity lost clk */
TFA9873_BF_BSSCR = 0x5001, /*!< Battery safeguard attack time */
TFA9873_BF_BSST = 0x5023, /*!< Battery safeguard threshold voltage level */
TFA9873_BF_BSSRL = 0x5061, /*!< Battery safeguard maximum reduction */
TFA9873_BF_BSSR = 0x50e0, /*!< Battery voltage read out */
TFA9873_BF_BSSBY = 0x50f0, /*!< Bypass battery safeguard */
TFA9873_BF_BSSS = 0x5100, /*!< Vbat prot steepness */
TFA9873_BF_HPFBYP= 0x5150, /*!< Bypass HPF */
TFA9873_BF_DPSA = 0x5170, /*!< Enable DPSA */
TFA9873_BF_BYHWCLIP= 0x5240, /*!< Bypass hardware clipper */
TFA9873_BF_AMPGAIN= 0x5257, /*!< Amplifier gain */
TFA9873_BF_SLOPEE= 0x52d0, /*!< Enables slope control */
TFA9873_BF_SLOPESET= 0x52e0, /*!< Slope speed setting (bin. coded) */
TFA9873_BF_BYPDLYLINE= 0x52f0, /*!< Bypass the interpolator delay line */
TFA9873_BF_TDMSPKG= 0x5f63, /*!< Total gain depending on INPLEV setting (channel 0) */
TFA9873_BF_IPM = 0x60e1, /*!< Idle power mode control */
TFA9873_BF_LNMODE= 0x62e1, /*!< Ctrl select mode */
TFA9873_BF_LPM1MODE= 0x64e1, /*!< Low power mode control */
TFA9873_BF_TDMSRCMAP= 0x6802, /*!< TDM source mapping */
TFA9873_BF_TDMSRCAS= 0x6831, /*!< Sensed value A */
TFA9873_BF_TDMSRCBS= 0x6851, /*!< Sensed value B */
TFA9873_BF_TDMSRCACLIP= 0x6871, /*!< Clip information (analog /digital) for source0 */
TFA9873_BF_TDMSRCBCLIP= 0x6891, /*!< Clip information (analog /digital) for source1 */
TFA9873_BF_LP0 = 0x6e00, /*!< Idle power mode */
TFA9873_BF_LP1 = 0x6e10, /*!< Low power mode 1 detection */
TFA9873_BF_LA = 0x6e20, /*!< Low amplitude detection */
TFA9873_BF_VDDPH = 0x6e30, /*!< Vddp greater than Vbat */
TFA9873_BF_DELCURCOMP= 0x6f02, /*!< Delay to allign compensation signal with current sense signal */
TFA9873_BF_SIGCURCOMP= 0x6f40, /*!< Polarity of compensation for current sense */
TFA9873_BF_ENCURCOMP= 0x6f50, /*!< Enable current sense compensation */
TFA9873_BF_LVLCLPPWM= 0x6f72, /*!< Set the amount of pwm pulse that may be skipped before clip-flag is triggered */
TFA9873_BF_DCMCC = 0x7003, /*!< Max coil current */
TFA9873_BF_DCCV = 0x7041, /*!< Slope compensation current, represents LxF (inductance x frequency) */
TFA9873_BF_DCIE = 0x7060, /*!< Adaptive boost mode */
TFA9873_BF_DCSR = 0x7070, /*!< Soft ramp up/down */
TFA9873_BF_DCOVL = 0x7085, /*!< Threshold level to activate active overshoot control */
TFA9873_BF_DCDIS = 0x70e0, /*!< DCDC on/off */
TFA9873_BF_DCPWM = 0x70f0, /*!< DCDC PWM only mode */
TFA9873_BF_DCDYFSW= 0x7420, /*!< Disables the dynamic frequency switching due to flag_voutcomp86/93 */
TFA9873_BF_DCTRACK= 0x7430, /*!< Boost algorithm selection, effective only when boost_intelligent is set to 1 */
TFA9873_BF_DCTRIP= 0x7444, /*!< 1st Adaptive boost trip levels, effective only when DCIE is set to 1 */
TFA9873_BF_DCHOLD= 0x7494, /*!< Hold time for DCDC booster, effective only when boost_intelligent is set to 1 */
TFA9873_BF_DCINT = 0x74e0, /*!< Selection of data for adaptive boost algorithm, effective only when boost_intelligent is set to 1 */
TFA9873_BF_DCTRIP2= 0x7534, /*!< 2nd Adaptive boost trip levels, effective only when DCIE is set to 1 */
TFA9873_BF_DCTRIPT= 0x7584, /*!< Track Adaptive boost trip levels, effective only when boost_intelligent is set to 1 */
TFA9873_BF_DCTRIPHYSTE= 0x75f0, /*!< Enable hysteresis on booster trip levels */
TFA9873_BF_ENBSTFLT= 0x7620, /*!< Enable the boost filter */
TFA9873_BF_DCVOF = 0x7635, /*!< First boost voltage level */
TFA9873_BF_DCVOS = 0x7695, /*!< Second boost voltage level */
TFA9873_BF_MTPK = 0xa107, /*!< MTP KEY2 register */
TFA9873_BF_KEY1LOCKED= 0xa200, /*!< Indicates KEY1 is locked */
TFA9873_BF_KEY2LOCKED= 0xa210, /*!< Indicates KEY2 is locked */
TFA9873_BF_MTPADDR= 0xa302, /*!< MTP address from I2C register for read/writing mtp in manual single word mode */
TFA9873_BF_MTPRDMSB= 0xa50f, /*!< MSB word of MTP manual read data */
TFA9873_BF_MTPRDLSB= 0xa60f, /*!< LSB word of MTP manual read data */
TFA9873_BF_MTPWRMSB= 0xa70f, /*!< MSB word of write data for MTP manual write */
TFA9873_BF_MTPWRLSB= 0xa80f, /*!< LSB word of write data for MTP manual write */
TFA9873_BF_EXTTS = 0xb108, /*!< External temperature (C) */
TFA9873_BF_TROS = 0xb190, /*!< Select temp Speaker calibration */
TFA9873_BF_PLLINSI= 0xcd05, /*!< PLL INSELI - PLL direct bandwidth control mode, only with pll_bandsel set to 1 */
TFA9873_BF_PLLINSP= 0xcd64, /*!< PLL INSELP - PLL direct bandwidth control mode only with pll_bandsel set to 1 */
TFA9873_BF_PLLINSR= 0xcdb3, /*!< PLL INSELR - PLL direct bandwidth control mode only with pll_bandsel set to 1 */
TFA9873_BF_PLLBDSEL= 0xcdf0, /*!< PLL bandwidth selection control, USE WITH CAUTION */
TFA9873_BF_PLLNDEC= 0xce09, /*!< PLL NDEC in direct control mode only, use_direct_pll_ctrl set to 1 */
TFA9873_BF_PLLMDECM= 0xcea0, /*!< MSB of PLL MDEC in direct control mode only, use_direct_pll_ctrl set to 1 */
TFA9873_BF_PLLBP = 0xceb0, /*!< PLL bypass control during functional mode */
TFA9873_BF_PLLDI = 0xcec0, /*!< PLL directi control in direct control mode only, use_direct_pll_ctrl set to 1 */
TFA9873_BF_PLLDO = 0xced0, /*!< PLL directo control in direct control mode only, use_direct_pll_ctrl set to 1 */
TFA9873_BF_PLLCLKSTB= 0xcee0, /*!< PLL FRM clock stable control in direct control mode only, use_direct_pll_ctrl set to 1 */
TFA9873_BF_PLLFRM= 0xcef0, /*!< PLL free running mode control in functional mode */
TFA9873_BF_PLLMDECL= 0xcf0f, /*!< Bits 15 to 0 of PLL MDEC in direct control mode, use_direct_pll_ctrl set to 1 */
TFA9873_BF_PLLPDEC= 0xd006, /*!< PLL PDEC in direct control mode only, use_direct_pll_ctrl set to 1 */
TFA9873_BF_PLLDCTRL= 0xd070, /*!< Enabled PLL direct control mode, overrules the PLL LUT with I2C register values */
TFA9873_BF_PLLLIMOFF= 0xd090, /*!< PLL up limiter control in PLL direct bandwidth control mode, pll_bandsel set to 1 */
TFA9873_BF_PLLSTRTM= 0xd0a2, /*!< PLL startup time selection control */
TFA9873_BF_SWPROFIL= 0xe00f, /*!< Software profile data */
TFA9873_BF_SWVSTEP= 0xe10f, /*!< Software vstep information */
TFA9873_BF_MTPOTC= 0xf000, /*!< Calibration schedule */
TFA9873_BF_MTPEX = 0xf010, /*!< Calibration Ron executed */
TFA9873_BF_DCMCCAPI= 0xf020, /*!< Calibration current limit DCDC */
TFA9873_BF_DCMCCSB= 0xf030, /*!< Sign bit for delta calibration current limit DCDC */
TFA9873_BF_USERDEF= 0xf042, /*!< Calibration delta current limit DCDC */
TFA9873_BF_CUSTINFO= 0xf078, /*!< Reserved space for allowing customer to store speaker information */
TFA9873_BF_R25C = 0xf50f, /*!< Ron resistance of speaker coil */
} Tfa9873BfEnumList_t;
#define TFA9873_NAMETABLE static tfaBfName_t Tfa9873DatasheetNames[]= {\
{ 0x0, "PWDN"}, /* Powerdown selection , */\
{ 0x10, "I2CR"}, /* I2C reset - auto clear , */\
{ 0x30, "AMPE"}, /* Activate amplifier , */\
{ 0x40, "DCA"}, /* Activate DC-to-DC converter , */\
{ 0x71, "INTP"}, /* Interrupt config , */\
{ 0x90, "FSSSEL"}, /* Audio sample reference , */\
{ 0xb0, "BYPOCP"}, /* Bypass OCP , */\
{ 0xc0, "TSTOCP"}, /* OCP testing control , */\
{ 0xe0, "ENPLLSYNC"}, /* Manager control for enabling synchronisation with PLL FS, */\
{ 0x101, "AMPINSEL"}, /* Amplifier input selection , */\
{ 0x120, "MANSCONF"}, /* I2C configured , */\
{ 0x160, "MUTETO"}, /* Time out SB mute sequence , */\
{ 0x1e0, "OPENMTP"}, /* Control for FAIM protection , */\
{ 0x1f0, "DISFCRBST"}, /* Disable boost control with FRCBST , */\
{ 0x203, "AUDFS"}, /* Sample rate (fs) , */\
{ 0x240, "INPLEV"}, /* TDM output attenuation , */\
{ 0x255, "FRACTDEL"}, /* V/I Fractional delay , */\
{ 0x30f, "REV"}, /* Device revision information , */\
{ 0x401, "REFCKEXT"}, /* PLL external ref clock , */\
{ 0x420, "REFCKSEL"}, /* PLL internal ref clock , */\
{ 0x460, "MANAOOSC"}, /* Internal osc off in power down mode , */\
{ 0x480, "FSSYNCEN"}, /* Enable FS synchronisation for clock divider , */\
{ 0x490, "CLKREFSYNCEN"}, /* Enable PLL reference clock synchronisation for clock divider, */\
{ 0x4a0, "AUTOFROSEL"}, /* Override automatic OSC selection mechanism , */\
{ 0x500, "CGUSYNCDCG"}, /* Clock gating control for CGU synchronisation module, */\
{ 0x510, "FRCCLKSPKR"}, /* Force active the speaker sub-system clock when in idle power, */\
{ 0x520, "BSTCLKLP"}, /* Boost clock control in low power mode1 , */\
{ 0x5c0, "SSFAIME"}, /* Sub-system FAIM , */\
{ 0x707, "CLKCHKLO"}, /* Clock check low threshold , */\
{ 0x787, "CLKCHKHI"}, /* Clock check higher threshold , */\
{ 0x802, "AMPOCRT"}, /* Amplifier on-off criteria for shutdown , */\
{ 0x1000, "VDDS"}, /* POR , */\
{ 0x1010, "DCOCPOK"}, /* DCDC OCP nmos (sticky register, clear on read) , */\
{ 0x1020, "OTDS"}, /* OTP alarm (sticky register, clear on read) , */\
{ 0x1030, "OCDS"}, /* OCP amplifier (sticky register, clear on read) , */\
{ 0x1040, "UVDS"}, /* UVP alarm (sticky register, clear on read) , */\
{ 0x1050, "MANALARM"}, /* Alarm state , */\
{ 0x1060, "CLKS"}, /* Clocks stable , */\
{ 0x1070, "MTPB"}, /* MTP busy , */\
{ 0x1080, "NOCLK"}, /* Lost clock (sticky register, clear on read) , */\
{ 0x10a0, "TDMERR"}, /* TDM error , */\
{ 0x1100, "DCIL"}, /* DCDC current limiting , */\
{ 0x1110, "DCDCA"}, /* DCDC active (sticky register, clear on read) , */\
{ 0x1120, "DCDCPC"}, /* Indicates current is max in DC-to-DC converter , */\
{ 0x1130, "DCHVBAT"}, /* DCDC level 1x , */\
{ 0x1140, "DCH114"}, /* DCDC level 1.14x , */\
{ 0x1150, "DCH107"}, /* DCDC level 1.07x , */\
{ 0x1160, "PLLS"}, /* PLL lock , */\
{ 0x1180, "TDMLUTER"}, /* TDM LUT error , */\
{ 0x11c0, "CLKOOR"}, /* External clock status , */\
{ 0x11d0, "SWS"}, /* Amplifier engage , */\
{ 0x11e0, "AMPS"}, /* Amplifier enable , */\
{ 0x11f0, "AREFS"}, /* References enable , */\
{ 0x1300, "OCPOAP"}, /* OCPOK pmos A , */\
{ 0x1310, "OCPOAN"}, /* OCPOK nmos A , */\
{ 0x1320, "OCPOBP"}, /* OCPOK pmos B , */\
{ 0x1330, "OCPOBN"}, /* OCPOK nmos B , */\
{ 0x1380, "OVDS"}, /* OVP alarm , */\
{ 0x1390, "CLIPS"}, /* Amplifier clipping , */\
{ 0x13a0, "ADCCR"}, /* Control ADC , */\
{ 0x13c0, "MANWAIT1"}, /* Wait HW I2C settings , */\
{ 0x13e0, "MANMUTE"}, /* Audio mute sequence , */\
{ 0x13f0, "MANOPER"}, /* Operating state , */\
{ 0x1402, "TDMSTAT"}, /* TDM status bits , */\
{ 0x1433, "MANSTATE"}, /* Device manager status , */\
{ 0x1473, "AMPSTE"}, /* Amplifier control status , */\
{ 0x14b1, "DCMODE"}, /* DCDC mode status bits , */\
{ 0x14d0, "WAITSYNC"}, /* CGU and PLL synchronisation status flag from CGU , */\
{ 0x1509, "BATS"}, /* Battery voltage (V) , */\
{ 0x1608, "TEMPS"}, /* IC Temperature (C) , */\
{ 0x1709, "VDDPS"}, /* IC VDDP voltage ( 1023*VDDP/13 V) , */\
{ 0x2000, "TDME"}, /* Enable interface , */\
{ 0x2013, "TDMSLOTS"}, /* N-slots in Frame , */\
{ 0x2060, "TDMCLINV"}, /* Reception data to BCK clock , */\
{ 0x2073, "TDMFSLN"}, /* FS length , */\
{ 0x20b0, "TDMFSPOL"}, /* FS polarity , */\
{ 0x20c3, "TDMNBCK"}, /* N-BCK's in FS , */\
{ 0x2144, "TDMSLLN"}, /* N-bits in slot , */\
{ 0x2194, "TDMBRMG"}, /* N-bits remaining , */\
{ 0x21e0, "TDMDEL"}, /* Data delay to FS , */\
{ 0x21f0, "TDMADJ"}, /* Data adjustment , */\
{ 0x2201, "TDMOOMP"}, /* Received audio compression , */\
{ 0x2224, "TDMSSIZE"}, /* Sample size per slot , */\
{ 0x2271, "TDMTXDFO"}, /* Format unused bits , */\
{ 0x2291, "TDMTXUS0"}, /* Format unused slots DATAO , */\
{ 0x2300, "TDMSPKE"}, /* Control audio TDM channel in 0 , */\
{ 0x2310, "TDMDCE"}, /* Control audio TDM channel in 1 , */\
{ 0x2330, "TDMCSE"}, /* current sense vbat temperature and vddp feedback , */\
{ 0x2340, "TDMVSE"}, /* Voltage sense vbat temperature and vddp feedback , */\
{ 0x2603, "TDMSPKS"}, /* TDM slot for sink 0 , */\
{ 0x2643, "TDMDCS"}, /* TDM slot for sink 1 , */\
{ 0x26c3, "TDMCSS"}, /* Slot Position of current sense vbat temperature and vddp feedback, */\
{ 0x2703, "TDMVSS"}, /* Slot Position of Voltage sense vbat temperature and vddp feedback, */\
{ 0x4000, "ISTVDDS"}, /* Status POR , */\
{ 0x4010, "ISTBSTOC"}, /* Status DCDC OCP , */\
{ 0x4020, "ISTOTDS"}, /* Status OTP alarm , */\
{ 0x4030, "ISTOCPR"}, /* Status OCP alarm , */\
{ 0x4040, "ISTUVDS"}, /* Status UVP alarm , */\
{ 0x4050, "ISTMANALARM"}, /* Status manager alarm state , */\
{ 0x4060, "ISTTDMER"}, /* Status TDM error , */\
{ 0x4070, "ISTNOCLK"}, /* Status lost clock , */\
{ 0x4400, "ICLVDDS"}, /* Clear POR , */\
{ 0x4410, "ICLBSTOC"}, /* Clear DCDC OCP , */\
{ 0x4420, "ICLOTDS"}, /* Clear OTP alarm , */\
{ 0x4430, "ICLOCPR"}, /* Clear OCP alarm , */\
{ 0x4440, "ICLUVDS"}, /* Clear UVP alarm , */\
{ 0x4450, "ICLMANALARM"}, /* Clear manager alarm state , */\
{ 0x4460, "ICLTDMER"}, /* Clear TDM error , */\
{ 0x4470, "ICLNOCLK"}, /* Clear lost clk , */\
{ 0x4800, "IEVDDS"}, /* Enable POR , */\
{ 0x4810, "IEBSTOC"}, /* Enable DCDC OCP , */\
{ 0x4820, "IEOTDS"}, /* Enable OTP alarm , */\
{ 0x4830, "IEOCPR"}, /* Enable OCP alarm , */\
{ 0x4840, "IEUVDS"}, /* Enable UVP alarm , */\
{ 0x4850, "IEMANALARM"}, /* Enable manager alarm state , */\
{ 0x4860, "IETDMER"}, /* Enable TDM error , */\
{ 0x4870, "IENOCLK"}, /* Enable lost clk , */\
{ 0x4c00, "IPOVDDS"}, /* Polarity POR , */\
{ 0x4c10, "IPOBSTOC"}, /* Polarity DCDC OCP , */\
{ 0x4c20, "IPOOTDS"}, /* Polarity OTP alarm , */\
{ 0x4c30, "IPOOCPR"}, /* Polarity OCP alarm , */\
{ 0x4c40, "IPOUVDS"}, /* Polarity UVP alarm , */\
{ 0x4c50, "IPOMANALARM"}, /* Polarity manager alarm state , */\
{ 0x4c60, "IPOTDMER"}, /* Polarity TDM error , */\
{ 0x4c70, "IPONOCLK"}, /* Polarity lost clk , */\
{ 0x5001, "BSSCR"}, /* Battery safeguard attack time , */\
{ 0x5023, "BSST"}, /* Battery safeguard threshold voltage level , */\
{ 0x5061, "BSSRL"}, /* Battery safeguard maximum reduction , */\
{ 0x50e0, "BSSR"}, /* Battery voltage read out , */\
{ 0x50f0, "BSSBY"}, /* Bypass battery safeguard , */\
{ 0x5100, "BSSS"}, /* Vbat prot steepness , */\
{ 0x5150, "HPFBYP"}, /* Bypass HPF , */\
{ 0x5170, "DPSA"}, /* Enable DPSA , */\
{ 0x5240, "BYHWCLIP"}, /* Bypass hardware clipper , */\
{ 0x5257, "AMPGAIN"}, /* Amplifier gain , */\
{ 0x52d0, "SLOPEE"}, /* Enables slope control , */\
{ 0x52e0, "SLOPESET"}, /* Slope speed setting (bin. coded) , */\
{ 0x52f0, "BYPDLYLINE"}, /* Bypass the interpolator delay line , */\
{ 0x5f63, "TDMSPKG"}, /* Total gain depending on INPLEV setting (channel 0), */\
{ 0x60e1, "IPM"}, /* Idle power mode control , */\
{ 0x62e1, "LNMODE"}, /* Ctrl select mode , */\
{ 0x64e1, "LPM1MODE"}, /* Low power mode control , */\
{ 0x6802, "TDMSRCMAP"}, /* TDM source mapping , */\
{ 0x6831, "TDMSRCAS"}, /* Sensed value A , */\
{ 0x6851, "TDMSRCBS"}, /* Sensed value B , */\
{ 0x6871, "TDMSRCACLIP"}, /* Clip information (analog /digital) for source0 , */\
{ 0x6891, "TDMSRCBCLIP"}, /* Clip information (analog /digital) for source1 , */\
{ 0x6e00, "LP0"}, /* Idle power mode , */\
{ 0x6e10, "LP1"}, /* Low power mode 1 detection , */\
{ 0x6e20, "LA"}, /* Low amplitude detection , */\
{ 0x6e30, "VDDPH"}, /* Vddp greater than Vbat , */\
{ 0x6f02, "DELCURCOMP"}, /* Delay to allign compensation signal with current sense signal, */\
{ 0x6f40, "SIGCURCOMP"}, /* Polarity of compensation for current sense , */\
{ 0x6f50, "ENCURCOMP"}, /* Enable current sense compensation , */\
{ 0x6f72, "LVLCLPPWM"}, /* Set the amount of pwm pulse that may be skipped before clip-flag is triggered, */\
{ 0x7003, "DCMCC"}, /* Max coil current , */\
{ 0x7041, "DCCV"}, /* Slope compensation current, represents LxF (inductance x frequency) , */\
{ 0x7060, "DCIE"}, /* Adaptive boost mode , */\
{ 0x7070, "DCSR"}, /* Soft ramp up/down , */\
{ 0x7085, "DCOVL"}, /* Threshold level to activate active overshoot control, */\
{ 0x70e0, "DCDIS"}, /* DCDC on/off , */\
{ 0x70f0, "DCPWM"}, /* DCDC PWM only mode , */\
{ 0x7420, "DCDYFSW"}, /* Disables the dynamic frequency switching due to flag_voutcomp86/93, */\
{ 0x7430, "DCTRACK"}, /* Boost algorithm selection, effective only when boost_intelligent is set to 1, */\
{ 0x7444, "DCTRIP"}, /* 1st Adaptive boost trip levels, effective only when DCIE is set to 1, */\
{ 0x7494, "DCHOLD"}, /* Hold time for DCDC booster, effective only when boost_intelligent is set to 1, */\
{ 0x74e0, "DCINT"}, /* Selection of data for adaptive boost algorithm, effective only when boost_intelligent is set to 1, */\
{ 0x7534, "DCTRIP2"}, /* 2nd Adaptive boost trip levels, effective only when DCIE is set to 1, */\
{ 0x7584, "DCTRIPT"}, /* Track Adaptive boost trip levels, effective only when boost_intelligent is set to 1, */\
{ 0x75f0, "DCTRIPHYSTE"}, /* Enable hysteresis on booster trip levels , */\
{ 0x7620, "ENBSTFLT"}, /* Enable the boost filter , */\
{ 0x7635, "DCVOF"}, /* First boost voltage level , */\
{ 0x7695, "DCVOS"}, /* Second boost voltage level , */\
{ 0xa107, "MTPK"}, /* MTP KEY2 register , */\
{ 0xa200, "KEY1LOCKED"}, /* Indicates KEY1 is locked , */\
{ 0xa210, "KEY2LOCKED"}, /* Indicates KEY2 is locked , */\
{ 0xa302, "MTPADDR"}, /* MTP address from I2C register for read/writing mtp in manual single word mode, */\
{ 0xa50f, "MTPRDMSB"}, /* MSB word of MTP manual read data , */\
{ 0xa60f, "MTPRDLSB"}, /* LSB word of MTP manual read data , */\
{ 0xa70f, "MTPWRMSB"}, /* MSB word of write data for MTP manual write , */\
{ 0xa80f, "MTPWRLSB"}, /* LSB word of write data for MTP manual write , */\
{ 0xb108, "EXTTS"}, /* External temperature (C) , */\
{ 0xb190, "TROS"}, /* Select temp Speaker calibration , */\
{ 0xcd05, "PLLINSI"}, /* PLL INSELI - PLL direct bandwidth control mode, only with pll_bandsel set to 1, */\
{ 0xcd64, "PLLINSP"}, /* PLL INSELP - PLL direct bandwidth control mode only with pll_bandsel set to 1, */\
{ 0xcdb3, "PLLINSR"}, /* PLL INSELR - PLL direct bandwidth control mode only with pll_bandsel set to 1, */\
{ 0xcdf0, "PLLBDSEL"}, /* PLL bandwidth selection control, USE WITH CAUTION , */\
{ 0xce09, "PLLNDEC"}, /* PLL NDEC in direct control mode only, use_direct_pll_ctrl set to 1, */\
{ 0xcea0, "PLLMDECM"}, /* MSB of PLL MDEC in direct control mode only, use_direct_pll_ctrl set to 1, */\
{ 0xceb0, "PLLBP"}, /* PLL bypass control during functional mode , */\
{ 0xcec0, "PLLDI"}, /* PLL directi control in direct control mode only, use_direct_pll_ctrl set to 1, */\
{ 0xced0, "PLLDO"}, /* PLL directo control in direct control mode only, use_direct_pll_ctrl set to 1, */\
{ 0xcee0, "PLLCLKSTB"}, /* PLL FRM clock stable control in direct control mode only, use_direct_pll_ctrl set to 1, */\
{ 0xcef0, "PLLFRM"}, /* PLL free running mode control in functional mode , */\
{ 0xcf0f, "PLLMDECL"}, /* Bits 15 to 0 of PLL MDEC in direct control mode, use_direct_pll_ctrl set to 1, */\
{ 0xd006, "PLLPDEC"}, /* PLL PDEC in direct control mode only, use_direct_pll_ctrl set to 1, */\
{ 0xd070, "PLLDCTRL"}, /* Enabled PLL direct control mode, overrules the PLL LUT with I2C register values, */\
{ 0xd090, "PLLLIMOFF"}, /* PLL up limiter control in PLL direct bandwidth control mode, pll_bandsel set to 1, */\
{ 0xd0a2, "PLLSTRTM"}, /* PLL startup time selection control , */\
{ 0xe00f, "SWPROFIL"}, /* Software profile data , */\
{ 0xe10f, "SWVSTEP"}, /* Software vstep information , */\
{ 0xf000, "MTPOTC"}, /* Calibration schedule , */\
{ 0xf010, "MTPEX"}, /* Calibration Ron executed , */\
{ 0xf020, "DCMCCAPI"}, /* Calibration current limit DCDC , */\
{ 0xf030, "DCMCCSB"}, /* Sign bit for delta calibration current limit DCDC , */\
{ 0xf042, "USERDEF"}, /* Calibration delta current limit DCDC , */\
{ 0xf078, "CUSTINFO"}, /* Reserved space for allowing customer to store speaker information, */\
{ 0xf50f, "R25C"}, /* Ron resistance of speaker coil , */\
{ 0xffff,"Unknown bitfield enum" } /* not found */\
};
#define TFA9873_BITNAMETABLE static tfaBfName_t Tfa9873BitNames[]= {\
{ 0x0, "powerdown"}, /* Powerdown selection , */\
{ 0x10, "reset"}, /* I2C reset - auto clear , */\
{ 0x30, "enbl_amplifier"}, /* Activate amplifier , */\
{ 0x40, "enbl_boost"}, /* Activate DC-to-DC converter , */\
{ 0x71, "int_pad_io"}, /* Interrupt config , */\
{ 0x90, "fs_pulse_sel"}, /* Audio sample reference , */\
{ 0xb0, "bypass_ocp"}, /* Bypass OCP , */\
{ 0xc0, "test_ocp"}, /* OCP testing control , */\
{ 0xd0, "sel_man_wait_time"}, /* Manager wait time selection control , */\
{ 0xe0, "enbl_pll_synchronisation"}, /* Manager control for enabling synchronisation with PLL FS, */\
{ 0x101, "vamp_sel1"}, /* Amplifier input selection , */\
{ 0x120, "src_set_configured"}, /* I2C configured , */\
{ 0x160, "disable_mute_time_out"}, /* Time out SB mute sequence , */\
{ 0x1e0, "unprotect_faim"}, /* Control for FAIM protection , */\
{ 0x1f0, "disable_frcbst"}, /* Disable boost control with FRCBST , */\
{ 0x203, "audio_fs"}, /* Sample rate (fs) , */\
{ 0x240, "input_level"}, /* TDM output attenuation , */\
{ 0x255, "cs_frac_delay"}, /* V/I Fractional delay , */\
{ 0x30f, "device_rev"}, /* Device revision information , */\
{ 0x401, "pll_clkin_sel"}, /* PLL external ref clock , */\
{ 0x420, "pll_clkin_sel_osc"}, /* PLL internal ref clock , */\
{ 0x460, "enbl_osc_auto_off"}, /* Internal osc off in power down mode , */\
{ 0x480, "enbl_fs_sync"}, /* Enable FS synchronisation for clock divider , */\
{ 0x490, "enbl_clkref_sync"}, /* Enable PLL reference clock synchronisation for clock divider, */\
{ 0x4a0, "override_auto_sel_osc"}, /* Override automatic OSC selection mechanism , */\
{ 0x500, "disable_cgu_sync_cgate"}, /* Clock gating control for CGU synchronisation module, */\
{ 0x510, "force_spkr_clk"}, /* Force active the speaker sub-system clock when in idle power, */\
{ 0x520, "ctrl_bst_clk_lp1"}, /* Boost clock control in low power mode1 , */\
{ 0x5c0, "enbl_faim_ss"}, /* Sub-system FAIM , */\
{ 0x707, "clkchk_th_lo"}, /* Clock check low threshold , */\
{ 0x787, "clkchk_th_hi"}, /* Clock check higher threshold , */\
{ 0x802, "ctrl_on2off_criterion"}, /* Amplifier on-off criteria for shutdown , */\
{ 0xe07, "ctrl_digtoana"}, /* Spare control from digital to analog , */\
{ 0xf0f, "hidden_code"}, /* 5A6Bh, 23147d to access registers (default for engineering), */\
{ 0x1000, "flag_por"}, /* POR , */\
{ 0x1010, "flag_bst_ocpok"}, /* DCDC OCP nmos (sticky register, clear on read) , */\
{ 0x1020, "flag_otpok"}, /* OTP alarm (sticky register, clear on read) , */\
{ 0x1030, "flag_ocp_alarm"}, /* OCP amplifier (sticky register, clear on read) , */\
{ 0x1040, "flag_uvpok"}, /* UVP alarm (sticky register, clear on read) , */\
{ 0x1050, "flag_man_alarm_state"}, /* Alarm state , */\
{ 0x1060, "flag_clocks_stable"}, /* Clocks stable , */\
{ 0x1070, "flag_mtp_busy"}, /* MTP busy , */\
{ 0x1080, "flag_lost_clk"}, /* Lost clock (sticky register, clear on read) , */\
{ 0x10a0, "flag_tdm_error"}, /* TDM error , */\
{ 0x1100, "flag_bst_bstcur"}, /* DCDC current limiting , */\
{ 0x1110, "flag_bst_hiz"}, /* DCDC active (sticky register, clear on read) , */\
{ 0x1120, "flag_bst_peakcur"}, /* Indicates current is max in DC-to-DC converter , */\
{ 0x1130, "flag_bst_voutcomp"}, /* DCDC level 1x , */\
{ 0x1140, "flag_bst_voutcomp86"}, /* DCDC level 1.14x , */\
{ 0x1150, "flag_bst_voutcomp93"}, /* DCDC level 1.07x , */\
{ 0x1160, "flag_pll_lock"}, /* PLL lock , */\
{ 0x1180, "flag_tdm_lut_error"}, /* TDM LUT error , */\
{ 0x11c0, "flag_clk_out_of_range"}, /* External clock status , */\
{ 0x11d0, "flag_engage"}, /* Amplifier engage , */\
{ 0x11e0, "flag_enbl_amp"}, /* Amplifier enable , */\
{ 0x11f0, "flag_enbl_ref"}, /* References enable , */\
{ 0x1300, "flag_ocpokap"}, /* OCPOK pmos A , */\
{ 0x1310, "flag_ocpokan"}, /* OCPOK nmos A , */\
{ 0x1320, "flag_ocpokbp"}, /* OCPOK pmos B , */\
{ 0x1330, "flag_ocpokbn"}, /* OCPOK nmos B , */\
{ 0x1380, "flag_ovpok"}, /* OVP alarm , */\
{ 0x1390, "flag_clip"}, /* Amplifier clipping , */\
{ 0x13a0, "flag_adc10_ready"}, /* Control ADC , */\
{ 0x13c0, "flag_man_wait_src_settings"}, /* Wait HW I2C settings , */\
{ 0x13e0, "flag_man_start_mute_audio"}, /* Audio mute sequence , */\
{ 0x13f0, "flag_man_operating_state"}, /* Operating state , */\
{ 0x1402, "flag_tdm_status"}, /* TDM status bits , */\
{ 0x1433, "man_state"}, /* Device manager status , */\
{ 0x1473, "amp_ctrl_state"}, /* Amplifier control status , */\
{ 0x14b1, "status_bst_mode"}, /* DCDC mode status bits , */\
{ 0x14d0, "flag_waiting_for_sync"}, /* CGU and PLL synchronisation status flag from CGU , */\
{ 0x1509, "bat_adc"}, /* Battery voltage (V) , */\
{ 0x1608, "temp_adc"}, /* IC Temperature (C) , */\
{ 0x1709, "vddp_adc"}, /* IC VDDP voltage ( 1023*VDDP/13 V) , */\
{ 0x2000, "tdm_enable"}, /* Enable interface , */\
{ 0x2013, "tdm_nb_of_slots"}, /* N-slots in Frame , */\
{ 0x2060, "tdm_clk_inversion"}, /* Reception data to BCK clock , */\
{ 0x2073, "tdm_fs_ws_length"}, /* FS length , */\
{ 0x20b0, "tdm_fs_ws_polarity"}, /* FS polarity , */\
{ 0x20c3, "tdm_nbck"}, /* N-BCK's in FS , */\
{ 0x2144, "tdm_slot_length"}, /* N-bits in slot , */\
{ 0x2194, "tdm_bits_remaining"}, /* N-bits remaining , */\
{ 0x21e0, "tdm_data_delay"}, /* Data delay to FS , */\
{ 0x21f0, "tdm_data_adjustment"}, /* Data adjustment , */\
{ 0x2201, "tdm_audio_sample_compression"}, /* Received audio compression , */\
{ 0x2224, "tdm_sample_size"}, /* Sample size per slot , */\
{ 0x2271, "tdm_txdata_format"}, /* Format unused bits , */\
{ 0x2291, "tdm_txdata_format_unused_slot_sd0"}, /* Format unused slots DATAO , */\
{ 0x2300, "tdm_sink0_enable"}, /* Control audio TDM channel in 0 , */\
{ 0x2310, "tdm_sink1_enable"}, /* Control audio TDM channel in 1 , */\
{ 0x2330, "tdm_source0_enable"}, /* current sense vbat temperature and vddp feedback , */\
{ 0x2340, "tdm_source1_enable"}, /* Voltage sense vbat temperature and vddp feedback , */\
{ 0x2603, "tdm_sink0_slot"}, /* TDM slot for sink 0 , */\
{ 0x2643, "tdm_sink1_slot"}, /* TDM slot for sink 1 , */\
{ 0x26c3, "tdm_source0_slot"}, /* Slot Position of current sense vbat temperature and vddp feedback, */\
{ 0x2703, "tdm_source1_slot"}, /* Slot Position of Voltage sense vbat temperature and vddp feedback, */\
{ 0x4000, "int_out_flag_por"}, /* Status POR , */\
{ 0x4010, "int_out_flag_bst_ocpok"}, /* Status DCDC OCP , */\
{ 0x4020, "int_out_flag_otpok"}, /* Status OTP alarm , */\
{ 0x4030, "int_out_flag_ocp_alarm"}, /* Status OCP alarm , */\
{ 0x4040, "int_out_flag_uvpok"}, /* Status UVP alarm , */\
{ 0x4050, "int_out_flag_man_alarm_state"}, /* Status manager alarm state , */\
{ 0x4060, "int_out_flag_tdm_error"}, /* Status TDM error , */\
{ 0x4070, "int_out_flag_lost_clk"}, /* Status lost clock , */\
{ 0x4400, "int_in_flag_por"}, /* Clear POR , */\
{ 0x4410, "int_in_flag_bst_ocpok"}, /* Clear DCDC OCP , */\
{ 0x4420, "int_in_flag_otpok"}, /* Clear OTP alarm , */\
{ 0x4430, "int_in_flag_ocp_alarm"}, /* Clear OCP alarm , */\
{ 0x4440, "int_in_flag_uvpok"}, /* Clear UVP alarm , */\
{ 0x4450, "int_in_flag_man_alarm_state"}, /* Clear manager alarm state , */\
{ 0x4460, "int_in_flag_tdm_error"}, /* Clear TDM error , */\
{ 0x4470, "int_in_flag_lost_clk"}, /* Clear lost clk , */\
{ 0x4800, "int_enable_flag_por"}, /* Enable POR , */\
{ 0x4810, "int_enable_flag_bst_ocpok"}, /* Enable DCDC OCP , */\
{ 0x4820, "int_enable_flag_otpok"}, /* Enable OTP alarm , */\
{ 0x4830, "int_enable_flag_ocp_alarm"}, /* Enable OCP alarm , */\
{ 0x4840, "int_enable_flag_uvpok"}, /* Enable UVP alarm , */\
{ 0x4850, "int_enable_flag_man_alarm_state"}, /* Enable manager alarm state , */\
{ 0x4860, "int_enable_flag_tdm_error"}, /* Enable TDM error , */\
{ 0x4870, "int_enable_flag_lost_clk"}, /* Enable lost clk , */\
{ 0x4c00, "int_polarity_flag_por"}, /* Polarity POR , */\
{ 0x4c10, "int_polarity_flag_bst_ocpok"}, /* Polarity DCDC OCP , */\
{ 0x4c20, "int_polarity_flag_otpok"}, /* Polarity OTP alarm , */\
{ 0x4c30, "int_polarity_flag_ocp_alarm"}, /* Polarity OCP alarm , */\
{ 0x4c40, "int_polarity_flag_uvpok"}, /* Polarity UVP alarm , */\
{ 0x4c50, "int_polarity_flag_man_alarm_state"}, /* Polarity manager alarm state , */\
{ 0x4c60, "int_polarity_flag_tdm_error"}, /* Polarity TDM error , */\
{ 0x4c70, "int_polarity_flag_lost_clk"}, /* Polarity lost clk , */\
{ 0x5001, "vbat_prot_attack_time"}, /* Battery safeguard attack time , */\
{ 0x5023, "vbat_prot_thlevel"}, /* Battery safeguard threshold voltage level , */\
{ 0x5061, "vbat_prot_max_reduct"}, /* Battery safeguard maximum reduction , */\
{ 0x50d0, "rst_min_vbat"}, /* Reset clipper - auto clear , */\
{ 0x50e0, "sel_vbat"}, /* Battery voltage read out , */\
{ 0x50f0, "bypass_clipper"}, /* Bypass battery safeguard , */\
{ 0x5100, "batsense_steepness"}, /* Vbat prot steepness , */\
{ 0x5150, "bypass_hp"}, /* Bypass HPF , */\
{ 0x5170, "enbl_dpsa"}, /* Enable DPSA , */\
{ 0x5240, "bypasshwclip"}, /* Bypass hardware clipper , */\
{ 0x5257, "gain"}, /* Amplifier gain , */\
{ 0x52d0, "ctrl_slopectrl"}, /* Enables slope control , */\
{ 0x52e0, "ctrl_slope"}, /* Slope speed setting (bin. coded) , */\
{ 0x52f0, "bypass_dly_line"}, /* Bypass the interpolator delay line , */\
{ 0x5301, "dpsa_level"}, /* DPSA threshold levels , */\
{ 0x5321, "dpsa_release"}, /* DPSA release time , */\
{ 0x5350, "bypass_lp"}, /* Bypass the low pass filter inside temperature sensor, */\
{ 0x5430, "icomp_engage"}, /* Engage of icomp , */\
{ 0x5440, "ctrl_kickback"}, /* Prevent double pulses of output stage , */\
{ 0x5450, "icomp_engage_overrule"}, /* To overrule the functional icomp_engage signal during validation, */\
{ 0x5463, "ctrl_dem"}, /* Enable DEM icomp and DEM one bit DAC , */\
{ 0x5500, "bypass_ctrlloop"}, /* Switch amplifier into open loop configuration , */\
{ 0x5513, "ctrl_dem_mismatch"}, /* Enable DEM icomp mismatch for testing , */\
{ 0x5552, "dpsa_drive"}, /* Drive setting (binary coded) , */\
{ 0x5581, "ctrlloop_vstress_select"}, /* GO2 capacitor stress selector for control loop , */\
{ 0x5600, "ref_iref_enbl"}, /* Enable of reference current for OCP , */\
{ 0x5631, "ref_irefdist_set_ctrl"}, /* Scaling of reference current for OCP , */\
{ 0x5652, "ref_irefdist_test_enbl"}, /* Enable of test-function of distribution of reference current, used for OCP. When enabled, the current will to to anamux iso powerstages. Using e.g. 011 it will add the current of powerstage P and N., */\
{ 0x570a, "enbl_amp"}, /* Switch on the class-D power sections, each part of the analog sections can be switched on/off individually, */\
{ 0x57b0, "enbl_engage"}, /* Enables/engage the control stage , */\
{ 0x57c0, "enbl_engage_pst"}, /* Enables/engage the power stage , */\
{ 0x5810, "hard_mute"}, /* Hard mute - PWM , */\
{ 0x5844, "pwm_delay"}, /* PWM delay bits to set the delay, clock PWM is 1/(K*2048*fs), */\
{ 0x5890, "reclock_pwm"}, /* Reclock the PWM signal inside analog , */\
{ 0x58c0, "enbl_pwm_phase_shift"}, /* Control for PWM phase shift , */\
{ 0x5900, "sel_pwm_freq"}, /* Control for selection for PWM switching frequency , */\
{ 0x5910, "sel_pwm_delay_src"}, /* Control for selection for PWM delay line source , */\
{ 0x5f63, "ctrl_attr"}, /* Total gain depending on INPLEV setting (channel 0), */\
{ 0x6005, "idle_power_cal_offset"}, /* Idle power mode detector ctrl cal_offset from gain module , */\
{ 0x6065, "idle_power_zero_lvl"}, /* IIdle power mode zero crossing detection level , */\
{ 0x60e1, "idle_power_mode"}, /* Idle power mode control , */\
{ 0x6105, "idle_power_threshold_lvl"}, /* Idle power mode amplitude trigger level , */\
{ 0x6165, "idle_power_hold_time"}, /* Idle power mode detector ctrl hold time before low audio is reckoned to be low audio, */\
{ 0x61c0, "disable_idle_power_mode"}, /* Idle power mode detector control , */\
{ 0x6265, "zero_lvl"}, /* Low noise gain switch zero trigger level , */\
{ 0x62c1, "ctrl_fb_resistor"}, /* Select amplifier feedback resistor connection , */\
{ 0x62e1, "lownoisegain_mode"}, /* Ctrl select mode , */\
{ 0x6305, "threshold_lvl"}, /* Low noise gain switch trigger level , */\
{ 0x6365, "hold_time"}, /* Low noise gain switch ctrl hold time before low audio is reckoned to be low audio, */\
{ 0x6405, "lpm1_cal_offset"}, /* Low power mode1 detector ctrl cal_offset from gain module , */\
{ 0x6465, "lpm1_zero_lvl"}, /* Low power mode1 zero crossing detection level , */\
{ 0x64e1, "lpm1_mode"}, /* Low power mode control , */\
{ 0x6505, "lpm1_threshold_lvl"}, /* Low power mode1 amplitude trigger level , */\
{ 0x6565, "lpm1_hold_time"}, /* Low power mode1 detector ctrl hold time before low audio is reckoned to be low audio, */\
{ 0x65c0, "disable_low_power_mode"}, /* Low power mode1 detector control , */\
{ 0x6611, "dcdc_ctrl_maxzercnt"}, /* DCDC Number of zero current flags to count before going to PFM mode, */\
{ 0x6631, "pfm2pwm_cnt_max"}, /* Number of pulses in PFM mode before going to PWM mode, */\
{ 0x6656, "dcdc_vbat_delta_detect"}, /* Threshold before booster is reacting on a delta Vbat (in PFM mode) by temporarily switching to PWM mode, */\
{ 0x66c0, "dcdc_ignore_vbat"}, /* Ignore an increase on Vbat , */\
{ 0x66d2, "pfmfreq_limit"}, /* Lowest PFM frequency limit , */\
{ 0x6700, "enbl_minion"}, /* Enables minion (small) power stage , */\
{ 0x6713, "vth_vddpvbat"}, /* Select vddp-vbat threshold signal , */\
{ 0x6750, "lpen_vddpvbat"}, /* Select vddp-vbat filtred vs unfiltered compare , */\
{ 0x6761, "ctrl_rfb"}, /* Feedback resistor selection - I2C direct mode , */\
{ 0x6802, "tdm_source_mapping"}, /* TDM source mapping , */\
{ 0x6831, "tdm_sourcea_frame_sel"}, /* Sensed value A , */\
{ 0x6851, "tdm_sourceb_frame_sel"}, /* Sensed value B , */\
{ 0x6871, "tdm_source0_clip_sel"}, /* Clip information (analog /digital) for source0 , */\
{ 0x6891, "tdm_source1_clip_sel"}, /* Clip information (analog /digital) for source1 , */\
{ 0x6a02, "rst_min_vbat_delay"}, /* rst_min_vbat delay (nb fs) , */\
{ 0x6b00, "disable_auto_engage"}, /* Disable auto engange , */\
{ 0x6b10, "disable_engage"}, /* Disable engange , */\
{ 0x6c02, "ns_hp2ln_criterion"}, /* 0..7 zeroes at ns as threshold to swap from high_power to low_noise, */\
{ 0x6c32, "ns_ln2hp_criterion"}, /* 0..7 zeroes at ns as threshold to swap from low_noise to high_power, */\
{ 0x6c69, "spare_out"}, /* spare_out , */\
{ 0x6d0f, "spare_in"}, /* spare_in , */\
{ 0x6e00, "flag_idle_power_mode"}, /* Idle power mode , */\
{ 0x6e10, "flag_lp_detect_mode1"}, /* Low power mode 1 detection , */\
{ 0x6e20, "flag_low_amplitude"}, /* Low amplitude detection , */\
{ 0x6e30, "flag_vddp_gt_vbat"}, /* Vddp greater than Vbat , */\
{ 0x6f02, "cursense_comp_delay"}, /* Delay to allign compensation signal with current sense signal, */\
{ 0x6f40, "cursense_comp_sign"}, /* Polarity of compensation for current sense , */\
{ 0x6f50, "enbl_cursense_comp"}, /* Enable current sense compensation , */\
{ 0x6f72, "pwms_clip_lvl"}, /* Set the amount of pwm pulse that may be skipped before clip-flag is triggered, */\
{ 0x7003, "boost_cur"}, /* Max coil current , */\
{ 0x7041, "bst_slpcmplvl"}, /* Slope compensation current, represents LxF (inductance x frequency) , */\
{ 0x7060, "boost_intel"}, /* Adaptive boost mode , */\
{ 0x7070, "boost_speed"}, /* Soft ramp up/down , */\
{ 0x7085, "overshoot_correction_lvl"}, /* Threshold level to activate active overshoot control, */\
{ 0x70e0, "dcdcoff_mode"}, /* DCDC on/off , */\
{ 0x70f0, "dcdc_pwmonly"}, /* DCDC PWM only mode , */\
{ 0x7104, "bst_drive"}, /* Binary coded drive setting for boost converter power stage, */\
{ 0x7151, "bst_scalecur"}, /* For testing direct control scale current , */\
{ 0x7174, "bst_slopecur"}, /* For testing direct control slope current , */\
{ 0x71c1, "bst_slope"}, /* Boost slope speed , */\
{ 0x71e0, "bst_bypass_bstcur"}, /* Bypass control for boost current settings , */\
{ 0x71f0, "bst_bypass_bstfoldback"}, /* Bypass control for boost foldback , */\
{ 0x7200, "enbl_bst_engage"}, /* Enable power stage dcdc controller , */\
{ 0x7210, "enbl_bst_hizcom"}, /* Enable hiz comparator , */\
{ 0x7220, "enbl_bst_peak2avg"}, /* Enable boost peak2avg functionality , */\
{ 0x7230, "enbl_bst_peakcur"}, /* Enable peak current , */\
{ 0x7240, "enbl_bst_power"}, /* Enable line of the powerstage , */\
{ 0x7250, "enbl_bst_slopecur"}, /* Enable bit of max-current DAC , */\
{ 0x7260, "enbl_bst_voutcomp"}, /* Enable vout comparators , */\
{ 0x7270, "enbl_bst_voutcomp86"}, /* Enable vout-86 comparators , */\
{ 0x7280, "enbl_bst_voutcomp93"}, /* Enable vout-93 comparators , */\
{ 0x7290, "enbl_bst_windac"}, /* Enable window DAC , */\
{ 0x72a5, "bst_windac"}, /* For testing direct control windac , */\
{ 0x7300, "boost_alg"}, /* Control for boost adaptive loop gain , */\
{ 0x7311, "boost_loopgain"}, /* DCDC boost loopgain setting , */\
{ 0x7331, "bst_freq"}, /* DCDC boost frequency control , */\
{ 0x7350, "disable_artf654484_fix"}, /* Disables the fix for artf654484 (loss of efficiency when Vbst is close to Vbat), */\
{ 0x7420, "disable_dynamic_freq"}, /* Disables the dynamic frequency switching due to flag_voutcomp86/93, */\
{ 0x7430, "boost_track"}, /* Boost algorithm selection, effective only when boost_intelligent is set to 1, */\
{ 0x7444, "boost_trip_lvl_1st"}, /* 1st Adaptive boost trip levels, effective only when DCIE is set to 1, */\
{ 0x7494, "boost_hold_time"}, /* Hold time for DCDC booster, effective only when boost_intelligent is set to 1, */\
{ 0x74e0, "sel_dcdc_envelope_8fs"}, /* Selection of data for adaptive boost algorithm, effective only when boost_intelligent is set to 1, */\
{ 0x74f0, "ignore_flag_voutcomp86"}, /* Determines the maximum PWM frequency be the most efficient in relation to the Booster inductor value, */\
{ 0x7534, "boost_trip_lvl_2nd"}, /* 2nd Adaptive boost trip levels, effective only when DCIE is set to 1, */\
{ 0x7584, "boost_trip_lvl_track"}, /* Track Adaptive boost trip levels, effective only when boost_intelligent is set to 1, */\
{ 0x75f0, "enbl_trip_hyst"}, /* Enable hysteresis on booster trip levels , */\
{ 0x7620, "enbl_bst_filter"}, /* Enable the boost filter , */\
{ 0x7635, "frst_boost_voltage"}, /* First boost voltage level , */\
{ 0x7695, "scnd_boost_voltage"}, /* Second boost voltage level , */\
{ 0x8050, "cs_gain_control"}, /* Current sense gain control , */\
{ 0x8060, "cs_bypass_gc"}, /* Bypasses the CS gain correction , */\
{ 0x8087, "cs_gain"}, /* Current sense gain , */\
{ 0x8210, "invertpwm"}, /* Current sense common mode feedback pwm invert control, */\
{ 0x8305, "cs_ktemp"}, /* Current sense temperature compensation trimming (1 - VALUE*TEMP)*signal, */\
{ 0x8364, "cs_ktemp2"}, /* Second order temperature compensation coefficient , */\
{ 0x8400, "cs_adc_bsoinv"}, /* Bitstream inversion for current sense ADC , */\
{ 0x8440, "cs_adc_nortz"}, /* Return to zero for current sense ADC , */\
{ 0x8490, "cs_adc_slowdel"}, /* Select delay for current sense ADC (internal decision circuitry), */\
{ 0x8510, "cs_classd_tran_skip"}, /* Skip current sense connection during a classD amplifier transition, */\
{ 0x8530, "cs_inn_short"}, /* Short current sense negative to common mode , */\
{ 0x8540, "cs_inp_short"}, /* Short current sense positive to common mode , */\
{ 0x8550, "cs_ldo_bypass"}, /* Bypass current sense LDO , */\
{ 0x8560, "cs_ldo_pulldown"}, /* Pull down current sense LDO, only valid if left_enbl_cs_ldo is high, */\
{ 0x8574, "cs_ldo_voset"}, /* Current sense LDO voltage level setting (two's complement), */\
{ 0x8700, "enbl_cs_adc"}, /* Enable current sense ADC , */\
{ 0x8710, "enbl_cs_inn1"}, /* Enable connection of current sense negative1 , */\
{ 0x8720, "enbl_cs_inn2"}, /* Enable connection of current sense negative2 , */\
{ 0x8730, "enbl_cs_inp1"}, /* Enable connection of current sense positive1 , */\
{ 0x8740, "enbl_cs_inp2"}, /* Enable connection of current sense positive2 , */\
{ 0x8750, "enbl_cs_ldo"}, /* Enable current sense LDO , */\
{ 0x8780, "enbl_cs_vbatldo"}, /* Enable of current sense LDO , */\
{ 0x8790, "enbl_dc_filter"}, /* Control for enabling the DC blocking filter for voltage and current sense, */\
{ 0x8850, "vs_gain_control"}, /* Voltage sense gain control , */\
{ 0x8860, "vs_bypass_gc"}, /* Bypasses the VS gain correction , */\
{ 0x8887, "vs_gain"}, /* Voltage sense gain , */\
{ 0x8c00, "vs_adc_bsoinv"}, /* Bitstream inversion for voltage sense ADC , */\
{ 0x8c40, "vs_adc_nortz"}, /* Return to zero for voltage sense ADC , */\
{ 0x8c90, "vs_adc_slowdel"}, /* Select delay for voltage sense ADC (internal decision circuitry), */\
{ 0x8d30, "vs_inn_short"}, /* Short voltage sense negative to common mode , */\
{ 0x8d40, "vs_inp_short"}, /* Short voltage sense positive to common mode , */\
{ 0x8d50, "vs_ldo_bypass"}, /* Bypass voltage sense LDO , */\
{ 0x8d60, "vs_ldo_pulldown"}, /* Pull down voltage sense LDO, only valid if left_enbl_cs_ldo is high, */\
{ 0x8d74, "vs_ldo_voset"}, /* Voltage sense LDO voltage level setting (two's complement), */\
{ 0x8f00, "enbl_vs_adc"}, /* Enable voltage sense ADC (Direct Control only only others done by manager), */\
{ 0x8f10, "enbl_vs_inn1"}, /* Enable connection of voltage sense negative1 , */\
{ 0x8f20, "enbl_vs_inn2"}, /* Enable connection of voltage sense negative2 , */\
{ 0x8f30, "enbl_vs_inp1"}, /* Enable connection of voltage sense positive1 , */\
{ 0x8f40, "enbl_vs_inp2"}, /* Enable connection of voltage sense positive2 , */\
{ 0x8f50, "enbl_vs_ldo"}, /* Enable voltage sense LDO (Direct Control only only others done by manager), */\
{ 0x8f80, "enbl_vs_vbatldo"}, /* Enable of voltage sense LDO (Direct Control only others done by manager), */\
{ 0xa007, "mtpkey1"}, /* 5Ah, 90d To access KEY1_protected registers (default for engineering), */\
{ 0xa107, "mtpkey2"}, /* MTP KEY2 register , */\
{ 0xa200, "key01_locked"}, /* Indicates KEY1 is locked , */\
{ 0xa210, "key02_locked"}, /* Indicates KEY2 is locked , */\
{ 0xa302, "mtp_man_address_in"}, /* MTP address from I2C register for read/writing mtp in manual single word mode, */\
{ 0xa330, "man_copy_mtp_to_iic"}, /* Start copying single word from mtp to I2C mtp register, */\
{ 0xa340, "man_copy_iic_to_mtp"}, /* Start copying single word from I2C mtp register to mtp, */\
{ 0xa350, "auto_copy_mtp_to_iic"}, /* Start copying all the data from mtp to I2C mtp registers, */\
{ 0xa360, "auto_copy_iic_to_mtp"}, /* Start copying data from I2C mtp registers to mtp , */\
{ 0xa400, "faim_set_clkws"}, /* Sets the faim controller clock wait state register, */\
{ 0xa410, "faim_sel_evenrows"}, /* All even rows of the faim are selected, active high, */\
{ 0xa420, "faim_sel_oddrows"}, /* All odd rows of the faim are selected, all rows in combination with sel_evenrows, */\
{ 0xa430, "faim_program_only"}, /* Skip the erase access at wr_faim command (write-program-marginread), */\
{ 0xa440, "faim_erase_only"}, /* Skip the program access at wr_faim command (write-erase-marginread), */\
{ 0xa50f, "mtp_man_data_out_msb"}, /* MSB word of MTP manual read data , */\
{ 0xa60f, "mtp_man_data_out_lsb"}, /* LSB word of MTP manual read data , */\
{ 0xa70f, "mtp_man_data_in_msb"}, /* MSB word of write data for MTP manual write , */\
{ 0xa80f, "mtp_man_data_in_lsb"}, /* LSB word of write data for MTP manual write , */\
{ 0xb010, "bypass_ocpcounter"}, /* Bypass OCP Counter , */\
{ 0xb020, "bypass_glitchfilter"}, /* Bypass glitch filter , */\
{ 0xb030, "bypass_ovp"}, /* Bypass OVP , */\
{ 0xb040, "bypass_uvp"}, /* Bypass UVP , */\
{ 0xb050, "bypass_otp"}, /* Bypass OTP , */\
{ 0xb060, "bypass_lost_clk"}, /* Bypass lost clock detector , */\
{ 0xb070, "ctrl_vpalarm"}, /* vpalarm (uvp ovp handling) , */\
{ 0xb087, "ocp_threshold"}, /* OCP threshold level , */\
{ 0xb108, "ext_temp"}, /* External temperature (C) , */\
{ 0xb190, "ext_temp_sel"}, /* Select temp Speaker calibration , */\
{ 0xb200, "bypass_ovpglitchfilter"}, /* Bypass glitch filter on over voltage protection signal from analog, */\
{ 0xb210, "enbl_ovp_alarm_state"}, /* Allow manager to go into alarm state when OVP (only when ctrl_vpalarm is 0), */\
{ 0xb220, "amp_in_tristate_when_ovp"}, /* Brings amplifier in tristate when OVP (only when ctrl_enbl_ovp_alarm_state is 0) , */\
{ 0xc000, "use_direct_ctrls"}, /* Direct control to overrule several functions for testing, */\
{ 0xc010, "rst_datapath"}, /* Direct control for datapath reset , */\
{ 0xc020, "rst_cgu"}, /* Direct control for cgu reset , */\
{ 0xc038, "enbl_ref"}, /* Switch on the analog references, each part of the references can be switched on/off individually, */\
{ 0xc0c0, "use_direct_vs_ctrls"}, /* Voltage sense direct control to overrule several functions for testing, */\
{ 0xc0d0, "enbl_ringo"}, /* Enable the ring oscillator for test purpose , */\
{ 0xc0e0, "enbl_pll"}, /* Enables PLL in I2C direct control mode only , */\
{ 0xc0f0, "enbl_fro"}, /* Enables FRO8M in I2C direct control mode only , */\
{ 0xc100, "enbl_tsense"}, /* Temperature sensor enable control - I2C direct mode, */\
{ 0xc110, "tsense_hibias"}, /* Bit to set the biasing in temp sensor to high , */\
{ 0xc120, "enbl_flag_vbg"}, /* Enable flagging of bandgap out of control , */\
{ 0xc20f, "abist_offset"}, /* Offset control for ABIST testing (two's complement), */\
{ 0xc300, "bypasslatch"}, /* Bypass latch , */\
{ 0xc311, "sourcea"}, /* Set OUTA to , */\
{ 0xc331, "sourceb"}, /* Set OUTB to , */\
{ 0xc350, "inverta"}, /* Invert pwma test signal , */\
{ 0xc360, "invertb"}, /* Invert pwmb test signal , */\
{ 0xc376, "pulselength"}, /* Pulse length setting test input for amplifier (PWM clock 2048/4096 Fs), */\
{ 0xc3e0, "tdm_enable_loopback"}, /* TDM loopback test , */\
{ 0xc400, "bst_bypasslatch"}, /* Bypass latch in boost converter , */\
{ 0xc411, "bst_source"}, /* Sets the source of the pwmbst output to boost converter input for testing, */\
{ 0xc430, "bst_invertb"}, /* Invert PWMbst test signal , */\
{ 0xc444, "bst_pulselength"}, /* Pulse length setting test input for boost converter , */\
{ 0xc490, "test_bst_ctrlsthv"}, /* Test mode for boost control stage , */\
{ 0xc4a0, "test_bst_iddq"}, /* IDDQ testing in power stage of boost converter , */\
{ 0xc4b0, "test_bst_rdson"}, /* RDSON testing - boost power stage , */\
{ 0xc4c0, "test_bst_cvi"}, /* CVI testing - boost power stage , */\
{ 0xc4d0, "test_bst_ocp"}, /* Boost OCP. For old OCP (ctrl_reversebst is 0), For new OCP (ctrl_reversebst is 1), */\
{ 0xc4e0, "test_bst_sense"}, /* Test option for the sense NMOS in booster for current mode control., */\
{ 0xc500, "test_cvi"}, /* Analog BIST, switch choose which transistor will be used as current source (also cross coupled sources possible), */\
{ 0xc510, "test_discrete"}, /* Test function noise measurement , */\
{ 0xc520, "test_iddq"}, /* Set the power stages in iddq mode for gate stress., */\
{ 0xc540, "test_rdson"}, /* Analog BIST, switch to enable Rdson measurement , */\
{ 0xc550, "test_sdelta"}, /* Analog BIST, noise test , */\
{ 0xc570, "test_enbl_cs"}, /* Enable for digimux mode of current sense , */\
{ 0xc580, "test_enbl_vs"}, /* Enable for digimux mode of voltage sense , */\
{ 0xc600, "enbl_pwm_dcc"}, /* Enables direct control of pwm duty cycle for DCDC power stage, */\
{ 0xc613, "pwm_dcc_cnt"}, /* Control pwm duty cycle when enbl_pwm_dcc is 1 , */\
{ 0xc650, "enbl_ldo_stress"}, /* Enable stress of internal supply voltages powerstages, */\
{ 0xc707, "digimuxa_sel"}, /* DigimuxA input selection control routed to DATAO (see Digimux list for details), */\
{ 0xc787, "digimuxb_sel"}, /* DigimuxB input selection control routed to INT (see Digimux list for details), */\
{ 0xc807, "digimuxc_sel"}, /* DigimuxC input selection control routed to ADS1 (see Digimux list for details), */\
{ 0xc981, "int_ehs"}, /* Speed/load setting for INT IO cell, clk or data mode range (see SLIMMF IO cell datasheet), */\
{ 0xc9c0, "hs_mode"}, /* I2C high speed mode control , */\
{ 0xca00, "enbl_anamux1"}, /* Enable anamux1 , */\
{ 0xca10, "enbl_anamux2"}, /* Enable anamux2 , */\
{ 0xca20, "enbl_anamux3"}, /* Enable anamux3 , */\
{ 0xca30, "enbl_anamux4"}, /* Enable anamux4 , */\
{ 0xca74, "anamux1"}, /* Anamux selection control - anamux on TEST1 , */\
{ 0xcb04, "anamux2"}, /* Anamux selection control - anamux on TEST2 , */\
{ 0xcb53, "anamux3"}, /* Anamux selection control - anamux on VSN/TEST3 , */\
{ 0xcba3, "anamux4"}, /* Anamux selection control - anamux on VSP/TEST4 , */\
{ 0xcd05, "pll_inseli"}, /* PLL INSELI - PLL direct bandwidth control mode, only with pll_bandsel set to 1, */\
{ 0xcd64, "pll_inselp"}, /* PLL INSELP - PLL direct bandwidth control mode only with pll_bandsel set to 1, */\
{ 0xcdb3, "pll_inselr"}, /* PLL INSELR - PLL direct bandwidth control mode only with pll_bandsel set to 1, */\
{ 0xcdf0, "pll_bandsel"}, /* PLL bandwidth selection control, USE WITH CAUTION , */\
{ 0xce09, "pll_ndec"}, /* PLL NDEC in direct control mode only, use_direct_pll_ctrl set to 1, */\
{ 0xcea0, "pll_mdec_msb"}, /* MSB of PLL MDEC in direct control mode only, use_direct_pll_ctrl set to 1, */\
{ 0xceb0, "pll_bypass"}, /* PLL bypass control during functional mode , */\
{ 0xcec0, "pll_directi"}, /* PLL directi control in direct control mode only, use_direct_pll_ctrl set to 1, */\
{ 0xced0, "pll_directo"}, /* PLL directo control in direct control mode only, use_direct_pll_ctrl set to 1, */\
{ 0xcee0, "pll_frm_clockstable"}, /* PLL FRM clock stable control in direct control mode only, use_direct_pll_ctrl set to 1, */\
{ 0xcef0, "pll_frm"}, /* PLL free running mode control in functional mode , */\
{ 0xcf0f, "pll_mdec_lsb"}, /* Bits 15 to 0 of PLL MDEC in direct control mode, use_direct_pll_ctrl set to 1, */\
{ 0xd006, "pll_pdec"}, /* PLL PDEC in direct control mode only, use_direct_pll_ctrl set to 1, */\
{ 0xd070, "use_direct_pll_ctrl"}, /* Enabled PLL direct control mode, overrules the PLL LUT with I2C register values, */\
{ 0xd090, "pll_limup_off"}, /* PLL up limiter control in PLL direct bandwidth control mode, pll_bandsel set to 1, */\
{ 0xd0a2, "sel_pll_startup_time"}, /* PLL startup time selection control , */\
{ 0xd10f, "tsig_freq_lsb"}, /* Internal sinus test generator frequency control , */\
{ 0xd202, "tsig_freq_msb"}, /* Internal sinus test generator, frequency control msb bits, */\
{ 0xd230, "inject_tsig"}, /* Control bit to switch to internal sinus test generator, */\
{ 0xd283, "tsig_gain"}, /* Test signal gain , */\
{ 0xd300, "adc10_reset"}, /* Reset for ADC10 - I2C direct control mode , */\
{ 0xd311, "adc10_test"}, /* Test mode selection signal for ADC10 - I2C direct control mode, */\
{ 0xd332, "adc10_sel"}, /* Select the input to convert for ADC10 - I2C direct control mode, */\
{ 0xd364, "adc10_prog_sample"}, /* ADC10 program sample setting - I2C direct control mode, */\
{ 0xd3b0, "adc10_enbl"}, /* Enable ADC10 - I2C direct control mode , */\
{ 0xd3c0, "bypass_lp_vbat"}, /* Bypass control for Low pass filter in batt sensor , */\
{ 0xd409, "data_adc10_tempbat"}, /* ADC 10 data output data for testing , */\
{ 0xd507, "ctrl_digtoana_hidden"}, /* Spare digital to analog control bits - Hidden , */\
{ 0xd580, "enbl_clk_out_of_range"}, /* Clock out of range , */\
{ 0xd721, "datao_ehs"}, /* Speed/load setting for DATAO IO cell, clk or data mode range (see SLIMMF IO cell datasheet), */\
{ 0xd740, "bck_ehs"}, /* High-speed and standard/fast mode selection for BCK IO cell (see IIC3V3 IO cell datasheet), */\
{ 0xd750, "datai_ehs"}, /* High-speed and standard/fast mode selection for DATAI IO cell (see IIC3V3 IO cell datasheet), */\
{ 0xd800, "source_in_testmode"}, /* TDM source in test mode (return only current and voltage sense), */\
{ 0xd810, "gainatt_tdm_feedback"}, /* GainAtt feedback to TDM , */\
{ 0xd822, "test_parametric_io"}, /* Test io parametric , */\
{ 0xd861, "test_spare_out1"}, /* Test spare out 1 , */\
{ 0xd880, "bst_dcmbst"}, /* DCM boost , */\
{ 0xd890, "railclamp_disable"}, /* ESD rail clamp control, controls amp and boost rail clamp for ESD, */\
{ 0xd8c3, "test_spare_out2"}, /* Test spare out 1 , */\
{ 0xd900, "enbl_frocal"}, /* Enable FRO calibration , */\
{ 0xd910, "start_fro_calibration"}, /* Start FRO8 Calibration , */\
{ 0xd920, "enbl_irefcal"}, /* Enable IREF calibration , */\
{ 0xd930, "start_iref_calibration"}, /* Start IREF Calibration , */\
{ 0xda00, "fro_calibration_done"}, /* FRO8 Calibration done - Read Only , */\
{ 0xda15, "fro_auto_trim_val"}, /* Calibration value from auto calibration, to be written into MTP - Read Only, */\
{ 0xda80, "iref_calibration_done"}, /* IREF Calibration done - Read Only , */\
{ 0xda94, "iref_auto_trim_val"}, /* Calibration value from auto calibration, to be written into MTP - Read Only, */\
{ 0xdae0, "iref_calibration_error"}, /* IREF Calibration done - Read Only , */\
{ 0xe00f, "sw_profile"}, /* Software profile data , */\
{ 0xe10f, "sw_vstep"}, /* Software vstep information , */\
{ 0xf000, "calibration_onetime"}, /* Calibration schedule , */\
{ 0xf010, "calibr_ron_done"}, /* Calibration Ron executed , */\
{ 0xf020, "calibr_dcdc_api_calibrate"}, /* Calibration current limit DCDC , */\
{ 0xf030, "calibr_dcdc_delta_sign"}, /* Sign bit for delta calibration current limit DCDC , */\
{ 0xf042, "calibr_dcdc_delta"}, /* Calibration delta current limit DCDC , */\
{ 0xf078, "calibr_speaker_info"}, /* Reserved space for allowing customer to store speaker information, */\
{ 0xf105, "calibr_vout_offset"}, /* DCDC offset calibration 2's complement (key1 protected), */\
{ 0xf203, "calibr_gain"}, /* HW gain module (2's complement) , */\
{ 0xf245, "calibr_offset"}, /* Offset for amplifier, HW gain module (2's complement), */\
{ 0xf307, "calibr_gain_vs1"}, /* Voltage sense gain when external voltage sensing input is selected, */\
{ 0xf387, "calibr_gain_vs2"}, /* Voltage sense gain when internal voltage sensing input is selected, */\
{ 0xf407, "vs_trim1"}, /* VS Trimming when external voltage sensing input is selected, */\
{ 0xf487, "vs_trim2"}, /* VS Trimming when internal voltage sensing input is selected, */\
{ 0xf50f, "calibr_R25C_R"}, /* Ron resistance of speaker coil , */\
{ 0xf607, "calibr_gain_cs"}, /* Current sense gain (signed two's complement format), */\
{ 0xf706, "ctrl_offset_a"}, /* Offset of level shifter A , */\
{ 0xf786, "ctrl_offset_b"}, /* Offset of amplifier level shifter B , */\
{ 0xf806, "htol_iic_addr"}, /* 7-bit I2C address to be used during HTOL testing , */\
{ 0xf870, "htol_iic_addr_en"}, /* HTOL I2C address enable control , */\
{ 0xf884, "calibr_temp_offset"}, /* Temperature offset 2's compliment (key1 protected), */\
{ 0xf8d2, "calibr_temp_gain"}, /* Temperature gain 2's compliment (key1 protected) , */\
{ 0xf900, "mtp_lock_dcdcoff_mode"}, /* Disable function dcdcoff_mode , */\
{ 0xf920, "mtp_lock_bypass_clipper"}, /* Disable function bypass_clipper , */\
{ 0xf930, "mtp_lock_max_dcdc_voltage"}, /* Force Boost in follower mode , */\
{ 0xf943, "calibr_vbg_trim"}, /* Bandgap trimming control , */\
{ 0xf990, "mtp_enbl_pwm_delay_clock_gating"}, /* PWM delay clock auto gating , */\
{ 0xf9a0, "mtp_enbl_ocp_clock_gating"}, /* OCP clock auto gating , */\
{ 0xfa0f, "mtpdataA"}, /* MTPdataA (key1 protected) , */\
{ 0xfb0f, "mtpdataB"}, /* MTPdataB (key1 protected) , */\
{ 0xfc0f, "mtpdataC"}, /* MTPdataC (key1 protected) , */\
{ 0xfd0f, "mtpdataD"}, /* MTPdataD (key1 protected) , */\
{ 0xfe0f, "mtpdataE"}, /* MTPdataE (key1 protected) , */\
{ 0xff05, "fro_trim"}, /* 8 MHz oscillator trim code , */\
{ 0xff61, "fro_shortnwell"}, /* Short 4 or 6 n-well resistors , */\
{ 0xff81, "fro_boost"}, /* Self bias current selection , */\
{ 0xffa4, "calibr_iref_trim"}, /* Trimming control of reference current for OCP , */\
{ 0xffff,"Unknown bitfield enum" } /* not found */\
};
enum tfa9873_irq {
tfa9873_irq_stvdds = 0,
tfa9873_irq_stbstoc = 1,
tfa9873_irq_stotds = 2,
tfa9873_irq_stocpr = 3,
tfa9873_irq_stuvds = 4,
tfa9873_irq_stmanalarm = 5,
tfa9873_irq_sttdmer = 6,
tfa9873_irq_stnoclk = 7,
tfa9873_irq_max = 8,
tfa9873_irq_all = -1 /* all irqs */};
#define TFA9873_IRQ_NAMETABLE static tfaIrqName_t Tfa9873IrqNames[]= {\
{ 0, "STVDDS"},\
{ 1, "STBSTOC"},\
{ 2, "STOTDS"},\
{ 3, "STOCPR"},\
{ 4, "STUVDS"},\
{ 5, "STMANALARM"},\
{ 6, "STTDMER"},\
{ 7, "STNOCLK"},\
{ 8, "8"},\
};
#endif /* _TFA9873_TFAFIELDNAMES_H */

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/*
* Copyright (C) 2014-2020 NXP Semiconductors, All Rights Reserved.
* Copyright 2020 GOODIX
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
*/
#ifndef _TFA9873_TFAFIELDNAMES_B0_H
#define _TFA9873_TFAFIELDNAMES_B0_H
#define TFA9873B0_I2CVERSION 13
typedef enum Tfa9873B0BfEnumList {
TFA9873B0_BF_PWDN = 0x0000, /*!< Powerdown selection */
TFA9873B0_BF_I2CR = 0x0010, /*!< I2C reset - auto clear */
TFA9873B0_BF_AMPE = 0x0030, /*!< Activate amplifier */
TFA9873B0_BF_DCA = 0x0040, /*!< Activate DC-to-DC converter */
TFA9873B0_BF_INTP = 0x0071, /*!< Interrupt config */
TFA9873B0_BF_FSSSEL= 0x0090, /*!< Audio sample reference */
TFA9873B0_BF_BYPOCP= 0x00b0, /*!< Bypass OCP */
TFA9873B0_BF_TSTOCP= 0x00c0, /*!< OCP testing control */
TFA9873B0_BF_ENPLLSYNC= 0x00e0, /*!< Manager control for enabling synchronisation with PLL FS */
TFA9873B0_BF_AMPINSEL= 0x0101, /*!< Amplifier input selection */
TFA9873B0_BF_MANSCONF= 0x0120, /*!< I2C configured */
TFA9873B0_BF_MUTETO= 0x0160, /*!< Time out SB mute sequence */
TFA9873B0_BF_OPENMTP= 0x01e0, /*!< Control for FAIM protection */
TFA9873B0_BF_DISFCRBST= 0x01f0, /*!< Disable boost control with FRCBST */
TFA9873B0_BF_AUDFS = 0x0203, /*!< Sample rate (fs) */
TFA9873B0_BF_INPLEV= 0x0240, /*!< TDM output attenuation */
TFA9873B0_BF_FRACTDEL= 0x0255, /*!< V/I Fractional delay */
TFA9873B0_BF_REV = 0x030f, /*!< Device revision information */
TFA9873B0_BF_REFCKEXT= 0x0401, /*!< PLL external ref clock */
TFA9873B0_BF_REFCKSEL= 0x0420, /*!< PLL internal ref clock */
TFA9873B0_BF_MANAOOSC= 0x0460, /*!< Internal osc off in power down mode */
TFA9873B0_BF_FSSYNCEN= 0x0480, /*!< Enable FS synchronisation for clock divider */
TFA9873B0_BF_CLKREFSYNCEN= 0x0490, /*!< Enable PLL reference clock synchronisation for clock divider */
TFA9873B0_BF_AUTOFROSEL= 0x04a0, /*!< Override automatic OSC selection mechanism */
TFA9873B0_BF_CGUSYNCDCG= 0x0500, /*!< Clock gating control for CGU synchronisation module */
TFA9873B0_BF_FRCCLKSPKR= 0x0510, /*!< Force active the speaker sub-system clock when in idle power */
TFA9873B0_BF_BSTCLKLP= 0x0520, /*!< Boost clock control in low power mode1 */
TFA9873B0_BF_SSFAIME= 0x05c0, /*!< Sub-system FAIM */
TFA9873B0_BF_CLKCHKLO= 0x0707, /*!< Clock check low threshold */
TFA9873B0_BF_CLKCHKHI= 0x0787, /*!< Clock check higher threshold */
TFA9873B0_BF_AMPOCRT= 0x0802, /*!< Amplifier on-off criteria for shutdown */
TFA9873B0_BF_VDDS = 0x1000, /*!< POR */
TFA9873B0_BF_DCOCPOK= 0x1010, /*!< DCDC OCP nmos (sticky register, clear on read) */
TFA9873B0_BF_OTDS = 0x1020, /*!< OTP alarm (sticky register, clear on read) */
TFA9873B0_BF_OCDS = 0x1030, /*!< OCP amplifier (sticky register, clear on read) */
TFA9873B0_BF_UVDS = 0x1040, /*!< UVP alarm (sticky register, clear on read) */
TFA9873B0_BF_MANALARM= 0x1050, /*!< Alarm state */
TFA9873B0_BF_CLKS = 0x1060, /*!< Clocks stable */
TFA9873B0_BF_MTPB = 0x1070, /*!< MTP busy */
TFA9873B0_BF_NOCLK = 0x1080, /*!< Lost clock (sticky register, clear on read) */
TFA9873B0_BF_TDMERR= 0x10a0, /*!< TDM error */
TFA9873B0_BF_DCIL = 0x1100, /*!< DCDC current limiting */
TFA9873B0_BF_DCDCA = 0x1110, /*!< DCDC active (sticky register, clear on read) */
TFA9873B0_BF_DCDCPC= 0x1120, /*!< Indicates current is max in DC-to-DC converter */
TFA9873B0_BF_DCHVBAT= 0x1130, /*!< DCDC level 1x */
TFA9873B0_BF_DCH114= 0x1140, /*!< DCDC level 1.14x */
TFA9873B0_BF_DCH107= 0x1150, /*!< DCDC level 1.07x */
TFA9873B0_BF_PLLS = 0x1160, /*!< PLL lock */
TFA9873B0_BF_TDMLUTER= 0x1180, /*!< TDM LUT error */
TFA9873B0_BF_CLKOOR= 0x11c0, /*!< External clock status */
TFA9873B0_BF_SWS = 0x11d0, /*!< Amplifier engage */
TFA9873B0_BF_AMPS = 0x11e0, /*!< Amplifier enable */
TFA9873B0_BF_AREFS = 0x11f0, /*!< References enable */
TFA9873B0_BF_OCPOAP= 0x1300, /*!< OCPOK pmos A */
TFA9873B0_BF_OCPOAN= 0x1310, /*!< OCPOK nmos A */
TFA9873B0_BF_OCPOBP= 0x1320, /*!< OCPOK pmos B */
TFA9873B0_BF_OCPOBN= 0x1330, /*!< OCPOK nmos B */
TFA9873B0_BF_OVDS = 0x1380, /*!< OVP alarm */
TFA9873B0_BF_CLIPS = 0x1390, /*!< Amplifier clipping */
TFA9873B0_BF_ADCCR = 0x13a0, /*!< Control ADC */
TFA9873B0_BF_MANWAIT1= 0x13c0, /*!< Wait HW I2C settings */
TFA9873B0_BF_MANMUTE= 0x13e0, /*!< Audio mute sequence */
TFA9873B0_BF_MANOPER= 0x13f0, /*!< Operating state */
TFA9873B0_BF_TDMSTAT= 0x1402, /*!< TDM status bits */
TFA9873B0_BF_MANSTATE= 0x1433, /*!< Device manager status */
TFA9873B0_BF_AMPSTE= 0x1473, /*!< Amplifier control status */
TFA9873B0_BF_DCMODE= 0x14b1, /*!< DCDC mode status bits */
TFA9873B0_BF_WAITSYNC= 0x14d0, /*!< CGU and PLL synchronisation status flag from CGU */
TFA9873B0_BF_BATS = 0x1509, /*!< Battery voltage (V) */
TFA9873B0_BF_TEMPS = 0x1608, /*!< IC Temperature (C) */
TFA9873B0_BF_VDDPS = 0x1709, /*!< IC VDDP voltage ( 1023*VDDP/13 V) */
TFA9873B0_BF_TDME = 0x2000, /*!< Enable interface */
TFA9873B0_BF_TDMSLOTS= 0x2013, /*!< N-slots in Frame */
TFA9873B0_BF_TDMCLINV= 0x2060, /*!< Reception data to BCK clock */
TFA9873B0_BF_TDMFSLN= 0x2073, /*!< FS length */
TFA9873B0_BF_TDMFSPOL= 0x20b0, /*!< FS polarity */
TFA9873B0_BF_TDMNBCK= 0x20c3, /*!< N-BCK's in FS */
TFA9873B0_BF_TDMSLLN= 0x2144, /*!< N-bits in slot */
TFA9873B0_BF_TDMBRMG= 0x2194, /*!< N-bits remaining */
TFA9873B0_BF_TDMDEL= 0x21e0, /*!< Data delay to FS */
TFA9873B0_BF_TDMADJ= 0x21f0, /*!< Data adjustment */
TFA9873B0_BF_TDMOOMP= 0x2201, /*!< Received audio compression */
TFA9873B0_BF_TDMSSIZE= 0x2224, /*!< Sample size per slot */
TFA9873B0_BF_TDMTXDFO= 0x2271, /*!< Format unused bits */
TFA9873B0_BF_TDMTXUS0= 0x2291, /*!< Format unused slots DATAO */
TFA9873B0_BF_TDMSPKE= 0x2300, /*!< Control audio TDM channel in 0 */
TFA9873B0_BF_TDMDCE= 0x2310, /*!< Control audio TDM channel in 1 */
TFA9873B0_BF_TDMCSE= 0x2330, /*!< current sense vbat temperature and vddp feedback */
TFA9873B0_BF_TDMVSE= 0x2340, /*!< Voltage sense vbat temperature and vddp feedback */
TFA9873B0_BF_TDMSPKS= 0x2603, /*!< TDM slot for sink 0 */
TFA9873B0_BF_TDMDCS= 0x2643, /*!< TDM slot for sink 1 */
TFA9873B0_BF_TDMCSS= 0x26c3, /*!< Slot Position of current sense vbat temperature and vddp feedback */
TFA9873B0_BF_TDMVSS= 0x2703, /*!< Slot Position of Voltage sense vbat temperature and vddp feedback */
TFA9873B0_BF_ISTVDDS= 0x4000, /*!< Status POR */
TFA9873B0_BF_ISTBSTOC= 0x4010, /*!< Status DCDC OCP */
TFA9873B0_BF_ISTOTDS= 0x4020, /*!< Status OTP alarm */
TFA9873B0_BF_ISTOCPR= 0x4030, /*!< Status OCP alarm */
TFA9873B0_BF_ISTUVDS= 0x4040, /*!< Status UVP alarm */
TFA9873B0_BF_ISTMANALARM= 0x4050, /*!< Status manager alarm state */
TFA9873B0_BF_ISTTDMER= 0x4060, /*!< Status TDM error */
TFA9873B0_BF_ISTNOCLK= 0x4070, /*!< Status lost clock */
TFA9873B0_BF_ICLVDDS= 0x4400, /*!< Clear POR */
TFA9873B0_BF_ICLBSTOC= 0x4410, /*!< Clear DCDC OCP */
TFA9873B0_BF_ICLOTDS= 0x4420, /*!< Clear OTP alarm */
TFA9873B0_BF_ICLOCPR= 0x4430, /*!< Clear OCP alarm */
TFA9873B0_BF_ICLUVDS= 0x4440, /*!< Clear UVP alarm */
TFA9873B0_BF_ICLMANALARM= 0x4450, /*!< Clear manager alarm state */
TFA9873B0_BF_ICLTDMER= 0x4460, /*!< Clear TDM error */
TFA9873B0_BF_ICLNOCLK= 0x4470, /*!< Clear lost clk */
TFA9873B0_BF_IEVDDS= 0x4800, /*!< Enable POR */
TFA9873B0_BF_IEBSTOC= 0x4810, /*!< Enable DCDC OCP */
TFA9873B0_BF_IEOTDS= 0x4820, /*!< Enable OTP alarm */
TFA9873B0_BF_IEOCPR= 0x4830, /*!< Enable OCP alarm */
TFA9873B0_BF_IEUVDS= 0x4840, /*!< Enable UVP alarm */
TFA9873B0_BF_IEMANALARM= 0x4850, /*!< Enable manager alarm state */
TFA9873B0_BF_IETDMER= 0x4860, /*!< Enable TDM error */
TFA9873B0_BF_IENOCLK= 0x4870, /*!< Enable lost clk */
TFA9873B0_BF_IPOVDDS= 0x4c00, /*!< Polarity POR */
TFA9873B0_BF_IPOBSTOC= 0x4c10, /*!< Polarity DCDC OCP */
TFA9873B0_BF_IPOOTDS= 0x4c20, /*!< Polarity OTP alarm */
TFA9873B0_BF_IPOOCPR= 0x4c30, /*!< Polarity OCP alarm */
TFA9873B0_BF_IPOUVDS= 0x4c40, /*!< Polarity UVP alarm */
TFA9873B0_BF_IPOMANALARM= 0x4c50, /*!< Polarity manager alarm state */
TFA9873B0_BF_IPOTDMER= 0x4c60, /*!< Polarity TDM error */
TFA9873B0_BF_IPONOCLK= 0x4c70, /*!< Polarity lost clk */
TFA9873B0_BF_BSSCR = 0x5001, /*!< Battery safeguard attack time */
TFA9873B0_BF_BSST = 0x5023, /*!< Battery safeguard threshold voltage level */
TFA9873B0_BF_BSSRL = 0x5061, /*!< Battery safeguard maximum reduction */
TFA9873B0_BF_BSSR = 0x50e0, /*!< Battery voltage read out */
TFA9873B0_BF_BSSBY = 0x50f0, /*!< Bypass battery safeguard */
TFA9873B0_BF_BSSS = 0x5100, /*!< Vbat prot steepness */
TFA9873B0_BF_HPFBYP= 0x5150, /*!< Bypass HPF */
TFA9873B0_BF_DPSA = 0x5170, /*!< Enable DPSA */
TFA9873B0_BF_BYHWCLIP= 0x5240, /*!< Bypass hardware clipper */
TFA9873B0_BF_AMPGAIN= 0x5257, /*!< Amplifier gain */
TFA9873B0_BF_BYPDLYLINE= 0x52f0, /*!< Bypass the interpolator delay line */
TFA9873B0_BF_SLOPEE= 0x55a0, /*!< Enables slope control */
TFA9873B0_BF_SLOPESET= 0x55b0, /*!< Slope speed setting */
TFA9873B0_BF_PWMFREQ= 0x5900, /*!< Control for selection for PWM switching frequency */
TFA9873B0_BF_TDMSPKG= 0x5f63, /*!< Total gain depending on INPLEV setting (channel 0) */
TFA9873B0_BF_IPM = 0x60e1, /*!< Idle power mode control */
TFA9873B0_BF_LNMODE= 0x62e1, /*!< Ctrl select mode */
TFA9873B0_BF_LPM1MODE= 0x64e1, /*!< Low power mode control */
TFA9873B0_BF_TDMSRCMAP= 0x6802, /*!< TDM source mapping */
TFA9873B0_BF_TDMSRCAS= 0x6831, /*!< Sensed value A */
TFA9873B0_BF_TDMSRCBS= 0x6851, /*!< Sensed value B */
TFA9873B0_BF_TDMSRCACLIP= 0x6871, /*!< Clip information (analog /digital) for source0 */
TFA9873B0_BF_TDMSRCBCLIP= 0x6891, /*!< Clip information (analog /digital) for source1 */
TFA9873B0_BF_LP0 = 0x6e00, /*!< Idle power mode */
TFA9873B0_BF_LP1 = 0x6e10, /*!< Low power mode 1 detection */
TFA9873B0_BF_LA = 0x6e20, /*!< Low amplitude detection */
TFA9873B0_BF_VDDPH = 0x6e30, /*!< Vddp greater than Vbat */
TFA9873B0_BF_DELCURCOMP= 0x6f02, /*!< Delay to allign compensation signal with current sense signal */
TFA9873B0_BF_SIGCURCOMP= 0x6f40, /*!< Polarity of compensation for current sense */
TFA9873B0_BF_ENCURCOMP= 0x6f50, /*!< Enable current sense compensation */
TFA9873B0_BF_LVLCLPPWM= 0x6f72, /*!< Set the amount of pwm pulse that may be skipped before clip-flag is triggered */
TFA9873B0_BF_DCMCC = 0x7003, /*!< Max coil current */
TFA9873B0_BF_DCCV = 0x7041, /*!< Slope compensation current, represents LxF (inductance x frequency) */
TFA9873B0_BF_DCIE = 0x7060, /*!< Adaptive boost mode */
TFA9873B0_BF_DCSR = 0x7070, /*!< Soft ramp up/down */
TFA9873B0_BF_DCOVL = 0x7085, /*!< Threshold level to activate active overshoot control */
TFA9873B0_BF_DCDIS = 0x70e0, /*!< DCDC on/off */
TFA9873B0_BF_DCPWM = 0x70f0, /*!< DCDC PWM only mode */
TFA9873B0_BF_DCDYFSW= 0x7420, /*!< Disables the dynamic frequency switching due to flag_voutcomp86/93 */
TFA9873B0_BF_DCTRACK= 0x7430, /*!< Boost algorithm selection, effective only when boost_intelligent is set to 1 */
TFA9873B0_BF_DCTRIP= 0x7444, /*!< 1st Adaptive boost trip levels, effective only when DCIE is set to 1 */
TFA9873B0_BF_DCHOLD= 0x7494, /*!< Hold time for DCDC booster, effective only when boost_intelligent is set to 1 */
TFA9873B0_BF_DCINT = 0x74e0, /*!< Selection of data for adaptive boost algorithm, effective only when boost_intelligent is set to 1 */
TFA9873B0_BF_DCTRIP2= 0x7534, /*!< 2nd Adaptive boost trip levels, effective only when DCIE is set to 1 */
TFA9873B0_BF_DCTRIPT= 0x7584, /*!< Track Adaptive boost trip levels, effective only when boost_intelligent is set to 1 */
TFA9873B0_BF_DCTRIPHYSTE= 0x75f0, /*!< Enable hysteresis on booster trip levels */
TFA9873B0_BF_ENBSTFLT= 0x7620, /*!< Enable the boost filter */
TFA9873B0_BF_DCVOF = 0x7635, /*!< First boost voltage level */
TFA9873B0_BF_DCVOS = 0x7695, /*!< Second boost voltage level */
TFA9873B0_BF_MTPK = 0xa107, /*!< MTP KEY2 register */
TFA9873B0_BF_KEY1LOCKED= 0xa200, /*!< Indicates KEY1 is locked */
TFA9873B0_BF_KEY2LOCKED= 0xa210, /*!< Indicates KEY2 is locked */
TFA9873B0_BF_MTPADDR= 0xa302, /*!< MTP address from I2C register for read/writing mtp in manual single word mode */
TFA9873B0_BF_MTPRDMSB= 0xa50f, /*!< MSB word of MTP manual read data */
TFA9873B0_BF_MTPRDLSB= 0xa60f, /*!< LSB word of MTP manual read data */
TFA9873B0_BF_MTPWRMSB= 0xa70f, /*!< MSB word of write data for MTP manual write */
TFA9873B0_BF_MTPWRLSB= 0xa80f, /*!< LSB word of write data for MTP manual write */
TFA9873B0_BF_EXTTS = 0xb108, /*!< External temperature (C) */
TFA9873B0_BF_TROS = 0xb190, /*!< Select temp Speaker calibration */
TFA9873B0_BF_PLLINSI= 0xcd05, /*!< PLL INSELI - PLL direct bandwidth control mode, only with pll_bandsel set to 1 */
TFA9873B0_BF_PLLINSP= 0xcd64, /*!< PLL INSELP - PLL direct bandwidth control mode only with pll_bandsel set to 1 */
TFA9873B0_BF_PLLINSR= 0xcdb3, /*!< PLL INSELR - PLL direct bandwidth control mode only with pll_bandsel set to 1 */
TFA9873B0_BF_PLLBDSEL= 0xcdf0, /*!< PLL bandwidth selection control, USE WITH CAUTION */
TFA9873B0_BF_PLLNDEC= 0xce09, /*!< PLL NDEC in direct control mode only, use_direct_pll_ctrl set to 1 */
TFA9873B0_BF_PLLMDECM= 0xcea0, /*!< MSB of PLL MDEC in direct control mode only, use_direct_pll_ctrl set to 1 */
TFA9873B0_BF_PLLBP = 0xceb0, /*!< PLL bypass control during functional mode */
TFA9873B0_BF_PLLDI = 0xcec0, /*!< PLL directi control in direct control mode only, use_direct_pll_ctrl set to 1 */
TFA9873B0_BF_PLLDO = 0xced0, /*!< PLL directo control in direct control mode only, use_direct_pll_ctrl set to 1 */
TFA9873B0_BF_PLLCLKSTB= 0xcee0, /*!< PLL FRM clock stable control in direct control mode only, use_direct_pll_ctrl set to 1 */
TFA9873B0_BF_PLLFRM= 0xcef0, /*!< PLL free running mode control in functional mode */
TFA9873B0_BF_PLLMDECL= 0xcf0f, /*!< Bits 15 to 0 of PLL MDEC in direct control mode, use_direct_pll_ctrl set to 1 */
TFA9873B0_BF_PLLPDEC= 0xd006, /*!< PLL PDEC in direct control mode only, use_direct_pll_ctrl set to 1 */
TFA9873B0_BF_PLLDCTRL= 0xd070, /*!< Enabled PLL direct control mode, overrules the PLL LUT with I2C register values */
TFA9873B0_BF_PLLLIMOFF= 0xd090, /*!< PLL up limiter control in PLL direct bandwidth control mode, pll_bandsel set to 1 */
TFA9873B0_BF_PLLSTRTM= 0xd0a2, /*!< PLL startup time selection control */
TFA9873B0_BF_SWPROFIL= 0xe00f, /*!< Software profile data */
TFA9873B0_BF_SWVSTEP= 0xe10f, /*!< Software vstep information */
TFA9873B0_BF_MTPOTC= 0xf000, /*!< Calibration schedule */
TFA9873B0_BF_MTPEX = 0xf010, /*!< Calibration Ron executed */
TFA9873B0_BF_DCMCCAPI= 0xf020, /*!< Calibration current limit DCDC */
TFA9873B0_BF_DCMCCSB= 0xf030, /*!< Sign bit for delta calibration current limit DCDC */
TFA9873B0_BF_USERDEF= 0xf042, /*!< Calibration delta current limit DCDC */
TFA9873B0_BF_CUSTINFO= 0xf078, /*!< Reserved space for allowing customer to store speaker information */
TFA9873B0_BF_R25C = 0xf50f, /*!< Ron resistance of speaker coil */
} Tfa9873B0BfEnumList_t;
#define TFA9873B0_NAMETABLE static tfaBfName_t Tfa9873B0DatasheetNames[]= {\
{ 0x0, "PWDN"}, /* Powerdown selection , */\
{ 0x10, "I2CR"}, /* I2C reset - auto clear , */\
{ 0x30, "AMPE"}, /* Activate amplifier , */\
{ 0x40, "DCA"}, /* Activate DC-to-DC converter , */\
{ 0x71, "INTP"}, /* Interrupt config , */\
{ 0x90, "FSSSEL"}, /* Audio sample reference , */\
{ 0xb0, "BYPOCP"}, /* Bypass OCP , */\
{ 0xc0, "TSTOCP"}, /* OCP testing control , */\
{ 0xe0, "ENPLLSYNC"}, /* Manager control for enabling synchronisation with PLL FS, */\
{ 0x101, "AMPINSEL"}, /* Amplifier input selection , */\
{ 0x120, "MANSCONF"}, /* I2C configured , */\
{ 0x160, "MUTETO"}, /* Time out SB mute sequence , */\
{ 0x1e0, "OPENMTP"}, /* Control for FAIM protection , */\
{ 0x1f0, "DISFCRBST"}, /* Disable boost control with FRCBST , */\
{ 0x203, "AUDFS"}, /* Sample rate (fs) , */\
{ 0x240, "INPLEV"}, /* TDM output attenuation , */\
{ 0x255, "FRACTDEL"}, /* V/I Fractional delay , */\
{ 0x30f, "REV"}, /* Device revision information , */\
{ 0x401, "REFCKEXT"}, /* PLL external ref clock , */\
{ 0x420, "REFCKSEL"}, /* PLL internal ref clock , */\
{ 0x460, "MANAOOSC"}, /* Internal osc off in power down mode , */\
{ 0x480, "FSSYNCEN"}, /* Enable FS synchronisation for clock divider , */\
{ 0x490, "CLKREFSYNCEN"}, /* Enable PLL reference clock synchronisation for clock divider, */\
{ 0x4a0, "AUTOFROSEL"}, /* Override automatic OSC selection mechanism , */\
{ 0x500, "CGUSYNCDCG"}, /* Clock gating control for CGU synchronisation module, */\
{ 0x510, "FRCCLKSPKR"}, /* Force active the speaker sub-system clock when in idle power, */\
{ 0x520, "BSTCLKLP"}, /* Boost clock control in low power mode1 , */\
{ 0x5c0, "SSFAIME"}, /* Sub-system FAIM , */\
{ 0x707, "CLKCHKLO"}, /* Clock check low threshold , */\
{ 0x787, "CLKCHKHI"}, /* Clock check higher threshold , */\
{ 0x802, "AMPOCRT"}, /* Amplifier on-off criteria for shutdown , */\
{ 0x1000, "VDDS"}, /* POR , */\
{ 0x1010, "DCOCPOK"}, /* DCDC OCP nmos (sticky register, clear on read) , */\
{ 0x1020, "OTDS"}, /* OTP alarm (sticky register, clear on read) , */\
{ 0x1030, "OCDS"}, /* OCP amplifier (sticky register, clear on read) , */\
{ 0x1040, "UVDS"}, /* UVP alarm (sticky register, clear on read) , */\
{ 0x1050, "MANALARM"}, /* Alarm state , */\
{ 0x1060, "CLKS"}, /* Clocks stable , */\
{ 0x1070, "MTPB"}, /* MTP busy , */\
{ 0x1080, "NOCLK"}, /* Lost clock (sticky register, clear on read) , */\
{ 0x10a0, "TDMERR"}, /* TDM error , */\
{ 0x1100, "DCIL"}, /* DCDC current limiting , */\
{ 0x1110, "DCDCA"}, /* DCDC active (sticky register, clear on read) , */\
{ 0x1120, "DCDCPC"}, /* Indicates current is max in DC-to-DC converter , */\
{ 0x1130, "DCHVBAT"}, /* DCDC level 1x , */\
{ 0x1140, "DCH114"}, /* DCDC level 1.14x , */\
{ 0x1150, "DCH107"}, /* DCDC level 1.07x , */\
{ 0x1160, "PLLS"}, /* PLL lock , */\
{ 0x1180, "TDMLUTER"}, /* TDM LUT error , */\
{ 0x11c0, "CLKOOR"}, /* External clock status , */\
{ 0x11d0, "SWS"}, /* Amplifier engage , */\
{ 0x11e0, "AMPS"}, /* Amplifier enable , */\
{ 0x11f0, "AREFS"}, /* References enable , */\
{ 0x1300, "OCPOAP"}, /* OCPOK pmos A , */\
{ 0x1310, "OCPOAN"}, /* OCPOK nmos A , */\
{ 0x1320, "OCPOBP"}, /* OCPOK pmos B , */\
{ 0x1330, "OCPOBN"}, /* OCPOK nmos B , */\
{ 0x1380, "OVDS"}, /* OVP alarm , */\
{ 0x1390, "CLIPS"}, /* Amplifier clipping , */\
{ 0x13a0, "ADCCR"}, /* Control ADC , */\
{ 0x13c0, "MANWAIT1"}, /* Wait HW I2C settings , */\
{ 0x13e0, "MANMUTE"}, /* Audio mute sequence , */\
{ 0x13f0, "MANOPER"}, /* Operating state , */\
{ 0x1402, "TDMSTAT"}, /* TDM status bits , */\
{ 0x1433, "MANSTATE"}, /* Device manager status , */\
{ 0x1473, "AMPSTE"}, /* Amplifier control status , */\
{ 0x14b1, "DCMODE"}, /* DCDC mode status bits , */\
{ 0x14d0, "WAITSYNC"}, /* CGU and PLL synchronisation status flag from CGU , */\
{ 0x1509, "BATS"}, /* Battery voltage (V) , */\
{ 0x1608, "TEMPS"}, /* IC Temperature (C) , */\
{ 0x1709, "VDDPS"}, /* IC VDDP voltage ( 1023*VDDP/13 V) , */\
{ 0x2000, "TDME"}, /* Enable interface , */\
{ 0x2013, "TDMSLOTS"}, /* N-slots in Frame , */\
{ 0x2060, "TDMCLINV"}, /* Reception data to BCK clock , */\
{ 0x2073, "TDMFSLN"}, /* FS length , */\
{ 0x20b0, "TDMFSPOL"}, /* FS polarity , */\
{ 0x20c3, "TDMNBCK"}, /* N-BCK's in FS , */\
{ 0x2144, "TDMSLLN"}, /* N-bits in slot , */\
{ 0x2194, "TDMBRMG"}, /* N-bits remaining , */\
{ 0x21e0, "TDMDEL"}, /* Data delay to FS , */\
{ 0x21f0, "TDMADJ"}, /* Data adjustment , */\
{ 0x2201, "TDMOOMP"}, /* Received audio compression , */\
{ 0x2224, "TDMSSIZE"}, /* Sample size per slot , */\
{ 0x2271, "TDMTXDFO"}, /* Format unused bits , */\
{ 0x2291, "TDMTXUS0"}, /* Format unused slots DATAO , */\
{ 0x2300, "TDMSPKE"}, /* Control audio TDM channel in 0 , */\
{ 0x2310, "TDMDCE"}, /* Control audio TDM channel in 1 , */\
{ 0x2330, "TDMCSE"}, /* current sense vbat temperature and vddp feedback , */\
{ 0x2340, "TDMVSE"}, /* Voltage sense vbat temperature and vddp feedback , */\
{ 0x2603, "TDMSPKS"}, /* TDM slot for sink 0 , */\
{ 0x2643, "TDMDCS"}, /* TDM slot for sink 1 , */\
{ 0x26c3, "TDMCSS"}, /* Slot Position of current sense vbat temperature and vddp feedback, */\
{ 0x2703, "TDMVSS"}, /* Slot Position of Voltage sense vbat temperature and vddp feedback, */\
{ 0x4000, "ISTVDDS"}, /* Status POR , */\
{ 0x4010, "ISTBSTOC"}, /* Status DCDC OCP , */\
{ 0x4020, "ISTOTDS"}, /* Status OTP alarm , */\
{ 0x4030, "ISTOCPR"}, /* Status OCP alarm , */\
{ 0x4040, "ISTUVDS"}, /* Status UVP alarm , */\
{ 0x4050, "ISTMANALARM"}, /* Status manager alarm state , */\
{ 0x4060, "ISTTDMER"}, /* Status TDM error , */\
{ 0x4070, "ISTNOCLK"}, /* Status lost clock , */\
{ 0x4400, "ICLVDDS"}, /* Clear POR , */\
{ 0x4410, "ICLBSTOC"}, /* Clear DCDC OCP , */\
{ 0x4420, "ICLOTDS"}, /* Clear OTP alarm , */\
{ 0x4430, "ICLOCPR"}, /* Clear OCP alarm , */\
{ 0x4440, "ICLUVDS"}, /* Clear UVP alarm , */\
{ 0x4450, "ICLMANALARM"}, /* Clear manager alarm state , */\
{ 0x4460, "ICLTDMER"}, /* Clear TDM error , */\
{ 0x4470, "ICLNOCLK"}, /* Clear lost clk , */\
{ 0x4800, "IEVDDS"}, /* Enable POR , */\
{ 0x4810, "IEBSTOC"}, /* Enable DCDC OCP , */\
{ 0x4820, "IEOTDS"}, /* Enable OTP alarm , */\
{ 0x4830, "IEOCPR"}, /* Enable OCP alarm , */\
{ 0x4840, "IEUVDS"}, /* Enable UVP alarm , */\
{ 0x4850, "IEMANALARM"}, /* Enable manager alarm state , */\
{ 0x4860, "IETDMER"}, /* Enable TDM error , */\
{ 0x4870, "IENOCLK"}, /* Enable lost clk , */\
{ 0x4c00, "IPOVDDS"}, /* Polarity POR , */\
{ 0x4c10, "IPOBSTOC"}, /* Polarity DCDC OCP , */\
{ 0x4c20, "IPOOTDS"}, /* Polarity OTP alarm , */\
{ 0x4c30, "IPOOCPR"}, /* Polarity OCP alarm , */\
{ 0x4c40, "IPOUVDS"}, /* Polarity UVP alarm , */\
{ 0x4c50, "IPOMANALARM"}, /* Polarity manager alarm state , */\
{ 0x4c60, "IPOTDMER"}, /* Polarity TDM error , */\
{ 0x4c70, "IPONOCLK"}, /* Polarity lost clk , */\
{ 0x5001, "BSSCR"}, /* Battery safeguard attack time , */\
{ 0x5023, "BSST"}, /* Battery safeguard threshold voltage level , */\
{ 0x5061, "BSSRL"}, /* Battery safeguard maximum reduction , */\
{ 0x50e0, "BSSR"}, /* Battery voltage read out , */\
{ 0x50f0, "BSSBY"}, /* Bypass battery safeguard , */\
{ 0x5100, "BSSS"}, /* Vbat prot steepness , */\
{ 0x5150, "HPFBYP"}, /* Bypass HPF , */\
{ 0x5170, "DPSA"}, /* Enable DPSA , */\
{ 0x5240, "BYHWCLIP"}, /* Bypass hardware clipper , */\
{ 0x5257, "AMPGAIN"}, /* Amplifier gain , */\
{ 0x52f0, "BYPDLYLINE"}, /* Bypass the interpolator delay line , */\
{ 0x55a0, "SLOPEE"}, /* Enables slope control , */\
{ 0x55b0, "SLOPESET"}, /* Slope speed setting , */\
{ 0x5900, "PWMFREQ"}, /* Control for selection for PWM switching frequency , */\
{ 0x5f63, "TDMSPKG"}, /* Total gain depending on INPLEV setting (channel 0), */\
{ 0x60e1, "IPM"}, /* Idle power mode control , */\
{ 0x62e1, "LNMODE"}, /* Ctrl select mode , */\
{ 0x64e1, "LPM1MODE"}, /* Low power mode control , */\
{ 0x6802, "TDMSRCMAP"}, /* TDM source mapping , */\
{ 0x6831, "TDMSRCAS"}, /* Sensed value A , */\
{ 0x6851, "TDMSRCBS"}, /* Sensed value B , */\
{ 0x6871, "TDMSRCACLIP"}, /* Clip information (analog /digital) for source0 , */\
{ 0x6891, "TDMSRCBCLIP"}, /* Clip information (analog /digital) for source1 , */\
{ 0x6e00, "LP0"}, /* Idle power mode , */\
{ 0x6e10, "LP1"}, /* Low power mode 1 detection , */\
{ 0x6e20, "LA"}, /* Low amplitude detection , */\
{ 0x6e30, "VDDPH"}, /* Vddp greater than Vbat , */\
{ 0x6f02, "DELCURCOMP"}, /* Delay to allign compensation signal with current sense signal, */\
{ 0x6f40, "SIGCURCOMP"}, /* Polarity of compensation for current sense , */\
{ 0x6f50, "ENCURCOMP"}, /* Enable current sense compensation , */\
{ 0x6f72, "LVLCLPPWM"}, /* Set the amount of pwm pulse that may be skipped before clip-flag is triggered, */\
{ 0x7003, "DCMCC"}, /* Max coil current , */\
{ 0x7041, "DCCV"}, /* Slope compensation current, represents LxF (inductance x frequency) , */\
{ 0x7060, "DCIE"}, /* Adaptive boost mode , */\
{ 0x7070, "DCSR"}, /* Soft ramp up/down , */\
{ 0x7085, "DCOVL"}, /* Threshold level to activate active overshoot control, */\
{ 0x70e0, "DCDIS"}, /* DCDC on/off , */\
{ 0x70f0, "DCPWM"}, /* DCDC PWM only mode , */\
{ 0x7420, "DCDYFSW"}, /* Disables the dynamic frequency switching due to flag_voutcomp86/93, */\
{ 0x7430, "DCTRACK"}, /* Boost algorithm selection, effective only when boost_intelligent is set to 1, */\
{ 0x7444, "DCTRIP"}, /* 1st Adaptive boost trip levels, effective only when DCIE is set to 1, */\
{ 0x7494, "DCHOLD"}, /* Hold time for DCDC booster, effective only when boost_intelligent is set to 1, */\
{ 0x74e0, "DCINT"}, /* Selection of data for adaptive boost algorithm, effective only when boost_intelligent is set to 1, */\
{ 0x7534, "DCTRIP2"}, /* 2nd Adaptive boost trip levels, effective only when DCIE is set to 1, */\
{ 0x7584, "DCTRIPT"}, /* Track Adaptive boost trip levels, effective only when boost_intelligent is set to 1, */\
{ 0x75f0, "DCTRIPHYSTE"}, /* Enable hysteresis on booster trip levels , */\
{ 0x7620, "ENBSTFLT"}, /* Enable the boost filter , */\
{ 0x7635, "DCVOF"}, /* First boost voltage level , */\
{ 0x7695, "DCVOS"}, /* Second boost voltage level , */\
{ 0xa107, "MTPK"}, /* MTP KEY2 register , */\
{ 0xa200, "KEY1LOCKED"}, /* Indicates KEY1 is locked , */\
{ 0xa210, "KEY2LOCKED"}, /* Indicates KEY2 is locked , */\
{ 0xa302, "MTPADDR"}, /* MTP address from I2C register for read/writing mtp in manual single word mode, */\
{ 0xa50f, "MTPRDMSB"}, /* MSB word of MTP manual read data , */\
{ 0xa60f, "MTPRDLSB"}, /* LSB word of MTP manual read data , */\
{ 0xa70f, "MTPWRMSB"}, /* MSB word of write data for MTP manual write , */\
{ 0xa80f, "MTPWRLSB"}, /* LSB word of write data for MTP manual write , */\
{ 0xb108, "EXTTS"}, /* External temperature (C) , */\
{ 0xb190, "TROS"}, /* Select temp Speaker calibration , */\
{ 0xcd05, "PLLINSI"}, /* PLL INSELI - PLL direct bandwidth control mode, only with pll_bandsel set to 1, */\
{ 0xcd64, "PLLINSP"}, /* PLL INSELP - PLL direct bandwidth control mode only with pll_bandsel set to 1, */\
{ 0xcdb3, "PLLINSR"}, /* PLL INSELR - PLL direct bandwidth control mode only with pll_bandsel set to 1, */\
{ 0xcdf0, "PLLBDSEL"}, /* PLL bandwidth selection control, USE WITH CAUTION , */\
{ 0xce09, "PLLNDEC"}, /* PLL NDEC in direct control mode only, use_direct_pll_ctrl set to 1, */\
{ 0xcea0, "PLLMDECM"}, /* MSB of PLL MDEC in direct control mode only, use_direct_pll_ctrl set to 1, */\
{ 0xceb0, "PLLBP"}, /* PLL bypass control during functional mode , */\
{ 0xcec0, "PLLDI"}, /* PLL directi control in direct control mode only, use_direct_pll_ctrl set to 1, */\
{ 0xced0, "PLLDO"}, /* PLL directo control in direct control mode only, use_direct_pll_ctrl set to 1, */\
{ 0xcee0, "PLLCLKSTB"}, /* PLL FRM clock stable control in direct control mode only, use_direct_pll_ctrl set to 1, */\
{ 0xcef0, "PLLFRM"}, /* PLL free running mode control in functional mode , */\
{ 0xcf0f, "PLLMDECL"}, /* Bits 15 to 0 of PLL MDEC in direct control mode, use_direct_pll_ctrl set to 1, */\
{ 0xd006, "PLLPDEC"}, /* PLL PDEC in direct control mode only, use_direct_pll_ctrl set to 1, */\
{ 0xd070, "PLLDCTRL"}, /* Enabled PLL direct control mode, overrules the PLL LUT with I2C register values, */\
{ 0xd090, "PLLLIMOFF"}, /* PLL up limiter control in PLL direct bandwidth control mode, pll_bandsel set to 1, */\
{ 0xd0a2, "PLLSTRTM"}, /* PLL startup time selection control , */\
{ 0xe00f, "SWPROFIL"}, /* Software profile data , */\
{ 0xe10f, "SWVSTEP"}, /* Software vstep information , */\
{ 0xf000, "MTPOTC"}, /* Calibration schedule , */\
{ 0xf010, "MTPEX"}, /* Calibration Ron executed , */\
{ 0xf020, "DCMCCAPI"}, /* Calibration current limit DCDC , */\
{ 0xf030, "DCMCCSB"}, /* Sign bit for delta calibration current limit DCDC , */\
{ 0xf042, "USERDEF"}, /* Calibration delta current limit DCDC , */\
{ 0xf078, "CUSTINFO"}, /* Reserved space for allowing customer to store speaker information, */\
{ 0xf50f, "R25C"}, /* Ron resistance of speaker coil , */\
{ 0xffff,"Unknown bitfield enum" } /* not found */\
};
#define TFA9873B0_BITNAMETABLE static tfaBfName_t Tfa9873B0BitNames[]= {\
{ 0x0, "powerdown"}, /* Powerdown selection , */\
{ 0x10, "reset"}, /* I2C reset - auto clear , */\
{ 0x30, "enbl_amplifier"}, /* Activate amplifier , */\
{ 0x40, "enbl_boost"}, /* Activate DC-to-DC converter , */\
{ 0x71, "int_pad_io"}, /* Interrupt config , */\
{ 0x90, "fs_pulse_sel"}, /* Audio sample reference , */\
{ 0xb0, "bypass_ocp"}, /* Bypass OCP , */\
{ 0xc0, "test_ocp"}, /* OCP testing control , */\
{ 0xd0, "sel_man_wait_time"}, /* Manager wait time selection control , */\
{ 0xe0, "enbl_pll_synchronisation"}, /* Manager control for enabling synchronisation with PLL FS, */\
{ 0x101, "vamp_sel1"}, /* Amplifier input selection , */\
{ 0x120, "src_set_configured"}, /* I2C configured , */\
{ 0x160, "disable_mute_time_out"}, /* Time out SB mute sequence , */\
{ 0x1e0, "unprotect_faim"}, /* Control for FAIM protection , */\
{ 0x1f0, "disable_frcbst"}, /* Disable boost control with FRCBST , */\
{ 0x203, "audio_fs"}, /* Sample rate (fs) , */\
{ 0x240, "input_level"}, /* TDM output attenuation , */\
{ 0x255, "cs_frac_delay"}, /* V/I Fractional delay , */\
{ 0x30f, "device_rev"}, /* Device revision information , */\
{ 0x401, "pll_clkin_sel"}, /* PLL external ref clock , */\
{ 0x420, "pll_clkin_sel_osc"}, /* PLL internal ref clock , */\
{ 0x460, "enbl_osc_auto_off"}, /* Internal osc off in power down mode , */\
{ 0x480, "enbl_fs_sync"}, /* Enable FS synchronisation for clock divider , */\
{ 0x490, "enbl_clkref_sync"}, /* Enable PLL reference clock synchronisation for clock divider, */\
{ 0x4a0, "override_auto_sel_osc"}, /* Override automatic OSC selection mechanism , */\
{ 0x500, "disable_cgu_sync_cgate"}, /* Clock gating control for CGU synchronisation module, */\
{ 0x510, "force_spkr_clk"}, /* Force active the speaker sub-system clock when in idle power, */\
{ 0x520, "ctrl_bst_clk_lp1"}, /* Boost clock control in low power mode1 , */\
{ 0x5c0, "enbl_faim_ss"}, /* Sub-system FAIM , */\
{ 0x707, "clkchk_th_lo"}, /* Clock check low threshold , */\
{ 0x787, "clkchk_th_hi"}, /* Clock check higher threshold , */\
{ 0x802, "ctrl_on2off_criterion"}, /* Amplifier on-off criteria for shutdown , */\
{ 0xe07, "ctrl_digtoana"}, /* Spare control from digital to analog , */\
{ 0xf0f, "hidden_code"}, /* 5A6Bh, 23147d to access registers (default for engineering), */\
{ 0x1000, "flag_por"}, /* POR , */\
{ 0x1010, "flag_bst_ocpok"}, /* DCDC OCP nmos (sticky register, clear on read) , */\
{ 0x1020, "flag_otpok"}, /* OTP alarm (sticky register, clear on read) , */\
{ 0x1030, "flag_ocp_alarm"}, /* OCP amplifier (sticky register, clear on read) , */\
{ 0x1040, "flag_uvpok"}, /* UVP alarm (sticky register, clear on read) , */\
{ 0x1050, "flag_man_alarm_state"}, /* Alarm state , */\
{ 0x1060, "flag_clocks_stable"}, /* Clocks stable , */\
{ 0x1070, "flag_mtp_busy"}, /* MTP busy , */\
{ 0x1080, "flag_lost_clk"}, /* Lost clock (sticky register, clear on read) , */\
{ 0x10a0, "flag_tdm_error"}, /* TDM error , */\
{ 0x1100, "flag_bst_bstcur"}, /* DCDC current limiting , */\
{ 0x1110, "flag_bst_hiz"}, /* DCDC active (sticky register, clear on read) , */\
{ 0x1120, "flag_bst_peakcur"}, /* Indicates current is max in DC-to-DC converter , */\
{ 0x1130, "flag_bst_voutcomp"}, /* DCDC level 1x , */\
{ 0x1140, "flag_bst_voutcomp86"}, /* DCDC level 1.14x , */\
{ 0x1150, "flag_bst_voutcomp93"}, /* DCDC level 1.07x , */\
{ 0x1160, "flag_pll_lock"}, /* PLL lock , */\
{ 0x1180, "flag_tdm_lut_error"}, /* TDM LUT error , */\
{ 0x11c0, "flag_clk_out_of_range"}, /* External clock status , */\
{ 0x11d0, "flag_engage"}, /* Amplifier engage , */\
{ 0x11e0, "flag_enbl_amp"}, /* Amplifier enable , */\
{ 0x11f0, "flag_enbl_ref"}, /* References enable , */\
{ 0x1300, "flag_ocpokap"}, /* OCPOK pmos A , */\
{ 0x1310, "flag_ocpokan"}, /* OCPOK nmos A , */\
{ 0x1320, "flag_ocpokbp"}, /* OCPOK pmos B , */\
{ 0x1330, "flag_ocpokbn"}, /* OCPOK nmos B , */\
{ 0x1380, "flag_ovpok"}, /* OVP alarm , */\
{ 0x1390, "flag_clip"}, /* Amplifier clipping , */\
{ 0x13a0, "flag_adc10_ready"}, /* Control ADC , */\
{ 0x13c0, "flag_man_wait_src_settings"}, /* Wait HW I2C settings , */\
{ 0x13e0, "flag_man_start_mute_audio"}, /* Audio mute sequence , */\
{ 0x13f0, "flag_man_operating_state"}, /* Operating state , */\
{ 0x1402, "flag_tdm_status"}, /* TDM status bits , */\
{ 0x1433, "man_state"}, /* Device manager status , */\
{ 0x1473, "amp_ctrl_state"}, /* Amplifier control status , */\
{ 0x14b1, "status_bst_mode"}, /* DCDC mode status bits , */\
{ 0x14d0, "flag_waiting_for_sync"}, /* CGU and PLL synchronisation status flag from CGU , */\
{ 0x1509, "bat_adc"}, /* Battery voltage (V) , */\
{ 0x1608, "temp_adc"}, /* IC Temperature (C) , */\
{ 0x1709, "vddp_adc"}, /* IC VDDP voltage ( 1023*VDDP/13 V) , */\
{ 0x2000, "tdm_enable"}, /* Enable interface , */\
{ 0x2013, "tdm_nb_of_slots"}, /* N-slots in Frame , */\
{ 0x2060, "tdm_clk_inversion"}, /* Reception data to BCK clock , */\
{ 0x2073, "tdm_fs_ws_length"}, /* FS length , */\
{ 0x20b0, "tdm_fs_ws_polarity"}, /* FS polarity , */\
{ 0x20c3, "tdm_nbck"}, /* N-BCK's in FS , */\
{ 0x2144, "tdm_slot_length"}, /* N-bits in slot , */\
{ 0x2194, "tdm_bits_remaining"}, /* N-bits remaining , */\
{ 0x21e0, "tdm_data_delay"}, /* Data delay to FS , */\
{ 0x21f0, "tdm_data_adjustment"}, /* Data adjustment , */\
{ 0x2201, "tdm_audio_sample_compression"}, /* Received audio compression , */\
{ 0x2224, "tdm_sample_size"}, /* Sample size per slot , */\
{ 0x2271, "tdm_txdata_format"}, /* Format unused bits , */\
{ 0x2291, "tdm_txdata_format_unused_slot_sd0"}, /* Format unused slots DATAO , */\
{ 0x2300, "tdm_sink0_enable"}, /* Control audio TDM channel in 0 , */\
{ 0x2310, "tdm_sink1_enable"}, /* Control audio TDM channel in 1 , */\
{ 0x2330, "tdm_source0_enable"}, /* current sense vbat temperature and vddp feedback , */\
{ 0x2340, "tdm_source1_enable"}, /* Voltage sense vbat temperature and vddp feedback , */\
{ 0x2603, "tdm_sink0_slot"}, /* TDM slot for sink 0 , */\
{ 0x2643, "tdm_sink1_slot"}, /* TDM slot for sink 1 , */\
{ 0x26c3, "tdm_source0_slot"}, /* Slot Position of current sense vbat temperature and vddp feedback, */\
{ 0x2703, "tdm_source1_slot"}, /* Slot Position of Voltage sense vbat temperature and vddp feedback, */\
{ 0x4000, "int_out_flag_por"}, /* Status POR , */\
{ 0x4010, "int_out_flag_bst_ocpok"}, /* Status DCDC OCP , */\
{ 0x4020, "int_out_flag_otpok"}, /* Status OTP alarm , */\
{ 0x4030, "int_out_flag_ocp_alarm"}, /* Status OCP alarm , */\
{ 0x4040, "int_out_flag_uvpok"}, /* Status UVP alarm , */\
{ 0x4050, "int_out_flag_man_alarm_state"}, /* Status manager alarm state , */\
{ 0x4060, "int_out_flag_tdm_error"}, /* Status TDM error , */\
{ 0x4070, "int_out_flag_lost_clk"}, /* Status lost clock , */\
{ 0x4400, "int_in_flag_por"}, /* Clear POR , */\
{ 0x4410, "int_in_flag_bst_ocpok"}, /* Clear DCDC OCP , */\
{ 0x4420, "int_in_flag_otpok"}, /* Clear OTP alarm , */\
{ 0x4430, "int_in_flag_ocp_alarm"}, /* Clear OCP alarm , */\
{ 0x4440, "int_in_flag_uvpok"}, /* Clear UVP alarm , */\
{ 0x4450, "int_in_flag_man_alarm_state"}, /* Clear manager alarm state , */\
{ 0x4460, "int_in_flag_tdm_error"}, /* Clear TDM error , */\
{ 0x4470, "int_in_flag_lost_clk"}, /* Clear lost clk , */\
{ 0x4800, "int_enable_flag_por"}, /* Enable POR , */\
{ 0x4810, "int_enable_flag_bst_ocpok"}, /* Enable DCDC OCP , */\
{ 0x4820, "int_enable_flag_otpok"}, /* Enable OTP alarm , */\
{ 0x4830, "int_enable_flag_ocp_alarm"}, /* Enable OCP alarm , */\
{ 0x4840, "int_enable_flag_uvpok"}, /* Enable UVP alarm , */\
{ 0x4850, "int_enable_flag_man_alarm_state"}, /* Enable manager alarm state , */\
{ 0x4860, "int_enable_flag_tdm_error"}, /* Enable TDM error , */\
{ 0x4870, "int_enable_flag_lost_clk"}, /* Enable lost clk , */\
{ 0x4c00, "int_polarity_flag_por"}, /* Polarity POR , */\
{ 0x4c10, "int_polarity_flag_bst_ocpok"}, /* Polarity DCDC OCP , */\
{ 0x4c20, "int_polarity_flag_otpok"}, /* Polarity OTP alarm , */\
{ 0x4c30, "int_polarity_flag_ocp_alarm"}, /* Polarity OCP alarm , */\
{ 0x4c40, "int_polarity_flag_uvpok"}, /* Polarity UVP alarm , */\
{ 0x4c50, "int_polarity_flag_man_alarm_state"}, /* Polarity manager alarm state , */\
{ 0x4c60, "int_polarity_flag_tdm_error"}, /* Polarity TDM error , */\
{ 0x4c70, "int_polarity_flag_lost_clk"}, /* Polarity lost clk , */\
{ 0x5001, "vbat_prot_attack_time"}, /* Battery safeguard attack time , */\
{ 0x5023, "vbat_prot_thlevel"}, /* Battery safeguard threshold voltage level , */\
{ 0x5061, "vbat_prot_max_reduct"}, /* Battery safeguard maximum reduction , */\
{ 0x50d0, "rst_min_vbat"}, /* Reset clipper - auto clear , */\
{ 0x50e0, "sel_vbat"}, /* Battery voltage read out , */\
{ 0x50f0, "bypass_clipper"}, /* Bypass battery safeguard , */\
{ 0x5100, "batsense_steepness"}, /* Vbat prot steepness , */\
{ 0x5150, "bypass_hp"}, /* Bypass HPF , */\
{ 0x5170, "enbl_dpsa"}, /* Enable DPSA , */\
{ 0x5240, "bypasshwclip"}, /* Bypass hardware clipper , */\
{ 0x5257, "gain"}, /* Amplifier gain , */\
{ 0x52f0, "bypass_dly_line"}, /* Bypass the interpolator delay line , */\
{ 0x5301, "dpsa_level"}, /* DPSA threshold levels , */\
{ 0x5321, "dpsa_release"}, /* DPSA release time , */\
{ 0x5350, "bypass_lp"}, /* Bypass the low pass filter inside temperature sensor, */\
{ 0x5430, "icomp_engage"}, /* Engage of icomp , */\
{ 0x5440, "ctrl_kickback"}, /* Prevent double pulses of output stage , */\
{ 0x5450, "icomp_engage_overrule"}, /* To overrule the functional icomp_engage signal during validation, */\
{ 0x5463, "ctrl_dem"}, /* Enable DEM icomp and DEM one bit DAC , */\
{ 0x54a1, "ref_amp_irefdist_set_ctrl"}, /* Scaling of reference current for amplifier OCP , */\
{ 0x5500, "bypass_ctrlloop"}, /* Switch amplifier into open loop configuration , */\
{ 0x5513, "ctrl_dem_mismatch"}, /* Enable DEM icomp mismatch for testing , */\
{ 0x5552, "dpsa_drive"}, /* Drive setting (binary coded) , */\
{ 0x5581, "ctrlloop_vstress_select"}, /* GO2 capacitor stress selector for control loop , */\
{ 0x55a0, "ctrl_slopectrl"}, /* Enables slope control , */\
{ 0x55b0, "ctrl_slope"}, /* Slope speed setting , */\
{ 0x5600, "ref_iref_enbl"}, /* Enable of reference current for OCP , */\
{ 0x5652, "ref_irefdist_test_enbl"}, /* Enable of test-function of distribution of reference current, used for OCP. When enabled, the current will to to anamux iso powerstages. Using e.g. 011 it will add the current of powerstage P and N., */\
{ 0x570a, "enbl_amp"}, /* Switch on the class-D power sections, each part of the analog sections can be switched on/off individually, */\
{ 0x57b0, "enbl_engage"}, /* Enables/engage the control stage , */\
{ 0x57c0, "enbl_engage_pst"}, /* Enables/engage the power stage , */\
{ 0x5810, "hard_mute"}, /* Hard mute - PWM , */\
{ 0x5844, "pwm_delay"}, /* PWM delay bits to set the delay, clock PWM is 1/(K*2048*fs), */\
{ 0x5890, "reclock_pwm"}, /* Reclock the PWM signal inside analog , */\
{ 0x58c0, "enbl_pwm_phase_shift"}, /* Control for PWM phase shift , */\
{ 0x5900, "sel_pwm_freq"}, /* Control for selection for PWM switching frequency , */\
{ 0x5910, "sel_pwm_delay_src"}, /* Control for selection for PWM delay line source , */\
{ 0x5f63, "ctrl_attr"}, /* Total gain depending on INPLEV setting (channel 0), */\
{ 0x6005, "idle_power_cal_offset"}, /* Idle power mode detector ctrl cal_offset from gain module , */\
{ 0x6065, "idle_power_zero_lvl"}, /* IIdle power mode zero crossing detection level , */\
{ 0x60e1, "idle_power_mode"}, /* Idle power mode control , */\
{ 0x6105, "idle_power_threshold_lvl"}, /* Idle power mode amplitude trigger level , */\
{ 0x6165, "idle_power_hold_time"}, /* Idle power mode detector ctrl hold time before low audio is reckoned to be low audio, */\
{ 0x61c0, "disable_idle_power_mode"}, /* Idle power mode detector control , */\
{ 0x6265, "zero_lvl"}, /* Low noise gain switch zero trigger level , */\
{ 0x62c1, "ctrl_fb_resistor"}, /* Select amplifier feedback resistor connection , */\
{ 0x62e1, "lownoisegain_mode"}, /* Ctrl select mode , */\
{ 0x6305, "threshold_lvl"}, /* Low noise gain switch trigger level , */\
{ 0x6365, "hold_time"}, /* Low noise gain switch ctrl hold time before low audio is reckoned to be low audio, */\
{ 0x6405, "lpm1_cal_offset"}, /* Low power mode1 detector ctrl cal_offset from gain module , */\
{ 0x6465, "lpm1_zero_lvl"}, /* Low power mode1 zero crossing detection level , */\
{ 0x64e1, "lpm1_mode"}, /* Low power mode control , */\
{ 0x6505, "lpm1_threshold_lvl"}, /* Low power mode1 amplitude trigger level , */\
{ 0x6565, "lpm1_hold_time"}, /* Low power mode1 detector ctrl hold time before low audio is reckoned to be low audio, */\
{ 0x65c0, "disable_low_power_mode"}, /* Low power mode1 detector control , */\
{ 0x6611, "dcdc_ctrl_maxzercnt"}, /* DCDC Number of zero current flags to count before going to PFM mode, */\
{ 0x6656, "dcdc_vbat_delta_detect"}, /* Threshold before booster is reacting on a delta Vbat (in PFM mode) by temporarily switching to PWM mode, */\
{ 0x66c0, "dcdc_ignore_vbat"}, /* Ignore an increase on Vbat , */\
{ 0x66d2, "pfmfreq_limit"}, /* Lowest PFM frequency limit , */\
{ 0x6700, "enbl_minion"}, /* Enables minion (small) power stage , */\
{ 0x6713, "vth_vddpvbat"}, /* Select vddp-vbat threshold signal , */\
{ 0x6750, "lpen_vddpvbat"}, /* Select vddp-vbat filtred vs unfiltered compare , */\
{ 0x6761, "ctrl_rfb"}, /* Feedback resistor selection - I2C direct mode , */\
{ 0x6802, "tdm_source_mapping"}, /* TDM source mapping , */\
{ 0x6831, "tdm_sourcea_frame_sel"}, /* Sensed value A , */\
{ 0x6851, "tdm_sourceb_frame_sel"}, /* Sensed value B , */\
{ 0x6871, "tdm_source0_clip_sel"}, /* Clip information (analog /digital) for source0 , */\
{ 0x6891, "tdm_source1_clip_sel"}, /* Clip information (analog /digital) for source1 , */\
{ 0x6a02, "rst_min_vbat_delay"}, /* rst_min_vbat delay (nb fs) , */\
{ 0x6b00, "disable_auto_engage"}, /* Disable auto engange , */\
{ 0x6b10, "disable_engage"}, /* Disable engange , */\
{ 0x6c02, "ns_hp2ln_criterion"}, /* 0..7 zeroes at ns as threshold to swap from high_power to low_noise, */\
{ 0x6c32, "ns_ln2hp_criterion"}, /* 0..7 zeroes at ns as threshold to swap from low_noise to high_power, */\
{ 0x6c69, "spare_out"}, /* spare_out , */\
{ 0x6d0f, "spare_in"}, /* spare_in , */\
{ 0x6e00, "flag_idle_power_mode"}, /* Idle power mode , */\
{ 0x6e10, "flag_lp_detect_mode1"}, /* Low power mode 1 detection , */\
{ 0x6e20, "flag_low_amplitude"}, /* Low amplitude detection , */\
{ 0x6e30, "flag_vddp_gt_vbat"}, /* Vddp greater than Vbat , */\
{ 0x6f02, "cursense_comp_delay"}, /* Delay to allign compensation signal with current sense signal, */\
{ 0x6f40, "cursense_comp_sign"}, /* Polarity of compensation for current sense , */\
{ 0x6f50, "enbl_cursense_comp"}, /* Enable current sense compensation , */\
{ 0x6f72, "pwms_clip_lvl"}, /* Set the amount of pwm pulse that may be skipped before clip-flag is triggered, */\
{ 0x7003, "boost_cur"}, /* Max coil current , */\
{ 0x7041, "bst_slpcmplvl"}, /* Slope compensation current, represents LxF (inductance x frequency) , */\
{ 0x7060, "boost_intel"}, /* Adaptive boost mode , */\
{ 0x7070, "boost_speed"}, /* Soft ramp up/down , */\
{ 0x7085, "overshoot_correction_lvl"}, /* Threshold level to activate active overshoot control, */\
{ 0x70e0, "dcdcoff_mode"}, /* DCDC on/off , */\
{ 0x70f0, "dcdc_pwmonly"}, /* DCDC PWM only mode , */\
{ 0x7104, "bst_drive"}, /* Binary coded drive setting for boost converter power stage, */\
{ 0x7151, "bst_scalecur"}, /* For testing direct control scale current , */\
{ 0x7174, "bst_slopecur"}, /* For testing direct control slope current , */\
{ 0x71c1, "bst_slope"}, /* Boost slope speed , */\
{ 0x71e0, "bst_bypass_bstcur"}, /* Bypass control for boost current settings , */\
{ 0x71f0, "bst_bypass_bstfoldback"}, /* Bypass control for boost foldback , */\
{ 0x7200, "enbl_bst_engage"}, /* Enable power stage dcdc controller , */\
{ 0x7210, "enbl_bst_hizcom"}, /* Enable hiz comparator , */\
{ 0x7220, "enbl_bst_peak2avg"}, /* Enable boost peak2avg functionality , */\
{ 0x7230, "enbl_bst_peakcur"}, /* Enable peak current , */\
{ 0x7240, "enbl_bst_power"}, /* Enable line of the powerstage , */\
{ 0x7250, "enbl_bst_slopecur"}, /* Enable bit of max-current DAC , */\
{ 0x7260, "enbl_bst_voutcomp"}, /* Enable vout comparators , */\
{ 0x7270, "enbl_bst_voutcomp86"}, /* Enable vout-86 comparators , */\
{ 0x7280, "enbl_bst_voutcomp93"}, /* Enable vout-93 comparators , */\
{ 0x7290, "enbl_bst_windac"}, /* Enable window DAC , */\
{ 0x72a5, "bst_windac"}, /* For testing direct control windac , */\
{ 0x7300, "boost_alg"}, /* Control for boost adaptive loop gain , */\
{ 0x7311, "boost_loopgain"}, /* DCDC boost loopgain setting , */\
{ 0x7331, "bst_freq"}, /* DCDC boost frequency control , */\
{ 0x7350, "disable_artf654484_fix"}, /* Disables the fix for artf654484 (loss of efficiency when Vbst is close to Vbat), */\
{ 0x7360, "disable_artf676996_fix"}, /* Disables the fix for artf676996 (OCP booster triggered when Vtrgt is just above Vbat), */\
{ 0x7371, "ref_bst_irefdist_set_ctrl"}, /* Scaling of reference current for booster OCP , */\
{ 0x7420, "disable_dynamic_freq"}, /* Disables the dynamic frequency switching due to flag_voutcomp86/93, */\
{ 0x7430, "boost_track"}, /* Boost algorithm selection, effective only when boost_intelligent is set to 1, */\
{ 0x7444, "boost_trip_lvl_1st"}, /* 1st Adaptive boost trip levels, effective only when DCIE is set to 1, */\
{ 0x7494, "boost_hold_time"}, /* Hold time for DCDC booster, effective only when boost_intelligent is set to 1, */\
{ 0x74e0, "sel_dcdc_envelope_8fs"}, /* Selection of data for adaptive boost algorithm, effective only when boost_intelligent is set to 1, */\
{ 0x74f0, "ignore_flag_voutcomp86"}, /* Determines the maximum PWM frequency be the most efficient in relation to the Booster inductor value, */\
{ 0x7534, "boost_trip_lvl_2nd"}, /* 2nd Adaptive boost trip levels, effective only when DCIE is set to 1, */\
{ 0x7584, "boost_trip_lvl_track"}, /* Track Adaptive boost trip levels, effective only when boost_intelligent is set to 1, */\
{ 0x75f0, "enbl_trip_hyst"}, /* Enable hysteresis on booster trip levels , */\
{ 0x7620, "enbl_bst_filter"}, /* Enable the boost filter , */\
{ 0x7635, "frst_boost_voltage"}, /* First boost voltage level , */\
{ 0x7695, "scnd_boost_voltage"}, /* Second boost voltage level , */\
{ 0x8050, "cs_gain_control"}, /* Current sense gain control , */\
{ 0x8060, "cs_bypass_gc"}, /* Bypasses the CS gain correction , */\
{ 0x8087, "cs_gain"}, /* Current sense gain , */\
{ 0x8210, "invertpwm"}, /* Current sense common mode feedback pwm invert control, */\
{ 0x8305, "cs_ktemp"}, /* Current sense temperature compensation trimming (1 - VALUE*TEMP)*signal, */\
{ 0x8364, "cs_ktemp2"}, /* Second order temperature compensation coefficient , */\
{ 0x8400, "cs_adc_bsoinv"}, /* Bitstream inversion for current sense ADC , */\
{ 0x8440, "cs_adc_nortz"}, /* Return to zero for current sense ADC , */\
{ 0x8490, "cs_adc_slowdel"}, /* Select delay for current sense ADC (internal decision circuitry), */\
{ 0x8510, "cs_classd_tran_skip"}, /* Skip current sense connection during a classD amplifier transition, */\
{ 0x8530, "cs_inn_short"}, /* Short current sense negative to common mode , */\
{ 0x8540, "cs_inp_short"}, /* Short current sense positive to common mode , */\
{ 0x8550, "cs_ldo_bypass"}, /* Bypass current sense LDO , */\
{ 0x8560, "cs_ldo_pulldown"}, /* Pull down current sense LDO, only valid if left_enbl_cs_ldo is high, */\
{ 0x8574, "cs_ldo_voset"}, /* Current sense LDO voltage level setting (two's complement), */\
{ 0x8700, "enbl_cs_adc"}, /* Enable current sense ADC , */\
{ 0x8710, "enbl_cs_inn1"}, /* Enable connection of current sense negative1 , */\
{ 0x8720, "enbl_cs_inn2"}, /* Enable connection of current sense negative2 , */\
{ 0x8730, "enbl_cs_inp1"}, /* Enable connection of current sense positive1 , */\
{ 0x8740, "enbl_cs_inp2"}, /* Enable connection of current sense positive2 , */\
{ 0x8750, "enbl_cs_ldo"}, /* Enable current sense LDO , */\
{ 0x8780, "enbl_cs_vbatldo"}, /* Enable of current sense LDO , */\
{ 0x8790, "enbl_dc_filter"}, /* Control for enabling the DC blocking filter for voltage and current sense, */\
{ 0x8850, "vs_gain_control"}, /* Voltage sense gain control , */\
{ 0x8860, "vs_bypass_gc"}, /* Bypasses the VS gain correction , */\
{ 0x8887, "vs_gain"}, /* Voltage sense gain , */\
{ 0x8c00, "vs_adc_bsoinv"}, /* Bitstream inversion for voltage sense ADC , */\
{ 0x8c40, "vs_adc_nortz"}, /* Return to zero for voltage sense ADC , */\
{ 0x8c90, "vs_adc_slowdel"}, /* Select delay for voltage sense ADC (internal decision circuitry), */\
{ 0x8d30, "vs_inn_short"}, /* Short voltage sense negative to common mode , */\
{ 0x8d40, "vs_inp_short"}, /* Short voltage sense positive to common mode , */\
{ 0x8d50, "vs_ldo_bypass"}, /* Bypass voltage sense LDO , */\
{ 0x8d60, "vs_ldo_pulldown"}, /* Pull down voltage sense LDO, only valid if left_enbl_cs_ldo is high, */\
{ 0x8d74, "vs_ldo_voset"}, /* Voltage sense LDO voltage level setting (two's complement), */\
{ 0x8f00, "enbl_vs_adc"}, /* Enable voltage sense ADC (Direct Control only only others done by manager), */\
{ 0x8f10, "enbl_vs_inn1"}, /* Enable connection of voltage sense negative1 , */\
{ 0x8f20, "enbl_vs_inn2"}, /* Enable connection of voltage sense negative2 , */\
{ 0x8f30, "enbl_vs_inp1"}, /* Enable connection of voltage sense positive1 , */\
{ 0x8f40, "enbl_vs_inp2"}, /* Enable connection of voltage sense positive2 , */\
{ 0x8f50, "enbl_vs_ldo"}, /* Enable voltage sense LDO (Direct Control only only others done by manager), */\
{ 0x8f80, "enbl_vs_vbatldo"}, /* Enable of voltage sense LDO (Direct Control only others done by manager), */\
{ 0xa007, "mtpkey1"}, /* 5Ah, 90d To access KEY1_protected registers (default for engineering), */\
{ 0xa107, "mtpkey2"}, /* MTP KEY2 register , */\
{ 0xa200, "key01_locked"}, /* Indicates KEY1 is locked , */\
{ 0xa210, "key02_locked"}, /* Indicates KEY2 is locked , */\
{ 0xa302, "mtp_man_address_in"}, /* MTP address from I2C register for read/writing mtp in manual single word mode, */\
{ 0xa330, "man_copy_mtp_to_iic"}, /* Start copying single word from mtp to I2C mtp register, */\
{ 0xa340, "man_copy_iic_to_mtp"}, /* Start copying single word from I2C mtp register to mtp, */\
{ 0xa350, "auto_copy_mtp_to_iic"}, /* Start copying all the data from mtp to I2C mtp registers, */\
{ 0xa360, "auto_copy_iic_to_mtp"}, /* Start copying data from I2C mtp registers to mtp , */\
{ 0xa400, "faim_set_clkws"}, /* Sets the faim controller clock wait state register, */\
{ 0xa410, "faim_sel_evenrows"}, /* All even rows of the faim are selected, active high, */\
{ 0xa420, "faim_sel_oddrows"}, /* All odd rows of the faim are selected, all rows in combination with sel_evenrows, */\
{ 0xa430, "faim_program_only"}, /* Skip the erase access at wr_faim command (write-program-marginread), */\
{ 0xa440, "faim_erase_only"}, /* Skip the program access at wr_faim command (write-erase-marginread), */\
{ 0xa50f, "mtp_man_data_out_msb"}, /* MSB word of MTP manual read data , */\
{ 0xa60f, "mtp_man_data_out_lsb"}, /* LSB word of MTP manual read data , */\
{ 0xa70f, "mtp_man_data_in_msb"}, /* MSB word of write data for MTP manual write , */\
{ 0xa80f, "mtp_man_data_in_lsb"}, /* LSB word of write data for MTP manual write , */\
{ 0xb010, "bypass_ocpcounter"}, /* Bypass OCP Counter , */\
{ 0xb020, "bypass_glitchfilter"}, /* Bypass glitch filter , */\
{ 0xb030, "bypass_ovp"}, /* Bypass OVP , */\
{ 0xb040, "bypass_uvp"}, /* Bypass UVP , */\
{ 0xb050, "bypass_otp"}, /* Bypass OTP , */\
{ 0xb060, "bypass_lost_clk"}, /* Bypass lost clock detector , */\
{ 0xb070, "ctrl_vpalarm"}, /* vpalarm (uvp ovp handling) , */\
{ 0xb087, "ocp_threshold"}, /* OCP threshold level , */\
{ 0xb108, "ext_temp"}, /* External temperature (C) , */\
{ 0xb190, "ext_temp_sel"}, /* Select temp Speaker calibration , */\
{ 0xb200, "bypass_ovpglitchfilter"}, /* Bypass glitch filter on over voltage protection signal from analog, */\
{ 0xb210, "enbl_ovp_alarm_state"}, /* Allow manager to go into alarm state when OVP (only when ctrl_vpalarm is 0), */\
{ 0xb220, "amp_in_tristate_when_ovp"}, /* Brings amplifier in tristate when OVP (only when ctrl_enbl_ovp_alarm_state is 0) , */\
{ 0xc000, "use_direct_ctrls"}, /* Direct control to overrule several functions for testing, */\
{ 0xc010, "rst_datapath"}, /* Direct control for datapath reset , */\
{ 0xc020, "rst_cgu"}, /* Direct control for cgu reset , */\
{ 0xc038, "enbl_ref"}, /* Switch on the analog references, each part of the references can be switched on/off individually, */\
{ 0xc0c0, "use_direct_vs_ctrls"}, /* Voltage sense direct control to overrule several functions for testing, */\
{ 0xc0d0, "enbl_ringo"}, /* Enable the ring oscillator for test purpose , */\
{ 0xc0e0, "enbl_pll"}, /* Enables PLL in I2C direct control mode only , */\
{ 0xc0f0, "enbl_fro"}, /* Enables FRO8M in I2C direct control mode only , */\
{ 0xc100, "enbl_tsense"}, /* Temperature sensor enable control - I2C direct mode, */\
{ 0xc110, "tsense_hibias"}, /* Bit to set the biasing in temp sensor to high , */\
{ 0xc120, "enbl_flag_vbg"}, /* Enable flagging of bandgap out of control , */\
{ 0xc20f, "abist_offset"}, /* Offset control for ABIST testing (two's complement), */\
{ 0xc300, "bypasslatch"}, /* Bypass latch , */\
{ 0xc311, "sourcea"}, /* Set OUTA to , */\
{ 0xc331, "sourceb"}, /* Set OUTB to , */\
{ 0xc350, "inverta"}, /* Invert pwma test signal , */\
{ 0xc360, "invertb"}, /* Invert pwmb test signal , */\
{ 0xc376, "pulselength"}, /* Pulse length setting test input for amplifier (PWM clock 2048/4096 Fs), */\
{ 0xc3e0, "tdm_enable_loopback"}, /* TDM loopback test , */\
{ 0xc400, "bst_bypasslatch"}, /* Bypass latch in boost converter , */\
{ 0xc411, "bst_source"}, /* Sets the source of the pwmbst output to boost converter input for testing, */\
{ 0xc430, "bst_invertb"}, /* Invert PWMbst test signal , */\
{ 0xc444, "bst_pulselength"}, /* Pulse length setting test input for boost converter , */\
{ 0xc490, "test_bst_ctrlsthv"}, /* Test mode for boost control stage , */\
{ 0xc4a0, "test_bst_iddq"}, /* IDDQ testing in power stage of boost converter , */\
{ 0xc4b0, "test_bst_rdson"}, /* RDSON testing - boost power stage , */\
{ 0xc4c0, "test_bst_cvi"}, /* CVI testing - boost power stage , */\
{ 0xc4d0, "test_bst_ocp"}, /* Boost OCP. For old OCP (ctrl_reversebst is 0), For new OCP (ctrl_reversebst is 1), */\
{ 0xc4e0, "test_bst_sense"}, /* Test option for the sense NMOS in booster for current mode control., */\
{ 0xc500, "test_cvi"}, /* Analog BIST, switch choose which transistor will be used as current source (also cross coupled sources possible), */\
{ 0xc510, "test_discrete"}, /* Test function noise measurement , */\
{ 0xc520, "test_iddq"}, /* Set the power stages in iddq mode for gate stress., */\
{ 0xc540, "test_rdson"}, /* Analog BIST, switch to enable Rdson measurement , */\
{ 0xc550, "test_sdelta"}, /* Analog BIST, noise test , */\
{ 0xc570, "test_enbl_cs"}, /* Enable for digimux mode of current sense , */\
{ 0xc580, "test_enbl_vs"}, /* Enable for digimux mode of voltage sense , */\
{ 0xc600, "enbl_pwm_dcc"}, /* Enables direct control of pwm duty cycle for DCDC power stage, */\
{ 0xc613, "pwm_dcc_cnt"}, /* Control pwm duty cycle when enbl_pwm_dcc is 1 , */\
{ 0xc650, "enbl_ldo_stress"}, /* Enable stress of internal supply voltages powerstages, */\
{ 0xc707, "digimuxa_sel"}, /* DigimuxA input selection control routed to DATAO (see Digimux list for details), */\
{ 0xc787, "digimuxb_sel"}, /* DigimuxB input selection control routed to INT (see Digimux list for details), */\
{ 0xc807, "digimuxc_sel"}, /* DigimuxC input selection control routed to ADS1 (see Digimux list for details), */\
{ 0xc981, "int_ehs"}, /* Speed/load setting for INT IO cell, clk or data mode range (see SLIMMF IO cell datasheet), */\
{ 0xc9c0, "hs_mode"}, /* I2C high speed mode control , */\
{ 0xca00, "enbl_anamux1"}, /* Enable anamux1 , */\
{ 0xca10, "enbl_anamux2"}, /* Enable anamux2 , */\
{ 0xca20, "enbl_anamux3"}, /* Enable anamux3 , */\
{ 0xca30, "enbl_anamux4"}, /* Enable anamux4 , */\
{ 0xca74, "anamux1"}, /* Anamux selection control - anamux on TEST1 , */\
{ 0xcb04, "anamux2"}, /* Anamux selection control - anamux on TEST2 , */\
{ 0xcb53, "anamux3"}, /* Anamux selection control - anamux on VSN/TEST3 , */\
{ 0xcba3, "anamux4"}, /* Anamux selection control - anamux on VSP/TEST4 , */\
{ 0xcd05, "pll_inseli"}, /* PLL INSELI - PLL direct bandwidth control mode, only with pll_bandsel set to 1, */\
{ 0xcd64, "pll_inselp"}, /* PLL INSELP - PLL direct bandwidth control mode only with pll_bandsel set to 1, */\
{ 0xcdb3, "pll_inselr"}, /* PLL INSELR - PLL direct bandwidth control mode only with pll_bandsel set to 1, */\
{ 0xcdf0, "pll_bandsel"}, /* PLL bandwidth selection control, USE WITH CAUTION , */\
{ 0xce09, "pll_ndec"}, /* PLL NDEC in direct control mode only, use_direct_pll_ctrl set to 1, */\
{ 0xcea0, "pll_mdec_msb"}, /* MSB of PLL MDEC in direct control mode only, use_direct_pll_ctrl set to 1, */\
{ 0xceb0, "pll_bypass"}, /* PLL bypass control during functional mode , */\
{ 0xcec0, "pll_directi"}, /* PLL directi control in direct control mode only, use_direct_pll_ctrl set to 1, */\
{ 0xced0, "pll_directo"}, /* PLL directo control in direct control mode only, use_direct_pll_ctrl set to 1, */\
{ 0xcee0, "pll_frm_clockstable"}, /* PLL FRM clock stable control in direct control mode only, use_direct_pll_ctrl set to 1, */\
{ 0xcef0, "pll_frm"}, /* PLL free running mode control in functional mode , */\
{ 0xcf0f, "pll_mdec_lsb"}, /* Bits 15 to 0 of PLL MDEC in direct control mode, use_direct_pll_ctrl set to 1, */\
{ 0xd006, "pll_pdec"}, /* PLL PDEC in direct control mode only, use_direct_pll_ctrl set to 1, */\
{ 0xd070, "use_direct_pll_ctrl"}, /* Enabled PLL direct control mode, overrules the PLL LUT with I2C register values, */\
{ 0xd090, "pll_limup_off"}, /* PLL up limiter control in PLL direct bandwidth control mode, pll_bandsel set to 1, */\
{ 0xd0a2, "sel_pll_startup_time"}, /* PLL startup time selection control , */\
{ 0xd10f, "tsig_freq_lsb"}, /* Internal sinus test generator frequency control , */\
{ 0xd202, "tsig_freq_msb"}, /* Internal sinus test generator, frequency control msb bits, */\
{ 0xd230, "inject_tsig"}, /* Control bit to switch to internal sinus test generator, */\
{ 0xd283, "tsig_gain"}, /* Test signal gain , */\
{ 0xd300, "adc10_reset"}, /* Reset for ADC10 - I2C direct control mode , */\
{ 0xd311, "adc10_test"}, /* Test mode selection signal for ADC10 - I2C direct control mode, */\
{ 0xd332, "adc10_sel"}, /* Select the input to convert for ADC10 - I2C direct control mode, */\
{ 0xd364, "adc10_prog_sample"}, /* ADC10 program sample setting - I2C direct control mode, */\
{ 0xd3b0, "adc10_enbl"}, /* Enable ADC10 - I2C direct control mode , */\
{ 0xd3c0, "bypass_lp_vbat"}, /* Bypass control for Low pass filter in batt sensor , */\
{ 0xd409, "data_adc10_tempbat"}, /* ADC 10 data output data for testing , */\
{ 0xd507, "ctrl_digtoana_hidden"}, /* Spare digital to analog control bits - Hidden , */\
{ 0xd580, "enbl_clk_out_of_range"}, /* Clock out of range , */\
{ 0xd721, "datao_ehs"}, /* Speed/load setting for DATAO IO cell, clk or data mode range (see SLIMMF IO cell datasheet), */\
{ 0xd740, "bck_ehs"}, /* High-speed and standard/fast mode selection for BCK IO cell (see IIC3V3 IO cell datasheet), */\
{ 0xd750, "datai_ehs"}, /* High-speed and standard/fast mode selection for DATAI IO cell (see IIC3V3 IO cell datasheet), */\
{ 0xd800, "source_in_testmode"}, /* TDM source in test mode (return only current and voltage sense), */\
{ 0xd810, "gainatt_tdm_feedback"}, /* GainAtt feedback to TDM , */\
{ 0xd822, "test_parametric_io"}, /* Test io parametric , */\
{ 0xd861, "test_spare_out1"}, /* Test spare out 1 , */\
{ 0xd880, "bst_dcmbst"}, /* DCM boost , */\
{ 0xd8c3, "test_spare_out2"}, /* Test spare out 1 , */\
{ 0xd900, "enbl_frocal"}, /* Enable FRO calibration , */\
{ 0xd910, "start_fro_calibration"}, /* Start FRO8 Calibration , */\
{ 0xd920, "enbl_irefcal"}, /* Enable IREF calibration , */\
{ 0xd930, "start_iref_calibration"}, /* Start IREF Calibration , */\
{ 0xda00, "fro_calibration_done"}, /* FRO8 Calibration done - Read Only , */\
{ 0xda15, "fro_auto_trim_val"}, /* Calibration value from auto calibration, to be written into MTP - Read Only, */\
{ 0xda80, "iref_calibration_done"}, /* IREF Calibration done - Read Only , */\
{ 0xda94, "iref_auto_trim_val"}, /* Calibration value from auto calibration, to be written into MTP - Read Only, */\
{ 0xdae0, "iref_calibration_error"}, /* IREF Calibration done - Read Only , */\
{ 0xe00f, "sw_profile"}, /* Software profile data , */\
{ 0xe10f, "sw_vstep"}, /* Software vstep information , */\
{ 0xf000, "calibration_onetime"}, /* Calibration schedule , */\
{ 0xf010, "calibr_ron_done"}, /* Calibration Ron executed , */\
{ 0xf020, "calibr_dcdc_api_calibrate"}, /* Calibration current limit DCDC , */\
{ 0xf030, "calibr_dcdc_delta_sign"}, /* Sign bit for delta calibration current limit DCDC , */\
{ 0xf042, "calibr_dcdc_delta"}, /* Calibration delta current limit DCDC , */\
{ 0xf078, "calibr_speaker_info"}, /* Reserved space for allowing customer to store speaker information, */\
{ 0xf105, "calibr_vout_offset"}, /* DCDC offset calibration 2's complement (key1 protected), */\
{ 0xf203, "calibr_gain"}, /* HW gain module (2's complement) , */\
{ 0xf245, "calibr_offset"}, /* Offset for amplifier, HW gain module (2's complement), */\
{ 0xf307, "calibr_gain_vs1"}, /* Voltage sense gain when external voltage sensing input is selected, */\
{ 0xf387, "calibr_gain_vs2"}, /* Voltage sense gain when internal voltage sensing input is selected, */\
{ 0xf407, "vs_trim1"}, /* VS Trimming when external voltage sensing input is selected, */\
{ 0xf487, "vs_trim2"}, /* VS Trimming when internal voltage sensing input is selected, */\
{ 0xf50f, "calibr_R25C_R"}, /* Ron resistance of speaker coil , */\
{ 0xf607, "calibr_gain_cs"}, /* Current sense gain (signed two's complement format), */\
{ 0xf706, "ctrl_offset_a"}, /* Offset of level shifter A , */\
{ 0xf786, "ctrl_offset_b"}, /* Offset of amplifier level shifter B , */\
{ 0xf806, "htol_iic_addr"}, /* 7-bit I2C address to be used during HTOL testing , */\
{ 0xf870, "htol_iic_addr_en"}, /* HTOL I2C address enable control , */\
{ 0xf884, "calibr_temp_offset"}, /* Temperature offset 2's compliment (key1 protected), */\
{ 0xf8d2, "calibr_temp_gain"}, /* Temperature gain 2's compliment (key1 protected) , */\
{ 0xf900, "mtp_lock_dcdcoff_mode"}, /* Disable function dcdcoff_mode , */\
{ 0xf910, "mtp_pll_lut_sel"}, /* PLL lookup table selection control , */\
{ 0xf920, "mtp_lock_bypass_clipper"}, /* Disable function bypass_clipper , */\
{ 0xf930, "mtp_lock_max_dcdc_voltage"}, /* Force Boost in follower mode , */\
{ 0xf943, "calibr_vbg_trim"}, /* Bandgap trimming control , */\
{ 0xf990, "mtp_enbl_pwm_delay_clock_gating"}, /* PWM delay clock auto gating , */\
{ 0xf9a0, "mtp_enbl_ocp_clock_gating"}, /* OCP clock auto gating , */\
{ 0xfa0f, "mtpdataA"}, /* MTPdataA (key1 protected) , */\
{ 0xfb0f, "mtpdataB"}, /* MTPdataB (key1 protected) , */\
{ 0xfc0f, "mtpdataC"}, /* MTPdataC (key1 protected) , */\
{ 0xfd0f, "mtpdataD"}, /* MTPdataD (key1 protected) , */\
{ 0xfe0f, "mtpdataE"}, /* MTPdataE (key1 protected) , */\
{ 0xff05, "fro_trim"}, /* 8 MHz oscillator trim code , */\
{ 0xff61, "fro_shortnwell"}, /* Short 4 or 6 n-well resistors , */\
{ 0xff81, "fro_boost"}, /* Self bias current selection , */\
{ 0xffa4, "calibr_iref_trim"}, /* Trimming control of reference current for OCP , */\
{ 0xffff,"Unknown bitfield enum" } /* not found */\
};
#if 0
enum tfa9873_irq {
tfa9873_irq_stvdds = 0,
tfa9873_irq_stbstoc = 1,
tfa9873_irq_stotds = 2,
tfa9873_irq_stocpr = 3,
tfa9873_irq_stuvds = 4,
tfa9873_irq_stmanalarm = 5,
tfa9873_irq_sttdmer = 6,
tfa9873_irq_stnoclk = 7,
tfa9873_irq_max = 8,
tfa9873_irq_all = -1 /* all irqs */};
#endif//
#define TFA9873_IRQ_NAMETABLE static tfaIrqName_t Tfa9873IrqNames[]= {\
{ 0, "STVDDS"},\
{ 1, "STBSTOC"},\
{ 2, "STOTDS"},\
{ 3, "STOCPR"},\
{ 4, "STUVDS"},\
{ 5, "STMANALARM"},\
{ 6, "STTDMER"},\
{ 7, "STNOCLK"},\
{ 8, "8"},\
};
#endif /* _TFA9873_TFAFIELDNAMES_B0_H */

843
techpack/audio/asoc/codecs/tfa98xx/inc/tfa9874_tfafieldnames.h Executable file
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/*
* Copyright (C) 2014-2020 NXP Semiconductors, All Rights Reserved.
* Copyright 2020 GOODIX
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
*/
/** Filename: tfa9874_tfaFieldnames_last.h
* This file was generated automatically on 09/28/18 at 11:20:52.
* Source file: TFA9874N1C0_DefaultI2CSettings.xlsx
*/
#ifndef _TFA9874_TFAFIELDNAMES_H
#define _TFA9874_TFAFIELDNAMES_H
#define TFA9874_I2CVERSION 1.16
typedef enum Tfa9874BfEnumList {
TFA9874_BF_PWDN = 0x0000, /*!< Powerdown selection */
TFA9874_BF_I2CR = 0x0010, /*!< I2C Reset - Auto clear */
TFA9874_BF_AMPE = 0x0030, /*!< Activate Amplifier */
TFA9874_BF_DCA = 0x0040, /*!< Activate DC-to-DC converter */
TFA9874_BF_INTP = 0x0071, /*!< Interrupt config */
TFA9874_BF_BYPOCP= 0x00b0, /*!< Bypass OCP */
TFA9874_BF_TSTOCP= 0x00c0, /*!< OCP testing control */
TFA9874_BF_MANSCONF= 0x0120, /*!< I2C configured */
TFA9874_BF_MANAOOSC= 0x0140, /*!< Internal osc off at PWDN */
TFA9874_BF_MUTETO= 0x01d0, /*!< Time out SB mute sequence */
TFA9874_BF_OPENMTP= 0x01e0, /*!< Control for FAIM protection */
TFA9874_BF_AUDFS = 0x0203, /*!< Sample rate (fs) */
TFA9874_BF_INPLEV= 0x0240, /*!< TDM output attenuation */
TFA9874_BF_FRACTDEL= 0x0255, /*!< V/I Fractional delay */
TFA9874_BF_REV = 0x030f, /*!< Revision info */
TFA9874_BF_REFCKEXT= 0x0401, /*!< PLL external ref clock */
TFA9874_BF_REFCKSEL= 0x0420, /*!< PLL internal ref clock */
TFA9874_BF_SSFAIME= 0x05c0, /*!< Sub-system FAIM */
TFA9874_BF_AMPOCRT= 0x0802, /*!< Amplifier on-off criteria for shutdown */
TFA9874_BF_VDDS = 0x1000, /*!< POR */
TFA9874_BF_DCOCPOK= 0x1010, /*!< DCDC OCP nmos (sticky register , clear on read) */
TFA9874_BF_OTDS = 0x1020, /*!< OTP alarm (sticky register , clear on read) */
TFA9874_BF_OCDS = 0x1030, /*!< OCP amplifier (sticky register , clear on read) */
TFA9874_BF_UVDS = 0x1040, /*!< UVP alarm (sticky register , clear on read) */
TFA9874_BF_MANALARM= 0x1050, /*!< Alarm state */
TFA9874_BF_TDMERR= 0x1060, /*!< TDM error */
TFA9874_BF_NOCLK = 0x1070, /*!< Lost clock (sticky register , clear on read) */
TFA9874_BF_DCIL = 0x1100, /*!< DCDC current limiting */
TFA9874_BF_DCDCA = 0x1110, /*!< DCDC active (sticky register , clear on read) */
TFA9874_BF_DCHVBAT= 0x1130, /*!< DCDC level 1x */
TFA9874_BF_DCH114= 0x1140, /*!< DCDC level 1.14x */
TFA9874_BF_DCH107= 0x1150, /*!< DCDC level 1.07x */
TFA9874_BF_PLLS = 0x1160, /*!< PLL lock */
TFA9874_BF_CLKS = 0x1170, /*!< Clocks stable */
TFA9874_BF_TDMLUTER= 0x1180, /*!< TDM LUT error */
TFA9874_BF_TDMSTAT= 0x1192, /*!< TDM status bits */
TFA9874_BF_MTPB = 0x11c0, /*!< MTP busy */
TFA9874_BF_SWS = 0x11d0, /*!< Amplifier engage */
TFA9874_BF_AMPS = 0x11e0, /*!< Amplifier enable */
TFA9874_BF_AREFS = 0x11f0, /*!< References enable */
TFA9874_BF_OCPOAP= 0x1300, /*!< OCPOK pmos A */
TFA9874_BF_OCPOAN= 0x1310, /*!< OCPOK nmos A */
TFA9874_BF_OCPOBP= 0x1320, /*!< OCPOK pmos B */
TFA9874_BF_OCPOBN= 0x1330, /*!< OCPOK nmos B */
TFA9874_BF_OVDS = 0x1380, /*!< OVP alarm */
TFA9874_BF_CLIPS = 0x1390, /*!< Amplifier clipping */
TFA9874_BF_ADCCR = 0x13a0, /*!< Control ADC */
TFA9874_BF_MANWAIT1= 0x13c0, /*!< Wait HW I2C settings */
TFA9874_BF_MANMUTE= 0x13e0, /*!< Audio mute sequence */
TFA9874_BF_MANOPER= 0x13f0, /*!< Operating state */
TFA9874_BF_CLKOOR= 0x1420, /*!< External clock status */
TFA9874_BF_MANSTATE= 0x1433, /*!< Device manager status */
TFA9874_BF_DCMODE= 0x1471, /*!< DCDC mode status bits */
TFA9874_BF_BATS = 0x1509, /*!< Battery voltage (V) */
TFA9874_BF_TEMPS = 0x1608, /*!< IC Temperature (C) */
TFA9874_BF_VDDPS = 0x1709, /*!< IC VDDP voltage ( 1023*VDDP/13 V) */
TFA9874_BF_TDME = 0x2040, /*!< Enable interface */
TFA9874_BF_TDMMODE= 0x2050, /*!< Slave/master */
TFA9874_BF_TDMCLINV= 0x2060, /*!< Reception data to BCK clock */
TFA9874_BF_TDMFSLN= 0x2073, /*!< FS length (master mode only) */
TFA9874_BF_TDMFSPOL= 0x20b0, /*!< FS polarity */
TFA9874_BF_TDMNBCK= 0x20c3, /*!< N-BCK's in FS */
TFA9874_BF_TDMSLOTS= 0x2103, /*!< N-slots in Frame */
TFA9874_BF_TDMSLLN= 0x2144, /*!< N-bits in slot */
TFA9874_BF_TDMBRMG= 0x2194, /*!< N-bits remaining */
TFA9874_BF_TDMDEL= 0x21e0, /*!< data delay to FS */
TFA9874_BF_TDMADJ= 0x21f0, /*!< data adjustment */
TFA9874_BF_TDMOOMP= 0x2201, /*!< Received audio compression */
TFA9874_BF_TDMSSIZE= 0x2224, /*!< Sample size per slot */
TFA9874_BF_TDMTXDFO= 0x2271, /*!< Format unused bits */
TFA9874_BF_TDMTXUS0= 0x2291, /*!< Format unused slots DATAO */
TFA9874_BF_TDMSPKE= 0x2300, /*!< Control audio tdm channel in 0 (spkr + dcdc) */
TFA9874_BF_TDMDCE= 0x2310, /*!< Control audio tdm channel in 1 (dcdc) */
TFA9874_BF_TDMCSE= 0x2330, /*!< current sense vbat temperature and vddp feedback */
TFA9874_BF_TDMVSE= 0x2340, /*!< Voltage sense vbat temperature and vddp feedback */
TFA9874_BF_TDMSPKS= 0x2603, /*!< tdm slot for sink 0 (speaker + dcdc) */
TFA9874_BF_TDMDCS= 0x2643, /*!< tdm slot for sink 1 (dcdc) */
TFA9874_BF_TDMCSS= 0x26c3, /*!< Slot Position of current sense vbat temperature and vddp feedback */
TFA9874_BF_TDMVSS= 0x2703, /*!< Slot Position of Voltage sense vbat temperature and vddp feedback */
TFA9874_BF_ISTVDDS= 0x4000, /*!< Status POR */
TFA9874_BF_ISTBSTOC= 0x4010, /*!< Status DCDC OCP */
TFA9874_BF_ISTOTDS= 0x4020, /*!< Status OTP alarm */
TFA9874_BF_ISTOCPR= 0x4030, /*!< Status ocp alarm */
TFA9874_BF_ISTUVDS= 0x4040, /*!< Status UVP alarm */
TFA9874_BF_ISTMANALARM= 0x4050, /*!< Status nanager Alarm state */
TFA9874_BF_ISTTDMER= 0x4060, /*!< Status tdm error */
TFA9874_BF_ISTNOCLK= 0x4070, /*!< Status lost clock */
TFA9874_BF_ICLVDDS= 0x4400, /*!< Clear POR */
TFA9874_BF_ICLBSTOC= 0x4410, /*!< Clear DCDC OCP */
TFA9874_BF_ICLOTDS= 0x4420, /*!< Clear OTP alarm */
TFA9874_BF_ICLOCPR= 0x4430, /*!< Clear ocp alarm */
TFA9874_BF_ICLUVDS= 0x4440, /*!< Clear UVP alarm */
TFA9874_BF_ICLMANALARM= 0x4450, /*!< clear nanager Alarm state */
TFA9874_BF_ICLTDMER= 0x4460, /*!< Clear tdm error */
TFA9874_BF_ICLNOCLK= 0x4470, /*!< Clear lost clk */
TFA9874_BF_IEVDDS= 0x4800, /*!< Enable por */
TFA9874_BF_IEBSTOC= 0x4810, /*!< Enable DCDC OCP */
TFA9874_BF_IEOTDS= 0x4820, /*!< Enable OTP alarm */
TFA9874_BF_IEOCPR= 0x4830, /*!< Enable ocp alarm */
TFA9874_BF_IEUVDS= 0x4840, /*!< Enable UVP alarm */
TFA9874_BF_IEMANALARM= 0x4850, /*!< Enable nanager Alarm state */
TFA9874_BF_IETDMER= 0x4860, /*!< Enable tdm error */
TFA9874_BF_IENOCLK= 0x4870, /*!< Enable lost clk */
TFA9874_BF_IPOVDDS= 0x4c00, /*!< Polarity por */
TFA9874_BF_IPOBSTOC= 0x4c10, /*!< Polarity DCDC OCP */
TFA9874_BF_IPOOTDS= 0x4c20, /*!< Polarity OTP alarm */
TFA9874_BF_IPOOCPR= 0x4c30, /*!< Polarity ocp alarm */
TFA9874_BF_IPOUVDS= 0x4c40, /*!< Polarity UVP alarm */
TFA9874_BF_IPOMANALARM= 0x4c50, /*!< Polarity nanager Alarm state */
TFA9874_BF_IPOTDMER= 0x4c60, /*!< Polarity tdm error */
TFA9874_BF_IPONOCLK= 0x4c70, /*!< Polarity lost clk */
TFA9874_BF_BSSCR = 0x5001, /*!< Battery Safeguard attack time */
TFA9874_BF_BSST = 0x5023, /*!< Battery Safeguard threshold voltage level */
TFA9874_BF_BSSRL = 0x5061, /*!< Battery Safeguard maximum reduction */
TFA9874_BF_VBATFLTL= 0x5080, /*!< vbat filter limit */
TFA9874_BF_BSSR = 0x50e0, /*!< Battery voltage read out */
TFA9874_BF_BSSBY = 0x50f0, /*!< Bypass battery safeguard */
TFA9874_BF_BSSS = 0x5100, /*!< Vbat prot steepness */
TFA9874_BF_HPFBYP= 0x5150, /*!< Bypass HPF */
TFA9874_BF_DPSA = 0x5170, /*!< Enable DPSA */
TFA9874_BF_CLIPCTRL= 0x5222, /*!< Clip control setting */
TFA9874_BF_AMPGAIN= 0x5257, /*!< Amplifier gain */
TFA9874_BF_SLOPEE= 0x52d0, /*!< Enables slope control */
TFA9874_BF_SLOPESET= 0x52e0, /*!< Slope speed setting (bin. coded) */
TFA9874_BF_TDMDCG= 0x6123, /*!< Second channel gain in case of stereo using a single coil. (Total gain depending on INPLEV). (In case of mono OR stereo using 2 separate DCDC channel 1 should be disabled using TDMDCE) */
TFA9874_BF_TDMSPKG= 0x6163, /*!< Total gain depending on INPLEV setting (channel 0) */
TFA9874_BF_LNMODE= 0x62e1, /*!< ctrl select mode */
TFA9874_BF_LPM1MODE= 0x64e1, /*!< low power mode control */
TFA9874_BF_TDMSRCMAP= 0x6802, /*!< tdm source mapping */
TFA9874_BF_TDMSRCAS= 0x6831, /*!< Sensed value A */
TFA9874_BF_TDMSRCBS= 0x6851, /*!< Sensed value B */
TFA9874_BF_TDMSRCACLIP= 0x6871, /*!< clip information (analog /digital) for source0 */
TFA9874_BF_TDMSRCBCLIP= 0x6891, /*!< clip information (analog /digital) for source1 */
TFA9874_BF_LP1 = 0x6e10, /*!< low power mode 1 detection */
TFA9874_BF_LA = 0x6e20, /*!< low amplitude detection */
TFA9874_BF_VDDPH = 0x6e30, /*!< vddp greater than vbat */
TFA9874_BF_DELCURCOMP= 0x6f02, /*!< delay to allign compensation signal with current sense signal */
TFA9874_BF_SIGCURCOMP= 0x6f40, /*!< polarity of compensation for current sense */
TFA9874_BF_ENCURCOMP= 0x6f50, /*!< enable current sense compensation */
TFA9874_BF_LVLCLPPWM= 0x6f72, /*!< set the amount of pwm pulse that may be skipped before clip-flag is triggered */
TFA9874_BF_DCMCC = 0x7033, /*!< Max coil current */
TFA9874_BF_DCCV = 0x7071, /*!< Slope compensation current, represents LxF (inductance x frequency) value */
TFA9874_BF_DCIE = 0x7090, /*!< Adaptive boost mode */
TFA9874_BF_DCSR = 0x70a0, /*!< Soft ramp up/down */
TFA9874_BF_DCDIS = 0x70e0, /*!< DCDC on/off */
TFA9874_BF_DCPWM = 0x70f0, /*!< DCDC PWM only mode */
TFA9874_BF_DCTRACK= 0x7430, /*!< Boost algorithm selection, effective only when boost_intelligent is set to 1 */
TFA9874_BF_DCTRIP= 0x7444, /*!< 1st Adaptive boost trip levels, effective only when DCIE is set to 1 */
TFA9874_BF_DCHOLD= 0x7494, /*!< Hold time for DCDC booster, effective only when boost_intelligent is set to 1 */
TFA9874_BF_DCINT = 0x74e0, /*!< Selection of data for adaptive boost algorithm, effective only when boost_intelligent is set to 1 */
TFA9874_BF_DCTRIP2= 0x7534, /*!< 2nd Adaptive boost trip levels, effective only when DCIE is set to 1 */
TFA9874_BF_DCTRIPT= 0x7584, /*!< Track Adaptive boost trip levels, effective only when boost_intelligent is set to 1 */
TFA9874_BF_DCTRIPHYSTE= 0x75f0, /*!< Enable hysteresis on booster trip levels */
TFA9874_BF_DCVOF = 0x7635, /*!< First boost voltage level */
TFA9874_BF_DCVOS = 0x7695, /*!< Second boost voltage level */
TFA9874_BF_MTPK = 0xa107, /*!< MTP KEY2 register */
TFA9874_BF_KEY1LOCKED= 0xa200, /*!< Indicates KEY1 is locked */
TFA9874_BF_KEY2LOCKED= 0xa210, /*!< Indicates KEY2 is locked */
TFA9874_BF_CIMTP = 0xa360, /*!< Start copying data from I2C mtp registers to mtp */
TFA9874_BF_MTPRDMSB= 0xa50f, /*!< MSB word of MTP manual read data */
TFA9874_BF_MTPRDLSB= 0xa60f, /*!< LSB word of MTP manual read data */
TFA9874_BF_EXTTS = 0xb108, /*!< External temperature (C) */
TFA9874_BF_TROS = 0xb190, /*!< Select temp Speaker calibration */
TFA9874_BF_SWPROFIL= 0xee0f, /*!< Software profile data */
TFA9874_BF_SWVSTEP= 0xef0f, /*!< Software vstep information */
TFA9874_BF_MTPOTC= 0xf000, /*!< Calibration schedule */
TFA9874_BF_MTPEX = 0xf010, /*!< Calibration Ron executed */
TFA9874_BF_DCMCCAPI= 0xf020, /*!< Calibration current limit DCDC */
TFA9874_BF_DCMCCSB= 0xf030, /*!< Sign bit for delta calibration current limit DCDC */
TFA9874_BF_USERDEF= 0xf042, /*!< Calibration delta current limit DCDC */
TFA9874_BF_CUSTINFO= 0xf078, /*!< Reserved space for allowing customer to store speaker information */
TFA9874_BF_R25C = 0xf50f, /*!< Ron resistance of speaker coil */
} Tfa9874BfEnumList_t;
#define TFA9874_NAMETABLE static tfaBfName_t Tfa9874DatasheetNames[]= {\
{ 0x0, "PWDN"}, /* Powerdown selection , */\
{ 0x10, "I2CR"}, /* I2C Reset - Auto clear , */\
{ 0x30, "AMPE"}, /* Activate Amplifier , */\
{ 0x40, "DCA"}, /* Activate DC-to-DC converter , */\
{ 0x71, "INTP"}, /* Interrupt config , */\
{ 0xb0, "BYPOCP"}, /* Bypass OCP , */\
{ 0xc0, "TSTOCP"}, /* OCP testing control , */\
{ 0x120, "MANSCONF"}, /* I2C configured , */\
{ 0x140, "MANAOOSC"}, /* Internal osc off at PWDN , */\
{ 0x1d0, "MUTETO"}, /* Time out SB mute sequence , */\
{ 0x1e0, "OPENMTP"}, /* Control for FAIM protection , */\
{ 0x203, "AUDFS"}, /* Sample rate (fs) , */\
{ 0x240, "INPLEV"}, /* TDM output attenuation , */\
{ 0x255, "FRACTDEL"}, /* V/I Fractional delay , */\
{ 0x30f, "REV"}, /* Revision info , */\
{ 0x401, "REFCKEXT"}, /* PLL external ref clock , */\
{ 0x420, "REFCKSEL"}, /* PLL internal ref clock , */\
{ 0x5c0, "SSFAIME"}, /* Sub-system FAIM , */\
{ 0x802, "AMPOCRT"}, /* Amplifier on-off criteria for shutdown , */\
{ 0x1000, "VDDS"}, /* POR , */\
{ 0x1010, "DCOCPOK"}, /* DCDC OCP nmos (sticky register , clear on read) , */\
{ 0x1020, "OTDS"}, /* OTP alarm (sticky register , clear on read) , */\
{ 0x1030, "OCDS"}, /* OCP amplifier (sticky register , clear on read), */\
{ 0x1040, "UVDS"}, /* UVP alarm (sticky register , clear on read) , */\
{ 0x1050, "MANALARM"}, /* Alarm state , */\
{ 0x1060, "TDMERR"}, /* TDM error , */\
{ 0x1070, "NOCLK"}, /* Lost clock (sticky register , clear on read) , */\
{ 0x1100, "DCIL"}, /* DCDC current limiting , */\
{ 0x1110, "DCDCA"}, /* DCDC active (sticky register , clear on read) , */\
{ 0x1130, "DCHVBAT"}, /* DCDC level 1x , */\
{ 0x1140, "DCH114"}, /* DCDC level 1.14x , */\
{ 0x1150, "DCH107"}, /* DCDC level 1.07x , */\
{ 0x1160, "PLLS"}, /* PLL lock , */\
{ 0x1170, "CLKS"}, /* Clocks stable , */\
{ 0x1180, "TDMLUTER"}, /* TDM LUT error , */\
{ 0x1192, "TDMSTAT"}, /* TDM status bits , */\
{ 0x11c0, "MTPB"}, /* MTP busy , */\
{ 0x11d0, "SWS"}, /* Amplifier engage , */\
{ 0x11e0, "AMPS"}, /* Amplifier enable , */\
{ 0x11f0, "AREFS"}, /* References enable , */\
{ 0x1300, "OCPOAP"}, /* OCPOK pmos A , */\
{ 0x1310, "OCPOAN"}, /* OCPOK nmos A , */\
{ 0x1320, "OCPOBP"}, /* OCPOK pmos B , */\
{ 0x1330, "OCPOBN"}, /* OCPOK nmos B , */\
{ 0x1380, "OVDS"}, /* OVP alarm , */\
{ 0x1390, "CLIPS"}, /* Amplifier clipping , */\
{ 0x13a0, "ADCCR"}, /* Control ADC , */\
{ 0x13c0, "MANWAIT1"}, /* Wait HW I2C settings , */\
{ 0x13e0, "MANMUTE"}, /* Audio mute sequence , */\
{ 0x13f0, "MANOPER"}, /* Operating state , */\
{ 0x1420, "CLKOOR"}, /* External clock status , */\
{ 0x1433, "MANSTATE"}, /* Device manager status , */\
{ 0x1471, "DCMODE"}, /* DCDC mode status bits , */\
{ 0x1509, "BATS"}, /* Battery voltage (V) , */\
{ 0x1608, "TEMPS"}, /* IC Temperature (C) , */\
{ 0x1709, "VDDPS"}, /* IC VDDP voltage ( 1023*VDDP/13 V) , */\
{ 0x2040, "TDME"}, /* Enable interface , */\
{ 0x2050, "TDMMODE"}, /* Slave/master , */\
{ 0x2060, "TDMCLINV"}, /* Reception data to BCK clock , */\
{ 0x2073, "TDMFSLN"}, /* FS length (master mode only) , */\
{ 0x20b0, "TDMFSPOL"}, /* FS polarity , */\
{ 0x20c3, "TDMNBCK"}, /* N-BCK's in FS , */\
{ 0x2103, "TDMSLOTS"}, /* N-slots in Frame , */\
{ 0x2144, "TDMSLLN"}, /* N-bits in slot , */\
{ 0x2194, "TDMBRMG"}, /* N-bits remaining , */\
{ 0x21e0, "TDMDEL"}, /* data delay to FS , */\
{ 0x21f0, "TDMADJ"}, /* data adjustment , */\
{ 0x2201, "TDMOOMP"}, /* Received audio compression , */\
{ 0x2224, "TDMSSIZE"}, /* Sample size per slot , */\
{ 0x2271, "TDMTXDFO"}, /* Format unused bits , */\
{ 0x2291, "TDMTXUS0"}, /* Format unused slots DATAO , */\
{ 0x2300, "TDMSPKE"}, /* Control audio tdm channel in 0 (spkr + dcdc) , */\
{ 0x2310, "TDMDCE"}, /* Control audio tdm channel in 1 (dcdc) , */\
{ 0x2330, "TDMCSE"}, /* current sense vbat temperature and vddp feedback , */\
{ 0x2340, "TDMVSE"}, /* Voltage sense vbat temperature and vddp feedback , */\
{ 0x2603, "TDMSPKS"}, /* tdm slot for sink 0 (speaker + dcdc) , */\
{ 0x2643, "TDMDCS"}, /* tdm slot for sink 1 (dcdc) , */\
{ 0x26c3, "TDMCSS"}, /* Slot Position of current sense vbat temperature and vddp feedback, */\
{ 0x2703, "TDMVSS"}, /* Slot Position of Voltage sense vbat temperature and vddp feedback, */\
{ 0x4000, "ISTVDDS"}, /* Status POR , */\
{ 0x4010, "ISTBSTOC"}, /* Status DCDC OCP , */\
{ 0x4020, "ISTOTDS"}, /* Status OTP alarm , */\
{ 0x4030, "ISTOCPR"}, /* Status ocp alarm , */\
{ 0x4040, "ISTUVDS"}, /* Status UVP alarm , */\
{ 0x4050, "ISTMANALARM"}, /* Status nanager Alarm state , */\
{ 0x4060, "ISTTDMER"}, /* Status tdm error , */\
{ 0x4070, "ISTNOCLK"}, /* Status lost clock , */\
{ 0x4400, "ICLVDDS"}, /* Clear POR , */\
{ 0x4410, "ICLBSTOC"}, /* Clear DCDC OCP , */\
{ 0x4420, "ICLOTDS"}, /* Clear OTP alarm , */\
{ 0x4430, "ICLOCPR"}, /* Clear ocp alarm , */\
{ 0x4440, "ICLUVDS"}, /* Clear UVP alarm , */\
{ 0x4450, "ICLMANALARM"}, /* clear nanager Alarm state , */\
{ 0x4460, "ICLTDMER"}, /* Clear tdm error , */\
{ 0x4470, "ICLNOCLK"}, /* Clear lost clk , */\
{ 0x4800, "IEVDDS"}, /* Enable por , */\
{ 0x4810, "IEBSTOC"}, /* Enable DCDC OCP , */\
{ 0x4820, "IEOTDS"}, /* Enable OTP alarm , */\
{ 0x4830, "IEOCPR"}, /* Enable ocp alarm , */\
{ 0x4840, "IEUVDS"}, /* Enable UVP alarm , */\
{ 0x4850, "IEMANALARM"}, /* Enable nanager Alarm state , */\
{ 0x4860, "IETDMER"}, /* Enable tdm error , */\
{ 0x4870, "IENOCLK"}, /* Enable lost clk , */\
{ 0x4c00, "IPOVDDS"}, /* Polarity por , */\
{ 0x4c10, "IPOBSTOC"}, /* Polarity DCDC OCP , */\
{ 0x4c20, "IPOOTDS"}, /* Polarity OTP alarm , */\
{ 0x4c30, "IPOOCPR"}, /* Polarity ocp alarm , */\
{ 0x4c40, "IPOUVDS"}, /* Polarity UVP alarm , */\
{ 0x4c50, "IPOMANALARM"}, /* Polarity nanager Alarm state , */\
{ 0x4c60, "IPOTDMER"}, /* Polarity tdm error , */\
{ 0x4c70, "IPONOCLK"}, /* Polarity lost clk , */\
{ 0x5001, "BSSCR"}, /* Battery Safeguard attack time , */\
{ 0x5023, "BSST"}, /* Battery Safeguard threshold voltage level , */\
{ 0x5061, "BSSRL"}, /* Battery Safeguard maximum reduction , */\
{ 0x5080, "VBATFLTL"}, /* vbat filter limit , */\
{ 0x50e0, "BSSR"}, /* Battery voltage read out , */\
{ 0x50f0, "BSSBY"}, /* Bypass battery safeguard , */\
{ 0x5100, "BSSS"}, /* Vbat prot steepness , */\
{ 0x5150, "HPFBYP"}, /* Bypass HPF , */\
{ 0x5170, "DPSA"}, /* Enable DPSA , */\
{ 0x5222, "CLIPCTRL"}, /* Clip control setting , */\
{ 0x5257, "AMPGAIN"}, /* Amplifier gain , */\
{ 0x52d0, "SLOPEE"}, /* Enables slope control , */\
{ 0x52e0, "SLOPESET"}, /* Slope speed setting (bin. coded) , */\
{ 0x6123, "TDMDCG"}, /* Second channel gain in case of stereo using a single coil. (Total gain depending on INPLEV). (In case of mono OR stereo using 2 separate DCDC channel 1 should be disabled using TDMDCE), */\
{ 0x6163, "TDMSPKG"}, /* Total gain depending on INPLEV setting (channel 0), */\
{ 0x62e1, "LNMODE"}, /* ctrl select mode , */\
{ 0x64e1, "LPM1MODE"}, /* low power mode control , */\
{ 0x6802, "TDMSRCMAP"}, /* tdm source mapping , */\
{ 0x6831, "TDMSRCAS"}, /* Sensed value A , */\
{ 0x6851, "TDMSRCBS"}, /* Sensed value B , */\
{ 0x6871, "TDMSRCACLIP"}, /* clip information (analog /digital) for source0 , */\
{ 0x6891, "TDMSRCBCLIP"}, /* clip information (analog /digital) for source1 , */\
{ 0x6e10, "LP1"}, /* low power mode 1 detection , */\
{ 0x6e20, "LA"}, /* low amplitude detection , */\
{ 0x6e30, "VDDPH"}, /* vddp greater than vbat , */\
{ 0x6f02, "DELCURCOMP"}, /* delay to allign compensation signal with current sense signal, */\
{ 0x6f40, "SIGCURCOMP"}, /* polarity of compensation for current sense , */\
{ 0x6f50, "ENCURCOMP"}, /* enable current sense compensation , */\
{ 0x6f72, "LVLCLPPWM"}, /* set the amount of pwm pulse that may be skipped before clip-flag is triggered, */\
{ 0x7033, "DCMCC"}, /* Max coil current , */\
{ 0x7071, "DCCV"}, /* Slope compensation current, represents LxF (inductance x frequency) value , */\
{ 0x7090, "DCIE"}, /* Adaptive boost mode , */\
{ 0x70a0, "DCSR"}, /* Soft ramp up/down , */\
{ 0x70e0, "DCDIS"}, /* DCDC on/off , */\
{ 0x70f0, "DCPWM"}, /* DCDC PWM only mode , */\
{ 0x7430, "DCTRACK"}, /* Boost algorithm selection, effective only when boost_intelligent is set to 1, */\
{ 0x7444, "DCTRIP"}, /* 1st Adaptive boost trip levels, effective only when DCIE is set to 1, */\
{ 0x7494, "DCHOLD"}, /* Hold time for DCDC booster, effective only when boost_intelligent is set to 1, */\
{ 0x74e0, "DCINT"}, /* Selection of data for adaptive boost algorithm, effective only when boost_intelligent is set to 1, */\
{ 0x7534, "DCTRIP2"}, /* 2nd Adaptive boost trip levels, effective only when DCIE is set to 1, */\
{ 0x7584, "DCTRIPT"}, /* Track Adaptive boost trip levels, effective only when boost_intelligent is set to 1, */\
{ 0x75f0, "DCTRIPHYSTE"}, /* Enable hysteresis on booster trip levels , */\
{ 0x7635, "DCVOF"}, /* First boost voltage level , */\
{ 0x7695, "DCVOS"}, /* Second boost voltage level , */\
{ 0xa107, "MTPK"}, /* MTP KEY2 register , */\
{ 0xa200, "KEY1LOCKED"}, /* Indicates KEY1 is locked , */\
{ 0xa210, "KEY2LOCKED"}, /* Indicates KEY2 is locked , */\
{ 0xa360, "CIMTP"}, /* Start copying data from I2C mtp registers to mtp , */\
{ 0xa50f, "MTPRDMSB"}, /* MSB word of MTP manual read data , */\
{ 0xa60f, "MTPRDLSB"}, /* LSB word of MTP manual read data , */\
{ 0xb108, "EXTTS"}, /* External temperature (C) , */\
{ 0xb190, "TROS"}, /* Select temp Speaker calibration , */\
{ 0xee0f, "SWPROFIL"}, /* Software profile data , */\
{ 0xef0f, "SWVSTEP"}, /* Software vstep information , */\
{ 0xf000, "MTPOTC"}, /* Calibration schedule , */\
{ 0xf010, "MTPEX"}, /* Calibration Ron executed , */\
{ 0xf020, "DCMCCAPI"}, /* Calibration current limit DCDC , */\
{ 0xf030, "DCMCCSB"}, /* Sign bit for delta calibration current limit DCDC , */\
{ 0xf042, "USERDEF"}, /* Calibration delta current limit DCDC , */\
{ 0xf078, "CUSTINFO"}, /* Reserved space for allowing customer to store speaker information, */\
{ 0xf50f, "R25C"}, /* Ron resistance of speaker coil , */\
{ 0xffff,"Unknown bitfield enum" } /* not found */\
};
#define TFA9874_BITNAMETABLE static tfaBfName_t Tfa9874BitNames[]= {\
{ 0x0, "powerdown"}, /* Powerdown selection , */\
{ 0x10, "reset"}, /* I2C Reset - Auto clear , */\
{ 0x30, "enbl_amplifier"}, /* Activate Amplifier , */\
{ 0x40, "enbl_boost"}, /* Activate DC-to-DC converter , */\
{ 0x71, "int_pad_io"}, /* Interrupt config , */\
{ 0xb0, "bypass_ocp"}, /* Bypass OCP , */\
{ 0xc0, "test_ocp"}, /* OCP testing control , */\
{ 0x120, "src_set_configured"}, /* I2C configured , */\
{ 0x140, "enbl_osc1m_auto_off"}, /* Internal osc off at PWDN , */\
{ 0x1d0, "disable_mute_time_out"}, /* Time out SB mute sequence , */\
{ 0x1e0, "unprotect_faim"}, /* Control for FAIM protection , */\
{ 0x203, "audio_fs"}, /* Sample rate (fs) , */\
{ 0x240, "input_level"}, /* TDM output attenuation , */\
{ 0x255, "cs_frac_delay"}, /* V/I Fractional delay , */\
{ 0x2d0, "sel_hysteresis"}, /* Select hysteresis for clock range detector , */\
{ 0x30f, "device_rev"}, /* Revision info , */\
{ 0x401, "pll_clkin_sel"}, /* PLL external ref clock , */\
{ 0x420, "pll_clkin_sel_osc"}, /* PLL internal ref clock , */\
{ 0x5c0, "enbl_faim_ss"}, /* Sub-system FAIM , */\
{ 0x802, "ctrl_on2off_criterion"}, /* Amplifier on-off criteria for shutdown , */\
{ 0xe07, "ctrl_digtoana"}, /* Spare control from digital to analog , */\
{ 0xf0f, "hidden_code"}, /* 5A6Bh, 23147d to access registers (default for engineering), */\
{ 0x1000, "flag_por"}, /* POR , */\
{ 0x1010, "flag_bst_ocpok"}, /* DCDC OCP nmos (sticky register , clear on read) , */\
{ 0x1020, "flag_otpok"}, /* OTP alarm (sticky register , clear on read) , */\
{ 0x1030, "flag_ocp_alarm"}, /* OCP amplifier (sticky register , clear on read), */\
{ 0x1040, "flag_uvpok"}, /* UVP alarm (sticky register , clear on read) , */\
{ 0x1050, "flag_man_alarm_state"}, /* Alarm state , */\
{ 0x1060, "flag_tdm_error"}, /* TDM error , */\
{ 0x1070, "flag_lost_clk"}, /* Lost clock (sticky register , clear on read) , */\
{ 0x1100, "flag_bst_bstcur"}, /* DCDC current limiting , */\
{ 0x1110, "flag_bst_hiz"}, /* DCDC active (sticky register , clear on read) , */\
{ 0x1120, "flag_bst_peakcur"}, /* Indicates current is max in DC-to-DC converter , */\
{ 0x1130, "flag_bst_voutcomp"}, /* DCDC level 1x , */\
{ 0x1140, "flag_bst_voutcomp86"}, /* DCDC level 1.14x , */\
{ 0x1150, "flag_bst_voutcomp93"}, /* DCDC level 1.07x , */\
{ 0x1160, "flag_pll_lock"}, /* PLL lock , */\
{ 0x1170, "flag_clocks_stable"}, /* Clocks stable , */\
{ 0x1180, "flag_tdm_lut_error"}, /* TDM LUT error , */\
{ 0x1192, "flag_tdm_status"}, /* TDM status bits , */\
{ 0x11c0, "flag_mtp_busy"}, /* MTP busy , */\
{ 0x11d0, "flag_engage"}, /* Amplifier engage , */\
{ 0x11e0, "flag_enbl_amp"}, /* Amplifier enable , */\
{ 0x11f0, "flag_enbl_ref"}, /* References enable , */\
{ 0x1300, "flag_ocpokap"}, /* OCPOK pmos A , */\
{ 0x1310, "flag_ocpokan"}, /* OCPOK nmos A , */\
{ 0x1320, "flag_ocpokbp"}, /* OCPOK pmos B , */\
{ 0x1330, "flag_ocpokbn"}, /* OCPOK nmos B , */\
{ 0x1380, "flag_ovpok"}, /* OVP alarm , */\
{ 0x1390, "flag_clip"}, /* Amplifier clipping , */\
{ 0x13a0, "flag_adc10_ready"}, /* Control ADC , */\
{ 0x13c0, "flag_man_wait_src_settings"}, /* Wait HW I2C settings , */\
{ 0x13e0, "flag_man_start_mute_audio"}, /* Audio mute sequence , */\
{ 0x13f0, "flag_man_operating_state"}, /* Operating state , */\
{ 0x1420, "flag_clk_out_of_range"}, /* External clock status , */\
{ 0x1433, "man_state"}, /* Device manager status , */\
{ 0x1471, "status_bst_mode"}, /* DCDC mode status bits , */\
{ 0x1509, "bat_adc"}, /* Battery voltage (V) , */\
{ 0x1608, "temp_adc"}, /* IC Temperature (C) , */\
{ 0x1709, "vddp_adc"}, /* IC VDDP voltage ( 1023*VDDP/13 V) , */\
{ 0x2040, "tdm_enable"}, /* Enable interface , */\
{ 0x2050, "tdm_mode"}, /* Slave/master , */\
{ 0x2060, "tdm_clk_inversion"}, /* Reception data to BCK clock , */\
{ 0x2073, "tdm_fs_ws_length"}, /* FS length (master mode only) , */\
{ 0x20b0, "tdm_fs_ws_polarity"}, /* FS polarity , */\
{ 0x20c3, "tdm_nbck"}, /* N-BCK's in FS , */\
{ 0x2103, "tdm_nb_of_slots"}, /* N-slots in Frame , */\
{ 0x2144, "tdm_slot_length"}, /* N-bits in slot , */\
{ 0x2194, "tdm_bits_remaining"}, /* N-bits remaining , */\
{ 0x21e0, "tdm_data_delay"}, /* data delay to FS , */\
{ 0x21f0, "tdm_data_adjustment"}, /* data adjustment , */\
{ 0x2201, "tdm_audio_sample_compression"}, /* Received audio compression , */\
{ 0x2224, "tdm_sample_size"}, /* Sample size per slot , */\
{ 0x2271, "tdm_txdata_format"}, /* Format unused bits , */\
{ 0x2291, "tdm_txdata_format_unused_slot_sd0"}, /* Format unused slots DATAO , */\
{ 0x2300, "tdm_sink0_enable"}, /* Control audio tdm channel in 0 (spkr + dcdc) , */\
{ 0x2310, "tdm_sink1_enable"}, /* Control audio tdm channel in 1 (dcdc) , */\
{ 0x2330, "tdm_source0_enable"}, /* current sense vbat temperature and vddp feedback , */\
{ 0x2340, "tdm_source1_enable"}, /* Voltage sense vbat temperature and vddp feedback , */\
{ 0x2603, "tdm_sink0_slot"}, /* tdm slot for sink 0 (speaker + dcdc) , */\
{ 0x2643, "tdm_sink1_slot"}, /* tdm slot for sink 1 (dcdc) , */\
{ 0x26c3, "tdm_source0_slot"}, /* Slot Position of current sense vbat temperature and vddp feedback, */\
{ 0x2703, "tdm_source1_slot"}, /* Slot Position of Voltage sense vbat temperature and vddp feedback, */\
{ 0x4000, "int_out_flag_por"}, /* Status POR , */\
{ 0x4010, "int_out_flag_bst_ocpok"}, /* Status DCDC OCP , */\
{ 0x4020, "int_out_flag_otpok"}, /* Status OTP alarm , */\
{ 0x4030, "int_out_flag_ocp_alarm"}, /* Status ocp alarm , */\
{ 0x4040, "int_out_flag_uvpok"}, /* Status UVP alarm , */\
{ 0x4050, "int_out_flag_man_alarm_state"}, /* Status nanager Alarm state , */\
{ 0x4060, "int_out_flag_tdm_error"}, /* Status tdm error , */\
{ 0x4070, "int_out_flag_lost_clk"}, /* Status lost clock , */\
{ 0x4400, "int_in_flag_por"}, /* Clear POR , */\
{ 0x4410, "int_in_flag_bst_ocpok"}, /* Clear DCDC OCP , */\
{ 0x4420, "int_in_flag_otpok"}, /* Clear OTP alarm , */\
{ 0x4430, "int_in_flag_ocp_alarm"}, /* Clear ocp alarm , */\
{ 0x4440, "int_in_flag_uvpok"}, /* Clear UVP alarm , */\
{ 0x4450, "int_in_flag_man_alarm_state"}, /* clear nanager Alarm state , */\
{ 0x4460, "int_in_flag_tdm_error"}, /* Clear tdm error , */\
{ 0x4470, "int_in_flag_lost_clk"}, /* Clear lost clk , */\
{ 0x4800, "int_enable_flag_por"}, /* Enable por , */\
{ 0x4810, "int_enable_flag_bst_ocpok"}, /* Enable DCDC OCP , */\
{ 0x4820, "int_enable_flag_otpok"}, /* Enable OTP alarm , */\
{ 0x4830, "int_enable_flag_ocp_alarm"}, /* Enable ocp alarm , */\
{ 0x4840, "int_enable_flag_uvpok"}, /* Enable UVP alarm , */\
{ 0x4850, "int_enable_flag_man_alarm_state"}, /* Enable nanager Alarm state , */\
{ 0x4860, "int_enable_flag_tdm_error"}, /* Enable tdm error , */\
{ 0x4870, "int_enable_flag_lost_clk"}, /* Enable lost clk , */\
{ 0x4c00, "int_polarity_flag_por"}, /* Polarity por , */\
{ 0x4c10, "int_polarity_flag_bst_ocpok"}, /* Polarity DCDC OCP , */\
{ 0x4c20, "int_polarity_flag_otpok"}, /* Polarity OTP alarm , */\
{ 0x4c30, "int_polarity_flag_ocp_alarm"}, /* Polarity ocp alarm , */\
{ 0x4c40, "int_polarity_flag_uvpok"}, /* Polarity UVP alarm , */\
{ 0x4c50, "int_polarity_flag_man_alarm_state"}, /* Polarity nanager Alarm state , */\
{ 0x4c60, "int_polarity_flag_tdm_error"}, /* Polarity tdm error , */\
{ 0x4c70, "int_polarity_flag_lost_clk"}, /* Polarity lost clk , */\
{ 0x5001, "vbat_prot_attack_time"}, /* Battery Safeguard attack time , */\
{ 0x5023, "vbat_prot_thlevel"}, /* Battery Safeguard threshold voltage level , */\
{ 0x5061, "vbat_prot_max_reduct"}, /* Battery Safeguard maximum reduction , */\
{ 0x5080, "vbat_flt_limit"}, /* vbat filter limit , */\
{ 0x50d0, "rst_min_vbat"}, /* Reset clipper - Auto clear , */\
{ 0x50e0, "sel_vbat"}, /* Battery voltage read out , */\
{ 0x50f0, "bypass_clipper"}, /* Bypass battery safeguard , */\
{ 0x5100, "batsense_steepness"}, /* Vbat prot steepness , */\
{ 0x5150, "bypass_hp"}, /* Bypass HPF , */\
{ 0x5170, "enbl_dpsa"}, /* Enable DPSA , */\
{ 0x5222, "ctrl_cc"}, /* Clip control setting , */\
{ 0x5257, "gain"}, /* Amplifier gain , */\
{ 0x52d0, "ctrl_slopectrl"}, /* Enables slope control , */\
{ 0x52e0, "ctrl_slope"}, /* Slope speed setting (bin. coded) , */\
{ 0x5301, "dpsa_level"}, /* DPSA threshold levels , */\
{ 0x5321, "dpsa_release"}, /* DPSA Release time , */\
{ 0x5340, "clipfast"}, /* Clock selection for HW clipper for Battery Safeguard, */\
{ 0x5350, "bypass_lp"}, /* Bypass the low power filter inside temperature sensor, */\
{ 0x5400, "first_order_mode"}, /* Overrule to 1st order mode of control stage when clipping, */\
{ 0x5410, "bypass_ctrlloop"}, /* Switch amplifier into open loop configuration , */\
{ 0x5430, "icomp_engage"}, /* Engage of icomp , */\
{ 0x5440, "ctrl_kickback"}, /* Prevent double pulses of output stage , */\
{ 0x5450, "icomp_engage_overrule"}, /* To overrule the functional icomp_engage signal during validation, */\
{ 0x5503, "ctrl_dem"}, /* Enable DEM icomp and DEM one bit dac , */\
{ 0x5543, "ctrl_dem_mismatch"}, /* Enable DEM icomp mismatch for testing , */\
{ 0x5582, "dpsa_drive"}, /* Drive setting (bin. coded) , */\
{ 0x5690, "sel_pwm_delay_src"}, /* Control for selection for PWM delay line source , */\
{ 0x56a1, "enbl_odd_up_even_down"}, /* Control for PWM reference sawtooth generartion , */\
{ 0x570a, "enbl_amp"}, /* Switch on the class-D power sections, each part of the analog sections can be switched on/off individually, */\
{ 0x57b0, "enbl_engage"}, /* Enables/engage power stage and control loop , */\
{ 0x57c0, "enbl_engage_pst"}, /* Enables/engage power stage and control loop , */\
{ 0x5810, "hard_mute"}, /* Hard mute - PWM , */\
{ 0x5820, "pwm_shape"}, /* PWM shape , */\
{ 0x5844, "pwm_delay"}, /* PWM delay bits to set the delay, clockd is 1/(k*2048*fs), */\
{ 0x5890, "reclock_pwm"}, /* Reclock the pwm signal inside analog , */\
{ 0x58a0, "reclock_voltsense"}, /* Reclock the voltage sense pwm signal , */\
{ 0x58c0, "enbl_pwm_phase_shift"}, /* Control for pwm phase shift , */\
{ 0x6123, "ctrl_attl"}, /* Second channel gain in case of stereo using a single coil. (Total gain depending on INPLEV). (In case of mono OR stereo using 2 separate DCDC channel 1 should be disabled using TDMDCE), */\
{ 0x6163, "ctrl_attr"}, /* Total gain depending on INPLEV setting (channel 0), */\
{ 0x6265, "zero_lvl"}, /* low noise gain switch zero trigger level , */\
{ 0x62c1, "ctrl_fb_resistor"}, /* Select amplifier feedback resistor connection , */\
{ 0x62e1, "lownoisegain_mode"}, /* ctrl select mode , */\
{ 0x6305, "threshold_lvl"}, /* low noise gain switch trigger level , */\
{ 0x6365, "hold_time"}, /* ctrl hold time before low audio is reckoned to be low audio, */\
{ 0x6405, "lpm1_cal_offset"}, /* low power mode1 detector ctrl cal_offset from gain module , */\
{ 0x6465, "lpm1_zero_lvl"}, /* low power mode1 zero crossing detection level , */\
{ 0x64e1, "lpm1_mode"}, /* low power mode control , */\
{ 0x6505, "lpm1_threshold_lvl"}, /* low power mode1 amplitude trigger level , */\
{ 0x6565, "lpm1_hold_time"}, /* low power mode1 detector ctrl hold time before low audio is reckoned to be low audio, */\
{ 0x65c0, "disable_low_power_mode"}, /* low power mode1 detector control , */\
{ 0x6600, "dcdc_pfm20khz_limit"}, /* DCDC in PFM mode pwm mode is activated each 50us to force a pwm pulse, */\
{ 0x6611, "dcdc_ctrl_maxzercnt"}, /* DCDC. Number of zero current flags to count before going to pfm mode, */\
{ 0x6656, "dcdc_vbat_delta_detect"}, /* Threshold before booster is reacting on a delta Vbat (in PFM mode) by temporarily switching to PWM mode, */\
{ 0x66c0, "dcdc_ignore_vbat"}, /* Ignore an increase on Vbat , */\
{ 0x6700, "enbl_minion"}, /* Enables minion (small) power stage , */\
{ 0x6713, "vth_vddpvbat"}, /* select vddp-vbat thres signal , */\
{ 0x6750, "lpen_vddpvbat"}, /* select vddp-vbat filtred vs unfiltered compare , */\
{ 0x6761, "ctrl_rfb"}, /* Feedback resistor selection - I2C direct mode , */\
{ 0x6802, "tdm_source_mapping"}, /* tdm source mapping , */\
{ 0x6831, "tdm_sourcea_frame_sel"}, /* Sensed value A , */\
{ 0x6851, "tdm_sourceb_frame_sel"}, /* Sensed value B , */\
{ 0x6871, "tdm_source0_clip_sel"}, /* clip information (analog /digital) for source0 , */\
{ 0x6891, "tdm_source1_clip_sel"}, /* clip information (analog /digital) for source1 , */\
{ 0x6a02, "rst_min_vbat_delay"}, /* rst_min_vbat delay (nb fs) , */\
{ 0x6b00, "disable_auto_engage"}, /* disable auto engange , */\
{ 0x6b10, "disable_engage"}, /* disable engange , */\
{ 0x6c02, "ns_hp2ln_criterion"}, /* 0..7 zeroes at ns as threshold to swap from high_power to low_noise, */\
{ 0x6c32, "ns_ln2hp_criterion"}, /* 0..7 zeroes at ns as threshold to swap from low_noise to high_power, */\
{ 0x6c69, "spare_out"}, /* spare_out , */\
{ 0x6d0f, "spare_in"}, /* spare_in , */\
{ 0x6e10, "flag_lp_detect_mode1"}, /* low power mode 1 detection , */\
{ 0x6e20, "flag_low_amplitude"}, /* low amplitude detection , */\
{ 0x6e30, "flag_vddp_gt_vbat"}, /* vddp greater than vbat , */\
{ 0x6f02, "cursense_comp_delay"}, /* delay to allign compensation signal with current sense signal, */\
{ 0x6f40, "cursense_comp_sign"}, /* polarity of compensation for current sense , */\
{ 0x6f50, "enbl_cursense_comp"}, /* enable current sense compensation , */\
{ 0x6f72, "pwms_clip_lvl"}, /* set the amount of pwm pulse that may be skipped before clip-flag is triggered, */\
{ 0x7033, "boost_cur"}, /* Max coil current , */\
{ 0x7071, "bst_slpcmplvl"}, /* Slope compensation current, represents LxF (inductance x frequency) value , */\
{ 0x7090, "boost_intel"}, /* Adaptive boost mode , */\
{ 0x70a0, "boost_speed"}, /* Soft ramp up/down , */\
{ 0x70e0, "dcdcoff_mode"}, /* DCDC on/off , */\
{ 0x70f0, "dcdc_pwmonly"}, /* DCDC PWM only mode , */\
{ 0x7104, "bst_drive"}, /* Binary coded drive setting for boost converter power stage, */\
{ 0x7151, "bst_scalecur"}, /* For testing direct control scale current , */\
{ 0x7174, "bst_slopecur"}, /* For testing direct control slope current , */\
{ 0x71c1, "bst_slope"}, /* Boost slope speed , */\
{ 0x71e0, "bst_bypass_bstcur"}, /* Bypass control for boost current settings , */\
{ 0x71f0, "bst_bypass_bstfoldback"}, /* Bypass control for boost foldback , */\
{ 0x7200, "enbl_bst_engage"}, /* Enable power stage dcdc controller , */\
{ 0x7210, "enbl_bst_hizcom"}, /* Enable hiz comparator , */\
{ 0x7220, "enbl_bst_peak2avg"}, /* Enable boost peak2avg functionality , */\
{ 0x7230, "enbl_bst_peakcur"}, /* Enable peak current , */\
{ 0x7240, "enbl_bst_power"}, /* Enable line of the powerstage , */\
{ 0x7250, "enbl_bst_slopecur"}, /* Enable bit of max-current dac , */\
{ 0x7260, "enbl_bst_voutcomp"}, /* Enable vout comparators , */\
{ 0x7270, "enbl_bst_voutcomp86"}, /* Enable vout-86 comparators , */\
{ 0x7280, "enbl_bst_voutcomp93"}, /* Enable vout-93 comparators , */\
{ 0x7290, "enbl_bst_windac"}, /* Enable window dac , */\
{ 0x72a5, "bst_windac"}, /* for testing direct control windac , */\
{ 0x7300, "boost_alg"}, /* Control for boost adaptive loop gain , */\
{ 0x7311, "boost_loopgain"}, /* DCDC boost loopgain setting , */\
{ 0x7331, "bst_freq"}, /* DCDC boost frequency control , */\
{ 0x7360, "bst_use_new_zercur_detect"}, /* Enable new zero current detection for boost control, */\
{ 0x7430, "boost_track"}, /* Boost algorithm selection, effective only when boost_intelligent is set to 1, */\
{ 0x7444, "boost_trip_lvl_1st"}, /* 1st Adaptive boost trip levels, effective only when DCIE is set to 1, */\
{ 0x7494, "boost_hold_time"}, /* Hold time for DCDC booster, effective only when boost_intelligent is set to 1, */\
{ 0x74e0, "sel_dcdc_envelope_8fs"}, /* Selection of data for adaptive boost algorithm, effective only when boost_intelligent is set to 1, */\
{ 0x74f0, "ignore_flag_voutcomp86"}, /* Determines the maximum PWM frequency be the most efficient in relation to the Booster inductor value, */\
{ 0x7534, "boost_trip_lvl_2nd"}, /* 2nd Adaptive boost trip levels, effective only when DCIE is set to 1, */\
{ 0x7584, "boost_trip_lvl_track"}, /* Track Adaptive boost trip levels, effective only when boost_intelligent is set to 1, */\
{ 0x75f0, "enbl_trip_hyst"}, /* Enable hysteresis on booster trip levels , */\
{ 0x7635, "frst_boost_voltage"}, /* First boost voltage level , */\
{ 0x7695, "scnd_boost_voltage"}, /* Second boost voltage level , */\
{ 0x8001, "sel_clk_cs"}, /* Current sense clock duty cycle control , */\
{ 0x8021, "micadc_speed"}, /* Current sense clock for MiCADC selection - 32/44.1/48 KHz Fs band only, */\
{ 0x8050, "cs_gain_control"}, /* Current sense gain control , */\
{ 0x8060, "cs_bypass_gc"}, /* Bypasses the CS gain correction , */\
{ 0x8087, "cs_gain"}, /* Current sense gain , */\
{ 0x8210, "invertpwm"}, /* Current sense common mode feedback pwm invert control, */\
{ 0x8305, "cs_ktemp"}, /* Current sense temperature compensation trimming (1 - VALUE*TEMP)*signal, */\
{ 0x8364, "cs_ktemp2"}, /* Second order temperature compensation coefficient , */\
{ 0x8400, "cs_adc_bsoinv"}, /* Bitstream inversion for current sense ADC , */\
{ 0x8421, "cs_adc_hifreq"}, /* Frequency mode current sense ADC , */\
{ 0x8440, "cs_adc_nortz"}, /* Return to zero for current sense ADC , */\
{ 0x8453, "cs_adc_offset"}, /* Micadc ADC offset setting , */\
{ 0x8490, "cs_adc_slowdel"}, /* Select delay for current sense ADC (internal decision circuitry), */\
{ 0x84a4, "cs_adc_gain"}, /* Gain setting for current sense ADC (two's complement), */\
{ 0x8500, "cs_resonator_enable"}, /* Enable for resonator to improve SRN , */\
{ 0x8510, "cs_classd_tran_skip"}, /* Skip current sense connection during a classD amplifier transition, */\
{ 0x8530, "cs_inn_short"}, /* Short current sense negative to common mode , */\
{ 0x8540, "cs_inp_short"}, /* Short current sense positive to common mode , */\
{ 0x8550, "cs_ldo_bypass"}, /* Bypass current sense LDO , */\
{ 0x8560, "cs_ldo_pulldown"}, /* Pull down current sense LDO, only valid if left_enbl_cs_ldo is high, */\
{ 0x8574, "cs_ldo_voset"}, /* Current sense LDO voltage level setting (two's complement), */\
{ 0x8700, "enbl_cs_adc"}, /* Enable current sense ADC , */\
{ 0x8710, "enbl_cs_inn1"}, /* Enable connection of current sense negative1 , */\
{ 0x8720, "enbl_cs_inn2"}, /* Enable connection of current sense negative2 , */\
{ 0x8730, "enbl_cs_inp1"}, /* Enable connection of current sense positive1 , */\
{ 0x8740, "enbl_cs_inp2"}, /* Enable connection of current sense positive2 , */\
{ 0x8750, "enbl_cs_ldo"}, /* Enable current sense LDO , */\
{ 0x8780, "enbl_cs_vbatldo"}, /* Enable of current sense LDO , */\
{ 0x8790, "enbl_dc_filter"}, /* Control for enabling the DC blocking filter for voltage and current sense, */\
{ 0x8801, "volsense_pwm_sel"}, /* Voltage sense source selection control , */\
{ 0x8850, "vs_gain_control"}, /* Voltage sense gain control , */\
{ 0x8860, "vs_bypass_gc"}, /* Bypasses the VS gain correction , */\
{ 0x8870, "vs_igen_supply"}, /* Switch internal supply of current generator , */\
{ 0x8887, "vs_gain"}, /* voltage sense gain , */\
{ 0x8c00, "vs_adc_bsoinv"}, /* Bitstream inversion for voltage sense ADC , */\
{ 0x8c40, "vs_adc_nortz"}, /* Return to zero for voltage sense ADC , */\
{ 0x8c90, "vs_adc_slowdel"}, /* Select delay for voltage sense ADC (internal decision circuitry), */\
{ 0x8d10, "vs_classd_tran_skip"}, /* Skip voltage sense connection during a classD amplifier transition, */\
{ 0x8d30, "vs_inn_short"}, /* Short voltage sense negative to common mode , */\
{ 0x8d40, "vs_inp_short"}, /* Short voltage sense positive to common mode , */\
{ 0x8d50, "vs_ldo_bypass"}, /* Bypass voltage sense LDO , */\
{ 0x8d60, "vs_ldo_pulldown"}, /* Pull down voltage sense LDO, only valid if left_enbl_cs_ldo is high, */\
{ 0x8d74, "vs_ldo_voset"}, /* Voltage sense LDO voltage level setting (two's complement), */\
{ 0x8f00, "enbl_vs_adc"}, /* Enable voltage sense ADC (Direct Control only only others done by manager), */\
{ 0x8f10, "enbl_vs_inn1"}, /* Enable connection of voltage sense negative1 , */\
{ 0x8f20, "enbl_vs_inn2"}, /* Enable connection of voltage sense negative2 , */\
{ 0x8f30, "enbl_vs_inp1"}, /* Enable connection of voltage sense positive1 , */\
{ 0x8f40, "enbl_vs_inp2"}, /* Enable connection of voltage sense positive2 , */\
{ 0x8f50, "enbl_vs_ldo"}, /* Enable voltage sense LDO (Direct Control only only others done by manager), */\
{ 0x8f80, "enbl_vs_vbatldo"}, /* Enable of voltage sense LDO (Direct Control only others done by manager), */\
{ 0xa007, "mtpkey1"}, /* 5Ah, 90d To access KEY1_Protected registers (Default for engineering), */\
{ 0xa107, "mtpkey2"}, /* MTP KEY2 register , */\
{ 0xa200, "key01_locked"}, /* Indicates KEY1 is locked , */\
{ 0xa210, "key02_locked"}, /* Indicates KEY2 is locked , */\
{ 0xa302, "mtp_man_address_in"}, /* MTP address from I2C register for read/writing mtp in manual single word mode, */\
{ 0xa330, "man_copy_mtp_to_iic"}, /* Start copying single word from mtp to I2C mtp register, */\
{ 0xa340, "man_copy_iic_to_mtp"}, /* Start copying single word from I2C mtp register to mtp, */\
{ 0xa350, "auto_copy_mtp_to_iic"}, /* Start copying all the data from mtp to I2C mtp registers, */\
{ 0xa360, "auto_copy_iic_to_mtp"}, /* Start copying data from I2C mtp registers to mtp , */\
{ 0xa400, "faim_set_clkws"}, /* Sets the faim controller clock wait state register, */\
{ 0xa410, "faim_sel_evenrows"}, /* All even rows of the faim are selected, active high, */\
{ 0xa420, "faim_sel_oddrows"}, /* All odd rows of the faim are selected, all rows in combination with sel_evenrows, */\
{ 0xa430, "faim_program_only"}, /* Skip the erase access at wr_faim command (write-program-marginread), */\
{ 0xa440, "faim_erase_only"}, /* Skip the program access at wr_faim command (write-erase-marginread), */\
{ 0xa50f, "mtp_man_data_out_msb"}, /* MSB word of MTP manual read data , */\
{ 0xa60f, "mtp_man_data_out_lsb"}, /* LSB word of MTP manual read data , */\
{ 0xa70f, "mtp_man_data_in_msb"}, /* MSB word of write data for MTP manual write , */\
{ 0xa80f, "mtp_man_data_in_lsb"}, /* LSB word of write data for MTP manual write , */\
{ 0xb010, "bypass_ocpcounter"}, /* Bypass OCP Counter , */\
{ 0xb020, "bypass_glitchfilter"}, /* Bypass glitch filter , */\
{ 0xb030, "bypass_ovp"}, /* Bypass OVP , */\
{ 0xb040, "bypass_uvp"}, /* Bypass UVP , */\
{ 0xb050, "bypass_otp"}, /* Bypass OTP , */\
{ 0xb060, "bypass_lost_clk"}, /* Bypass lost clock detector , */\
{ 0xb070, "ctrl_vpalarm"}, /* vpalarm (uvp ovp handling) , */\
{ 0xb087, "ocp_threshold"}, /* OCP threshold level , */\
{ 0xb108, "ext_temp"}, /* External temperature (C) , */\
{ 0xb190, "ext_temp_sel"}, /* Select temp Speaker calibration , */\
{ 0xc000, "use_direct_ctrls"}, /* Direct control to overrule several functions for testing, */\
{ 0xc010, "rst_datapath"}, /* Direct control for datapath reset , */\
{ 0xc020, "rst_cgu"}, /* Direct control for cgu reset , */\
{ 0xc038, "enbl_ref"}, /* Switch on the analog references, each part of the references can be switched on/off individually, */\
{ 0xc0c0, "use_direct_vs_ctrls"}, /* voltage sense Direct control to overrule several functions for testing, */\
{ 0xc0d0, "enbl_ringo"}, /* Enable the ring oscillator for test purpose , */\
{ 0xc0e0, "use_direct_clk_ctrl"}, /* Direct clock control to overrule several functions for testing, */\
{ 0xc0f0, "use_direct_pll_ctrl"}, /* Direct PLL control to overrule several functions for testing, */\
{ 0xc100, "enbl_tsense"}, /* Temperature sensor enable control - I2C direct mode, */\
{ 0xc110, "tsense_hibias"}, /* Bit to set the biasing in temp sensor to high , */\
{ 0xc120, "enbl_flag_vbg"}, /* Enable flagging of bandgap out of control , */\
{ 0xc20f, "abist_offset"}, /* Offset control for ABIST testing (two's complement), */\
{ 0xc300, "bypasslatch"}, /* Bypass latch , */\
{ 0xc311, "sourcea"}, /* Set OUTA to , */\
{ 0xc331, "sourceb"}, /* Set OUTB to , */\
{ 0xc350, "inverta"}, /* Invert pwma test signal , */\
{ 0xc360, "invertb"}, /* Invert pwmb test signal , */\
{ 0xc374, "pulselength"}, /* Pulse length setting test input for amplifier (clock d - k*2048*fs), */\
{ 0xc3c0, "tdm_enable_loopback"}, /* TDM loopback test , */\
{ 0xc400, "bst_bypasslatch"}, /* Bypass latch in boost converter , */\
{ 0xc411, "bst_source"}, /* Sets the source of the pwmbst output to boost converter input for testing, */\
{ 0xc430, "bst_invertb"}, /* Invert pwmbst test signal , */\
{ 0xc444, "bst_pulselength"}, /* Pulse length setting test input for boost converter , */\
{ 0xc490, "test_bst_ctrlsthv"}, /* Test mode for boost control stage , */\
{ 0xc4a0, "test_bst_iddq"}, /* IDDQ testing in power stage of boost converter , */\
{ 0xc4b0, "test_bst_rdson"}, /* RDSON testing - boost power stage , */\
{ 0xc4c0, "test_bst_cvi"}, /* CVI testing - boost power stage , */\
{ 0xc4d0, "test_bst_ocp"}, /* Boost OCP. For old ocp (ctrl_reversebst is 0), For new ocp (ctrl_reversebst is 1), */\
{ 0xc4e0, "test_bst_sense"}, /* Test option for the sense NMOS in booster for current mode control., */\
{ 0xc500, "test_cvi"}, /* Analog BIST, switch choose which transistor will be used as current source (also cross coupled sources possible), */\
{ 0xc510, "test_discrete"}, /* Test function noise measurement , */\
{ 0xc520, "test_iddq"}, /* Set the power stages in iddq mode for gate stress., */\
{ 0xc540, "test_rdson"}, /* Analog BIST, switch to enable Rdson measurement , */\
{ 0xc550, "test_sdelta"}, /* Analog BIST, noise test , */\
{ 0xc570, "test_enbl_cs"}, /* Enable for digimux mode of current sense , */\
{ 0xc580, "test_enbl_vs"}, /* Enable for digimux mode of voltage sense , */\
{ 0xc600, "enbl_pwm_dcc"}, /* Enables direct control of pwm duty cycle for DCDC power stage, */\
{ 0xc613, "pwm_dcc_cnt"}, /* Control pwm duty cycle when enbl_pwm_dcc is 1 , */\
{ 0xc650, "enbl_ldo_stress"}, /* Enable stress of internal supply voltages powerstages, */\
{ 0xc707, "digimuxa_sel"}, /* DigimuxA input selection control routed to DATAO (see Digimux list for details), */\
{ 0xc787, "digimuxb_sel"}, /* DigimuxB input selection control routed to INT (see Digimux list for details), */\
{ 0xc807, "digimuxc_sel"}, /* DigimuxC input selection control routed to PDMDAT (see Digimux list for details), */\
{ 0xc981, "int_ehs"}, /* Speed/load setting for INT IO cell, clk or data mode range (see SLIMMF IO cell datasheet), */\
{ 0xc9c0, "hs_mode"}, /* I2C high speed mode control , */\
{ 0xca00, "enbl_anamux1"}, /* Enable anamux1 , */\
{ 0xca10, "enbl_anamux2"}, /* Enable anamux2 , */\
{ 0xca20, "enbl_anamux3"}, /* Enable anamux3 , */\
{ 0xca30, "enbl_anamux4"}, /* Enable anamux4 , */\
{ 0xca74, "anamux1"}, /* Anamux selection control - anamux on TEST1 , */\
{ 0xcb04, "anamux2"}, /* Anamux selection control - anamux on TEST2 , */\
{ 0xcb53, "anamux3"}, /* Anamux selection control - anamux on TEST3 , */\
{ 0xcba3, "anamux4"}, /* Anamux selection control - anamux on TEST4 , */\
{ 0xcd05, "pll_seli"}, /* PLL SELI - I2C direct PLL control mode only , */\
{ 0xcd64, "pll_selp"}, /* PLL SELP - I2C direct PLL control mode only , */\
{ 0xcdb3, "pll_selr"}, /* PLL SELR - I2C direct PLL control mode only , */\
{ 0xcdf0, "pll_frm"}, /* PLL free running mode control; 1 in TCB direct control mode, else this control bit, */\
{ 0xce09, "pll_ndec"}, /* PLL NDEC - I2C direct PLL control mode only , */\
{ 0xcea0, "pll_mdec_msb"}, /* MSB of pll_mdec - I2C direct PLL control mode only, */\
{ 0xceb0, "enbl_pll"}, /* Enables PLL in I2C direct PLL control mode only , */\
{ 0xcec0, "enbl_osc"}, /* Enables OSC1M in I2C direct control mode only , */\
{ 0xced0, "pll_bypass"}, /* PLL bypass control in I2C direct PLL control mode only, */\
{ 0xcee0, "pll_directi"}, /* PLL directi control in I2C direct PLL control mode only, */\
{ 0xcef0, "pll_directo"}, /* PLL directo control in I2C direct PLL control mode only, */\
{ 0xcf0f, "pll_mdec_lsb"}, /* Bits 15..0 of PLL MDEC are I2C direct PLL control mode only, */\
{ 0xd006, "pll_pdec"}, /* PLL PDEC - I2C direct PLL control mode only , */\
{ 0xd10f, "tsig_freq_lsb"}, /* Internal sinus test generator frequency control , */\
{ 0xd202, "tsig_freq_msb"}, /* Select internal sinus test generator, frequency control msb bits, */\
{ 0xd230, "inject_tsig"}, /* Control bit to switch to internal sinus test generator, */\
{ 0xd283, "tsig_gain"}, /* Test signal gain , */\
{ 0xd300, "adc10_reset"}, /* Reset for ADC10 - I2C direct control mode , */\
{ 0xd311, "adc10_test"}, /* Test mode selection signal for ADC10 - I2C direct control mode, */\
{ 0xd332, "adc10_sel"}, /* Select the input to convert for ADC10 - I2C direct control mode, */\
{ 0xd364, "adc10_prog_sample"}, /* ADC10 program sample setting - I2C direct control mode, */\
{ 0xd3b0, "adc10_enbl"}, /* Enable ADC10 - I2C direct control mode , */\
{ 0xd3c0, "bypass_lp_vbat"}, /* Bypass control for Low pass filter in batt sensor , */\
{ 0xd409, "data_adc10_tempbat"}, /* ADC 10 data output data for testing , */\
{ 0xd507, "ctrl_digtoana_hidden"}, /* Spare digital to analog control bits - Hidden , */\
{ 0xd580, "enbl_clk_out_of_range"}, /* Clock out of range , */\
{ 0xd621, "clkdiv_audio_sel"}, /* Audio clock divider selection in direct clock control mode, */\
{ 0xd641, "clkdiv_muxa_sel"}, /* DCDC MUXA clock divider selection in direct clock control mode, */\
{ 0xd661, "clkdiv_muxb_sel"}, /* DCDC MUXB clock divider selection in direct clock control mode, */\
{ 0xd721, "datao_ehs"}, /* Speed/load setting for DATAO IO cell, clk or data mode range (see SLIMMF IO cell datasheet), */\
{ 0xd740, "bck_ehs"}, /* High-speed and standard/fast mode selection for BCK IO cell (see IIC3V3 IO cell datasheet), */\
{ 0xd750, "datai_ehs"}, /* High-speed and standard/fast mode selection for DATAI IO cell (see IIC3V3 IO cell datasheet), */\
{ 0xd800, "source_in_testmode"}, /* tdm source in test mode (return only current and voltage sense), */\
{ 0xd810, "gainatt_feedback"}, /* gainatt feedback to tdm , */\
{ 0xd822, "test_parametric_io"}, /* test io parametric , */\
{ 0xd850, "ctrl_bst_clk_lp1"}, /* boost clock control in low power mode1 , */\
{ 0xd861, "test_spare_out1"}, /* test spare out 1 , */\
{ 0xd880, "bst_dcmbst"}, /* dcm boost , */\
{ 0xd8c3, "test_spare_out2"}, /* test spare out 1 , */\
{ 0xee0f, "sw_profile"}, /* Software profile data , */\
{ 0xef0f, "sw_vstep"}, /* Software vstep information , */\
{ 0xf000, "calibration_onetime"}, /* Calibration schedule , */\
{ 0xf010, "calibr_ron_done"}, /* Calibration Ron executed , */\
{ 0xf020, "calibr_dcdc_api_calibrate"}, /* Calibration current limit DCDC , */\
{ 0xf030, "calibr_dcdc_delta_sign"}, /* Sign bit for delta calibration current limit DCDC , */\
{ 0xf042, "calibr_dcdc_delta"}, /* Calibration delta current limit DCDC , */\
{ 0xf078, "calibr_speaker_info"}, /* Reserved space for allowing customer to store speaker information, */\
{ 0xf105, "calibr_vout_offset"}, /* DCDC offset calibration 2's complement (key1 protected), */\
{ 0xf169, "spare_mpt1_15_6"}, /* SPARE , */\
{ 0xf203, "calibr_gain"}, /* HW gain module (2's complement) , */\
{ 0xf245, "calibr_offset"}, /* Offset for amplifier, HW gain module (2's complement), */\
{ 0xf2a5, "spare_mtp2_15_10"}, /* SPARE , */\
{ 0xf307, "calibr_gain_vs"}, /* Voltage sense gain , */\
{ 0xf387, "calibr_gain_cs"}, /* Current sense gain (signed two's complement format), */\
{ 0xf407, "spare_mtp4_15_0"}, /* SPARE , */\
{ 0xf487, "vs_trim"}, /* VS Trimming , */\
{ 0xf50f, "calibr_R25C_R"}, /* Ron resistance of speaker coil , */\
{ 0xf60f, "spare_mpt6_6_0"}, /* SPARE , */\
{ 0xf706, "ctrl_offset_a"}, /* Offset of level shifter A , */\
{ 0xf770, "spare_mtp7_07"}, /* SPARE , */\
{ 0xf786, "ctrl_offset_b"}, /* Offset of amplifier level shifter B , */\
{ 0xf7f0, "spare_mtp7_15"}, /* SPARE , */\
{ 0xf806, "htol_iic_addr"}, /* 7-bit I2C address to be used during HTOL testing , */\
{ 0xf870, "htol_iic_addr_en"}, /* HTOL I2C address enable control , */\
{ 0xf884, "calibr_temp_offset"}, /* Temperature offset 2's compliment (key1 protected), */\
{ 0xf8d2, "calibr_temp_gain"}, /* Temperature gain 2's compliment (key1 protected) , */\
{ 0xf900, "mtp_lock_dcdcoff_mode"}, /* Disable function dcdcoff_mode , */\
{ 0xf910, "spare_mtp9_1"}, /* SPARE , */\
{ 0xf920, "mtp_lock_bypass_clipper"}, /* Disable function bypass_clipper , */\
{ 0xf930, "mtp_lock_max_dcdc_voltage"}, /* Force Boost in follower mode , */\
{ 0xf943, "calibr_vbg_trim"}, /* Bandgap trimming control , */\
{ 0xf980, "spare_mtp9_8"}, /* SPARE , */\
{ 0xf990, "mtp_enbl_pwm_delay_clock_gating"}, /* pwm delay clock auto gating , */\
{ 0xf9a0, "mtp_enbl_ocp_clock_gating"}, /* ocpclock auto gating , */\
{ 0xf9b0, "mtp_gate_cgu_clock_for_test"}, /* cgu test clock control , */\
{ 0xf9c0, "mtp_tdm_pad_sel"}, /* tdm pad selection , */\
{ 0xf9d2, "spare_mtp9_15_12"}, /* MTP-control FW - See Firmware I2C API document for details, */\
{ 0xfa0f, "mtpdataA"}, /* MTPdataA (key1 protected) , */\
{ 0xfb0f, "mtpdataB"}, /* MTPdataB (key1 protected) , */\
{ 0xfc0f, "mtpdataC"}, /* MTPdataC (key1 protected) , */\
{ 0xfd0f, "mtpdataD"}, /* MTPdataD (key1 protected) , */\
{ 0xfe0f, "mtpdataE"}, /* MTPdataE (key1 protected) , */\
{ 0xff07, "calibr_osc_delta_ndiv"}, /* Calibration data for OSC1M, signed number representation, */\
{ 0xff87, "spare_mtp7_15_08"}, /* SPARE , */\
{ 0xffff,"Unknown bitfield enum" } /* not found */\
};
enum tfa9874_irq {
tfa9874_irq_stvdds = 0,
tfa9874_irq_stbstoc = 1,
tfa9874_irq_stotds = 2,
tfa9874_irq_stocpr = 3,
tfa9874_irq_stuvds = 4,
tfa9874_irq_stmanalarm = 5,
tfa9874_irq_sttdmer = 6,
tfa9874_irq_stnoclk = 7,
tfa9874_irq_max = 8,
tfa9874_irq_all = -1 /* all irqs */};
#define TFA9874_IRQ_NAMETABLE static tfaIrqName_t Tfa9874IrqNames[]= {\
{ 0, "STVDDS"},\
{ 1, "STBSTOC"},\
{ 2, "STOTDS"},\
{ 3, "STOCPR"},\
{ 4, "STUVDS"},\
{ 5, "STMANALARM"},\
{ 6, "STTDMER"},\
{ 7, "STNOCLK"},\
{ 8, "8"},\
};
#endif /* _TFA9874_TFAFIELDNAMES_H */

980
techpack/audio/asoc/codecs/tfa98xx/inc/tfa9878_tfafieldnames.h Executable file
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@ -0,0 +1,980 @@
/*
* Copyright (C) 2014-2020 NXP Semiconductors, All Rights Reserved.
* Copyright 2020 GOODIX
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
*/
/** Filename: tfa9878_tfaFieldnames.h
* This file was generated automatically on 06/28/19 at 10:22:32.
* Source file: TFA9878_PRB3_N1A1_DefaultI2CSettings.xlsx
*/
#ifndef _TFA9878_TFAFIELDNAMES_H
#define _TFA9878_TFAFIELDNAMES_H
#define TFA9878_I2CVERSION 12
typedef enum Tfa9878BfEnumList {
TFA9878_BF_PWDN = 0x0000, /*!< Powerdown selection */
TFA9878_BF_I2CR = 0x0010, /*!< I2C Reset - Auto clear */
TFA9878_BF_AMPE = 0x0030, /*!< Activate Amplifier */
TFA9878_BF_DCA = 0x0040, /*!< Activate DC-to-DC converter */
TFA9878_BF_INTP = 0x0071, /*!< Interrupt config */
TFA9878_BF_FSSSEL= 0x0090, /*!< Audio sample reference */
TFA9878_BF_BYPOCP= 0x00b0, /*!< Bypass OCP */
TFA9878_BF_TSTOCP= 0x00c0, /*!< OCP testing control */
TFA9878_BF_AMPINSEL= 0x0101, /*!< Amplifier input selection */
TFA9878_BF_MANSCONF= 0x0120, /*!< I2C configured */
TFA9878_BF_DCINSEL= 0x0131, /*!< VAMP_OUT2 input selection */
TFA9878_BF_MUTETO= 0x0160, /*!< Time out SB mute sequence */
TFA9878_BF_MANROBOD= 0x0170, /*!< Reaction on BOD */
TFA9878_BF_BODE = 0x0180, /*!< Enable BOD (only in direct control mode) */
TFA9878_BF_BODHYS= 0x0190, /*!< Enable Hysteresis of BOD */
TFA9878_BF_BODFILT= 0x01a1, /*!< BOD filter */
TFA9878_BF_BODTHLVL= 0x01c1, /*!< BOD threshold */
TFA9878_BF_OPENMTP= 0x01e0, /*!< Control for FAIM protection */
TFA9878_BF_DISFCRBST= 0x01f0, /*!< disable boost control with FRCBST */
TFA9878_BF_AUDFS = 0x0203, /*!< Sample rate (fs) */
TFA9878_BF_INPLEV= 0x0240, /*!< TDM output attenuation */
TFA9878_BF_FRACTDEL= 0x0255, /*!< V/I Fractional delay */
TFA9878_BF_AMPINPSEL= 0x02b1, /*!< amp input selection */
TFA9878_BF_PDMRATE= 0x02d0, /*!< Pdm rate */
TFA9878_BF_REV = 0x030f, /*!< Revision info */
TFA9878_BF_REFCKEXT= 0x0401, /*!< PLL external ref clock */
TFA9878_BF_REFCKSEL= 0x0420, /*!< PLL internal ref clock */
TFA9878_BF_SWCLKSEL= 0x0432, /*!< Sound Wire clock frequnecy */
TFA9878_BF_MANAOOSC= 0x0460, /*!< Internal osc off at PWDN */
TFA9878_BF_FSSYNCEN= 0x0480, /*!< Enable FS synchronisation for clock divider */
TFA9878_BF_CLKREFSYNCEN= 0x0490, /*!< Enable PLL reference clock synchronisation for clock divider */
TFA9878_BF_AUTOFROSEL= 0x04a0, /*!< override automatic OSC selection mechanism */
TFA9878_BF_SWFRSYNC= 0x04b0, /*!< Selection SW signal reference for Stream Synchronization */
TFA9878_BF_CGUSYNCDCG= 0x0500, /*!< Clock gating control for CGU synchronisation module */
TFA9878_BF_FRCCLKSPKR= 0x0510, /*!< force active the speaker sub-system clock when in idle power */
TFA9878_BF_SSFAIME= 0x05c0, /*!< Sub-system FAIM */
TFA9878_BF_CLKCHKLO= 0x0707, /*!< Clock check Low Threshold */
TFA9878_BF_CLKCHKHI= 0x0787, /*!< Clock check Higher Threshold */
TFA9878_BF_AMPOCRT= 0x0802, /*!< Amplifier on-off criteria for shutdown */
TFA9878_BF_VDDS = 0x1000, /*!< POR */
TFA9878_BF_DCOCPOK= 0x1010, /*!< DCDC OCP nmos (sticky register , clear on read) */
TFA9878_BF_OTDS = 0x1020, /*!< OTP alarm (sticky register , clear on read) */
TFA9878_BF_OCDS = 0x1030, /*!< OCP amplifier (sticky register , clear on read) */
TFA9878_BF_UVDS = 0x1040, /*!< UVP alarm (sticky register , clear on read) */
TFA9878_BF_MANALARM= 0x1050, /*!< Alarm state */
TFA9878_BF_CLKS = 0x1060, /*!< Clocks stable */
TFA9878_BF_MTPB = 0x1070, /*!< MTP busy */
TFA9878_BF_NOCLK = 0x1080, /*!< Lost clock (sticky register , clear on read) */
TFA9878_BF_BODNOK= 0x1090, /*!< BOD Flag - VDD NOT OK */
TFA9878_BF_TDMERR= 0x10a0, /*!< TDM error */
TFA9878_BF_DCIL = 0x1100, /*!< DCDC current limiting */
TFA9878_BF_DCDCA = 0x1110, /*!< DCDC active (sticky register , clear on read) */
TFA9878_BF_DCDCPC= 0x1120, /*!< Indicates current is max in DC-to-DC converter */
TFA9878_BF_DCHVBAT= 0x1130, /*!< DCDC level 1x */
TFA9878_BF_DCH114= 0x1140, /*!< DCDC level 1.14x */
TFA9878_BF_DCH107= 0x1150, /*!< DCDC level 1.07x */
TFA9878_BF_PLLS = 0x1160, /*!< PLL lock */
TFA9878_BF_TDMLUTER= 0x1180, /*!< TDM LUT error */
TFA9878_BF_CLKOOR= 0x11c0, /*!< External clock status */
TFA9878_BF_SWS = 0x11d0, /*!< Amplifier engage */
TFA9878_BF_AMPS = 0x11e0, /*!< Amplifier enable */
TFA9878_BF_AREFS = 0x11f0, /*!< References enable */
TFA9878_BF_OCPOAP= 0x1300, /*!< OCPOK pmos B */
TFA9878_BF_OCPOAN= 0x1310, /*!< OCPOK pmos A */
TFA9878_BF_OCPOBP= 0x1320, /*!< OCPOK nmos B */
TFA9878_BF_OCPOBN= 0x1330, /*!< OCPOK nmos A */
TFA9878_BF_OVDS = 0x1380, /*!< OVP alarm */
TFA9878_BF_CLIPS = 0x1390, /*!< Amplifier clipping */
TFA9878_BF_ADCCR = 0x13a0, /*!< Control ADC */
TFA9878_BF_MANWAIT1= 0x13c0, /*!< Wait HW I2C settings */
TFA9878_BF_MANMUTE= 0x13e0, /*!< Audio mute sequence */
TFA9878_BF_MANOPER= 0x13f0, /*!< Operating state */
TFA9878_BF_TDMSTAT= 0x1402, /*!< TDM status bits */
TFA9878_BF_MANSTATE= 0x1433, /*!< Device manager status */
TFA9878_BF_AMPSTE= 0x1473, /*!< Amplifier control status */
TFA9878_BF_DCMODE= 0x14b1, /*!< DCDC mode status bits */
TFA9878_BF_BATS = 0x1509, /*!< Battery voltage (V) */
TFA9878_BF_TEMPS = 0x1608, /*!< IC Temperature (C) */
TFA9878_BF_VDDPS = 0x1709, /*!< IC VDDP voltage ( 1023*VDDP/13 V) */
TFA9878_BF_TDME = 0x2000, /*!< Enable interface */
TFA9878_BF_TDMSLOTS= 0x2013, /*!< N-slots in Frame */
TFA9878_BF_TDMCLINV= 0x2060, /*!< Reception data to BCK clock */
TFA9878_BF_TDMFSLN= 0x2073, /*!< FS length */
TFA9878_BF_TDMFSPOL= 0x20b0, /*!< FS polarity */
TFA9878_BF_TDMNBCK= 0x20c3, /*!< N-BCK's in FS */
TFA9878_BF_TDMSLLN= 0x2144, /*!< N-bits in slot */
TFA9878_BF_TDMBRMG= 0x2194, /*!< N-bits remaining */
TFA9878_BF_TDMDEL= 0x21e0, /*!< data delay to FS */
TFA9878_BF_TDMADJ= 0x21f0, /*!< data adjustment */
TFA9878_BF_TDMOOMP= 0x2201, /*!< Received audio compression */
TFA9878_BF_TDMSSIZE= 0x2224, /*!< Sample size per slot */
TFA9878_BF_TDMTXDFO= 0x2271, /*!< Format unused bits */
TFA9878_BF_TDMTXUS0= 0x2291, /*!< Format unused slots DATAO */
TFA9878_BF_TDMSPKE= 0x2300, /*!< Control audio tdm channel in 0 */
TFA9878_BF_TDMDCE= 0x2310, /*!< Control audio tdm channel in 1 */
TFA9878_BF_TDMCSE= 0x2330, /*!< current sense vbat temperature and vddp feedback */
TFA9878_BF_TDMVSE= 0x2340, /*!< Voltage sense vbat temperature and vddp feedback */
TFA9878_BF_TDMSPKS= 0x2603, /*!< tdm slot for sink 0 */
TFA9878_BF_TDMDCS= 0x2643, /*!< tdm slot for sink 1 */
TFA9878_BF_TDMCSS= 0x26c3, /*!< Slot Position of current sense vbat temperature and vddp feedback */
TFA9878_BF_TDMVSS= 0x2703, /*!< Slot Position of Voltage sense vbat temperature and vddp feedback */
TFA9878_BF_ISTVDDS= 0x4000, /*!< Status POR */
TFA9878_BF_ISTBSTOC= 0x4010, /*!< Status DCDC OCP */
TFA9878_BF_ISTOTDS= 0x4020, /*!< Status OTP alarm */
TFA9878_BF_ISTOCPR= 0x4030, /*!< Status ocp alarm */
TFA9878_BF_ISTUVDS= 0x4040, /*!< Status UVP alarm */
TFA9878_BF_ISTMANALARM= 0x4050, /*!< Status nanager Alarm state */
TFA9878_BF_ISTTDMER= 0x4060, /*!< Status tdm error */
TFA9878_BF_ISTNOCLK= 0x4070, /*!< Status lost clock */
TFA9878_BF_ISTBODNOK= 0x4080, /*!< Status BOD event */
TFA9878_BF_ICLVDDS= 0x4400, /*!< Clear POR */
TFA9878_BF_ICLBSTOC= 0x4410, /*!< Clear DCDC OCP */
TFA9878_BF_ICLOTDS= 0x4420, /*!< Clear OTP alarm */
TFA9878_BF_ICLOCPR= 0x4430, /*!< Clear ocp alarm */
TFA9878_BF_ICLUVDS= 0x4440, /*!< Clear UVP alarm */
TFA9878_BF_ICLMANALARM= 0x4450, /*!< Clear manager Alarm state */
TFA9878_BF_ICLTDMER= 0x4460, /*!< Clear tdm error */
TFA9878_BF_ICLNOCLK= 0x4470, /*!< Clear lost clk */
TFA9878_BF_ICLBODNOK= 0x4480, /*!< Clear BOD event */
TFA9878_BF_IEVDDS= 0x4800, /*!< Enable por */
TFA9878_BF_IEBSTOC= 0x4810, /*!< Enable DCDC OCP */
TFA9878_BF_IEOTDS= 0x4820, /*!< Enable OTP alarm */
TFA9878_BF_IEOCPR= 0x4830, /*!< Enable ocp alarm */
TFA9878_BF_IEUVDS= 0x4840, /*!< Enable UVP alarm */
TFA9878_BF_IEMANALARM= 0x4850, /*!< Enable nanager Alarm state */
TFA9878_BF_IETDMER= 0x4860, /*!< Enable tdm error */
TFA9878_BF_IENOCLK= 0x4870, /*!< Enable lost clk */
TFA9878_BF_IEBODNOK= 0x4880, /*!< Enable BOD trigger */
TFA9878_BF_IPOVDDS= 0x4c00, /*!< Polarity por */
TFA9878_BF_IPOBSTOC= 0x4c10, /*!< Polarity DCDC OCP */
TFA9878_BF_IPOOTDS= 0x4c20, /*!< Polarity OTP alarm */
TFA9878_BF_IPOOCPR= 0x4c30, /*!< Polarity ocp alarm */
TFA9878_BF_IPOUVDS= 0x4c40, /*!< Polarity UVP alarm */
TFA9878_BF_IPOMANALARM= 0x4c50, /*!< Polarity nanager Alarm state */
TFA9878_BF_IPOTDMER= 0x4c60, /*!< Polarity tdm error */
TFA9878_BF_IPONOCLK= 0x4c70, /*!< Polarity lost clk */
TFA9878_BF_IPOBODNOK= 0x4c80, /*!< Polarity BOD trigger */
TFA9878_BF_BSSCR = 0x5001, /*!< Battery Safeguard attack time (with K = 1 at sample rate fs of 32kHz, 44,1 kHz or 48kHz ; with K = 2 at sample rate fs 16 kHz . With K =0.5 at sample rate of 96 kHz) */
TFA9878_BF_BSST = 0x5023, /*!< Battery Safeguard threshold voltage level */
TFA9878_BF_BSSRL = 0x5061, /*!< Battery Safeguard maximum reduction */
TFA9878_BF_BSSR = 0x50e0, /*!< Battery voltage read out */
TFA9878_BF_BSSBY = 0x50f0, /*!< Bypass battery safeguard */
TFA9878_BF_BSSS = 0x5100, /*!< Vbat prot steepness */
TFA9878_BF_HPFBYP= 0x5150, /*!< Bypass HPF */
TFA9878_BF_DPSA = 0x5170, /*!< Enable DPSA */
TFA9878_BF_CLIPCTRL= 0x5222, /*!< Clip control setting */
TFA9878_BF_AMPGAIN= 0x5257, /*!< Amplifier gain */
TFA9878_BF_SLOPEE= 0x52d0, /*!< Enables slope control */
TFA9878_BF_SLOPESET= 0x52e0, /*!< Slope speed setting (bin. coded) */
TFA9878_BF_BYPDLYLINE= 0x52f0, /*!< Bypass the interpolator delay line */
TFA9878_BF_TDMDCG= 0x5f23, /*!< Second channel gain in case of stereo using a single coil. (Total gain depending on INPLEV). (In case of mono OR stereo using 2 separate DCDC channel 1 should be disabled using TDMDCE) */
TFA9878_BF_TDMSPKG= 0x5f63, /*!< Total gain depending on INPLEV setting (channel 0) */
TFA9878_BF_IPM = 0x60e1, /*!< Idle power mode control */
TFA9878_BF_LNMODE= 0x62e1, /*!< ctrl select mode */
TFA9878_BF_LPM1MODE= 0x64e1, /*!< low power mode control */
TFA9878_BF_TDMSRCMAP= 0x6802, /*!< tdm source mapping */
TFA9878_BF_TDMSRCAS= 0x6831, /*!< Sensed value A */
TFA9878_BF_TDMSRCBS= 0x6851, /*!< Sensed value B */
TFA9878_BF_TDMSRCACLIP= 0x6871, /*!< clip information (analog /digital) for source0 */
TFA9878_BF_TDMSRCBCLIP= 0x6891, /*!< clip information (analog /digital) for source1 */
TFA9878_BF_LP0 = 0x6e00, /*!< Idle power mode */
TFA9878_BF_LP1 = 0x6e10, /*!< low power mode 1 detection */
TFA9878_BF_LA = 0x6e20, /*!< low amplitude detection */
TFA9878_BF_VDDPH = 0x6e30, /*!< vddp greater than vbat */
TFA9878_BF_DELCURCOMP= 0x6f02, /*!< delay to allign compensation signal with current sense signal */
TFA9878_BF_SIGCURCOMP= 0x6f40, /*!< polarity of compensation for current sense */
TFA9878_BF_ENCURCOMP= 0x6f50, /*!< enable current sense compensation */
TFA9878_BF_LVLCLPPWM= 0x6f72, /*!< set the amount of pwm pulse that may be skipped before clip-flag is triggered */
TFA9878_BF_DCMCC = 0x7003, /*!< Max coil current */
TFA9878_BF_DCCV = 0x7041, /*!< Slope compensation current, represents LxF (inductance x frequency) value */
TFA9878_BF_DCIE = 0x7060, /*!< Adaptive boost mode */
TFA9878_BF_DCSR = 0x7070, /*!< Soft ramp up/down */
TFA9878_BF_DCOVL = 0x7085, /*!< Threshold level to activate active overshoot control */
TFA9878_BF_DCDIS = 0x70e0, /*!< DCDC on/off */
TFA9878_BF_DCPWM = 0x70f0, /*!< DCDC PWM only mode */
TFA9878_BF_DCTRACK= 0x7430, /*!< Boost algorithm selection, effective only when boost_intelligent is set to 1 */
TFA9878_BF_DCTRIP= 0x7444, /*!< 1st Adaptive boost trip levels, effective only when DCIE is set to 1 */
TFA9878_BF_DCHOLD= 0x7494, /*!< Hold time for DCDC booster, effective only when boost_intelligent is set to 1 */
TFA9878_BF_DCINT = 0x74e0, /*!< Selection of data for adaptive boost algorithm, effective only when boost_intelligent is set to 1 */
TFA9878_BF_DCTRIP2= 0x7534, /*!< 2nd Adaptive boost trip levels, effective only when DCIE is set to 1 */
TFA9878_BF_DCTRIPT= 0x7584, /*!< Track Adaptive boost trip levels, effective only when boost_intelligent is set to 1 */
TFA9878_BF_DCTRIPHYSTE= 0x75f0, /*!< Enable hysteresis on booster trip levels */
TFA9878_BF_DCVOF = 0x7635, /*!< First boost voltage level */
TFA9878_BF_DCVOS = 0x7695, /*!< Second boost voltage level */
TFA9878_BF_MTPK = 0xa107, /*!< MTP KEY2 register */
TFA9878_BF_KEY1LOCKED= 0xa200, /*!< Indicates KEY1 is locked */
TFA9878_BF_KEY2LOCKED= 0xa210, /*!< Indicates KEY2 is locked */
TFA9878_BF_MTPADDR= 0xa302, /*!< MTP address from I2C register for read/writing mtp in manual single word mode */
TFA9878_BF_MTPRDMSB= 0xa50f, /*!< MSB word of MTP manual read data */
TFA9878_BF_MTPRDLSB= 0xa60f, /*!< LSB word of MTP manual read data */
TFA9878_BF_MTPWRMSB= 0xa70f, /*!< MSB word of write data for MTP manual write */
TFA9878_BF_MTPWRLSB= 0xa80f, /*!< LSB word of write data for MTP manual write */
TFA9878_BF_EXTTS = 0xb108, /*!< External temperature (C) */
TFA9878_BF_TROS = 0xb190, /*!< Select temp Speaker calibration */
TFA9878_BF_PLLINSI= 0xcd05, /*!< PLL INSELI - PLL direct bandwidth control mode only with pll_bandsel set to 1 */
TFA9878_BF_PLLINSP= 0xcd64, /*!< PLL INSELP - PLL direct bandwidth control mode only with pll_bandsel set to 1 */
TFA9878_BF_PLLINSR= 0xcdb3, /*!< PLL INSELR - PLL direct bandwidth control mode only with pll_bandsel set to 1 */
TFA9878_BF_PLLBDSEL= 0xcdf0, /*!< PLL bandwidth selection control, USE WITH CAUTION */
TFA9878_BF_PLLNDEC= 0xce09, /*!< PLL NDEC in direct control mode only, use_direct_pll_ctrl set to 1 */
TFA9878_BF_PLLMDECM= 0xcea0, /*!< MSB of PLL MDEC in direct control mode only, use_direct_pll_ctrl set to 1 */
TFA9878_BF_PLLBP = 0xceb0, /*!< PLL bypass control during functional mode */
TFA9878_BF_PLLDI = 0xcec0, /*!< PLL directi control in direct control mode only, use_direct_pll_ctrl set to 1 */
TFA9878_BF_PLLDO = 0xced0, /*!< PLL directo control in direct control mode only, use_direct_pll_ctrl set to 1 */
TFA9878_BF_PLLCLKSTB= 0xcee0, /*!< PLL FRM clock stable control in direct control mode only, use_direct_pll_ctrl set to 1 */
TFA9878_BF_PLLFRM= 0xcef0, /*!< PLL free running mode control in functional mode */
TFA9878_BF_PLLMDECL= 0xcf0f, /*!< Bits 15..0 of PLL MDEC in direct control mode only, use_direct_pll_ctrl set to 1 */
TFA9878_BF_PLLPDEC= 0xd006, /*!< PLL PDEC in direct control mode only, use_direct_pll_ctrl set to 1 */
TFA9878_BF_PLLDCTRL= 0xd070, /*!< Enabled PLL direct control mode, overrules the PLL LUT with I2C register values */
TFA9878_BF_PLLLIMOFF= 0xd090, /*!< PLL up limiter control in PLL direct bandwidth control mode, pll_bandsel set to 1 */
TFA9878_BF_PLLSTRTM= 0xd0a2, /*!< PLL startup time selection control */
TFA9878_BF_SWPROFIL= 0xe00f, /*!< Software profile data */
TFA9878_BF_SWVSTEP= 0xe10f, /*!< Software vstep information */
TFA9878_BF_MTPOTC= 0xf000, /*!< Calibration schedule */
TFA9878_BF_MTPEX = 0xf010, /*!< Calibration Ron executed */
TFA9878_BF_DCMCCAPI= 0xf020, /*!< Calibration current limit DCDC */
TFA9878_BF_DCMCCSB= 0xf030, /*!< Sign bit for delta calibration current limit DCDC */
TFA9878_BF_USERDEF= 0xf042, /*!< Calibration delta current limit DCDC */
TFA9878_BF_CUSTINFO= 0xf078, /*!< Reserved space for allowing customer to store speaker information */
TFA9878_BF_R25C = 0xf50f, /*!< Ron resistance of speaker coil */
} Tfa9878BfEnumList_t;
#define TFA9878_NAMETABLE static tfaBfName_t Tfa9878DatasheetNames[]= {\
{ 0x0, "PWDN"}, /* Powerdown selection , */\
{ 0x10, "I2CR"}, /* I2C Reset - Auto clear , */\
{ 0x30, "AMPE"}, /* Activate Amplifier , */\
{ 0x40, "DCA"}, /* Activate DC-to-DC converter , */\
{ 0x71, "INTP"}, /* Interrupt config , */\
{ 0x90, "FSSSEL"}, /* Audio sample reference , */\
{ 0xb0, "BYPOCP"}, /* Bypass OCP , */\
{ 0xc0, "TSTOCP"}, /* OCP testing control , */\
{ 0x101, "AMPINSEL"}, /* Amplifier input selection , */\
{ 0x120, "MANSCONF"}, /* I2C configured , */\
{ 0x131, "DCINSEL"}, /* VAMP_OUT2 input selection , */\
{ 0x160, "MUTETO"}, /* Time out SB mute sequence , */\
{ 0x170, "MANROBOD"}, /* Reaction on BOD , */\
{ 0x180, "BODE"}, /* Enable BOD (only in direct control mode) , */\
{ 0x190, "BODHYS"}, /* Enable Hysteresis of BOD , */\
{ 0x1a1, "BODFILT"}, /* BOD filter , */\
{ 0x1c1, "BODTHLVL"}, /* BOD threshold , */\
{ 0x1e0, "OPENMTP"}, /* Control for FAIM protection , */\
{ 0x1f0, "DISFCRBST"}, /* disable boost control with FRCBST , */\
{ 0x203, "AUDFS"}, /* Sample rate (fs) , */\
{ 0x240, "INPLEV"}, /* TDM output attenuation , */\
{ 0x255, "FRACTDEL"}, /* V/I Fractional delay , */\
{ 0x2b1, "AMPINPSEL"}, /* amp input selection , */\
{ 0x2d0, "PDMRATE"}, /* Pdm rate , */\
{ 0x30f, "REV"}, /* Revision info , */\
{ 0x401, "REFCKEXT"}, /* PLL external ref clock , */\
{ 0x420, "REFCKSEL"}, /* PLL internal ref clock , */\
{ 0x432, "SWCLKSEL"}, /* Sound Wire clock frequnecy , */\
{ 0x460, "MANAOOSC"}, /* Internal osc off at PWDN , */\
{ 0x480, "FSSYNCEN"}, /* Enable FS synchronisation for clock divider , */\
{ 0x490, "CLKREFSYNCEN"}, /* Enable PLL reference clock synchronisation for clock divider, */\
{ 0x4a0, "AUTOFROSEL"}, /* override automatic OSC selection mechanism , */\
{ 0x4b0, "SWFRSYNC"}, /* Selection SW signal reference for Stream Synchronization , */\
{ 0x500, "CGUSYNCDCG"}, /* Clock gating control for CGU synchronisation module, */\
{ 0x510, "FRCCLKSPKR"}, /* force active the speaker sub-system clock when in idle power, */\
{ 0x5c0, "SSFAIME"}, /* Sub-system FAIM , */\
{ 0x707, "CLKCHKLO"}, /* Clock check Low Threshold , */\
{ 0x787, "CLKCHKHI"}, /* Clock check Higher Threshold , */\
{ 0x802, "AMPOCRT"}, /* Amplifier on-off criteria for shutdown , */\
{ 0x1000, "VDDS"}, /* POR , */\
{ 0x1010, "DCOCPOK"}, /* DCDC OCP nmos (sticky register , clear on read) , */\
{ 0x1020, "OTDS"}, /* OTP alarm (sticky register , clear on read) , */\
{ 0x1030, "OCDS"}, /* OCP amplifier (sticky register , clear on read), */\
{ 0x1040, "UVDS"}, /* UVP alarm (sticky register , clear on read) , */\
{ 0x1050, "MANALARM"}, /* Alarm state , */\
{ 0x1060, "CLKS"}, /* Clocks stable , */\
{ 0x1070, "MTPB"}, /* MTP busy , */\
{ 0x1080, "NOCLK"}, /* Lost clock (sticky register , clear on read) , */\
{ 0x1090, "BODNOK"}, /* BOD Flag - VDD NOT OK , */\
{ 0x10a0, "TDMERR"}, /* TDM error , */\
{ 0x1100, "DCIL"}, /* DCDC current limiting , */\
{ 0x1110, "DCDCA"}, /* DCDC active (sticky register , clear on read) , */\
{ 0x1120, "DCDCPC"}, /* Indicates current is max in DC-to-DC converter , */\
{ 0x1130, "DCHVBAT"}, /* DCDC level 1x , */\
{ 0x1140, "DCH114"}, /* DCDC level 1.14x , */\
{ 0x1150, "DCH107"}, /* DCDC level 1.07x , */\
{ 0x1160, "PLLS"}, /* PLL lock , */\
{ 0x1180, "TDMLUTER"}, /* TDM LUT error , */\
{ 0x11c0, "CLKOOR"}, /* External clock status , */\
{ 0x11d0, "SWS"}, /* Amplifier engage , */\
{ 0x11e0, "AMPS"}, /* Amplifier enable , */\
{ 0x11f0, "AREFS"}, /* References enable , */\
{ 0x1300, "OCPOAP"}, /* OCPOK pmos B , */\
{ 0x1310, "OCPOAN"}, /* OCPOK pmos A , */\
{ 0x1320, "OCPOBP"}, /* OCPOK nmos B , */\
{ 0x1330, "OCPOBN"}, /* OCPOK nmos A , */\
{ 0x1380, "OVDS"}, /* OVP alarm , */\
{ 0x1390, "CLIPS"}, /* Amplifier clipping , */\
{ 0x13a0, "ADCCR"}, /* Control ADC , */\
{ 0x13c0, "MANWAIT1"}, /* Wait HW I2C settings , */\
{ 0x13e0, "MANMUTE"}, /* Audio mute sequence , */\
{ 0x13f0, "MANOPER"}, /* Operating state , */\
{ 0x1402, "TDMSTAT"}, /* TDM status bits , */\
{ 0x1433, "MANSTATE"}, /* Device manager status , */\
{ 0x1473, "AMPSTE"}, /* Amplifier control status , */\
{ 0x14b1, "DCMODE"}, /* DCDC mode status bits , */\
{ 0x1509, "BATS"}, /* Battery voltage (V) , */\
{ 0x1608, "TEMPS"}, /* IC Temperature (C) , */\
{ 0x1709, "VDDPS"}, /* IC VDDP voltage ( 1023*VDDP/13 V) , */\
{ 0x2000, "TDME"}, /* Enable interface , */\
{ 0x2013, "TDMSLOTS"}, /* N-slots in Frame , */\
{ 0x2060, "TDMCLINV"}, /* Reception data to BCK clock , */\
{ 0x2073, "TDMFSLN"}, /* FS length , */\
{ 0x20b0, "TDMFSPOL"}, /* FS polarity , */\
{ 0x20c3, "TDMNBCK"}, /* N-BCK's in FS , */\
{ 0x2144, "TDMSLLN"}, /* N-bits in slot , */\
{ 0x2194, "TDMBRMG"}, /* N-bits remaining , */\
{ 0x21e0, "TDMDEL"}, /* data delay to FS , */\
{ 0x21f0, "TDMADJ"}, /* data adjustment , */\
{ 0x2201, "TDMOOMP"}, /* Received audio compression , */\
{ 0x2224, "TDMSSIZE"}, /* Sample size per slot , */\
{ 0x2271, "TDMTXDFO"}, /* Format unused bits , */\
{ 0x2291, "TDMTXUS0"}, /* Format unused slots DATAO , */\
{ 0x2300, "TDMSPKE"}, /* Control audio tdm channel in 0 , */\
{ 0x2310, "TDMDCE"}, /* Control audio tdm channel in 1 , */\
{ 0x2330, "TDMCSE"}, /* current sense vbat temperature and vddp feedback , */\
{ 0x2340, "TDMVSE"}, /* Voltage sense vbat temperature and vddp feedback , */\
{ 0x2603, "TDMSPKS"}, /* tdm slot for sink 0 , */\
{ 0x2643, "TDMDCS"}, /* tdm slot for sink 1 , */\
{ 0x26c3, "TDMCSS"}, /* Slot Position of current sense vbat temperature and vddp feedback, */\
{ 0x2703, "TDMVSS"}, /* Slot Position of Voltage sense vbat temperature and vddp feedback, */\
{ 0x4000, "ISTVDDS"}, /* Status POR , */\
{ 0x4010, "ISTBSTOC"}, /* Status DCDC OCP , */\
{ 0x4020, "ISTOTDS"}, /* Status OTP alarm , */\
{ 0x4030, "ISTOCPR"}, /* Status ocp alarm , */\
{ 0x4040, "ISTUVDS"}, /* Status UVP alarm , */\
{ 0x4050, "ISTMANALARM"}, /* Status nanager Alarm state , */\
{ 0x4060, "ISTTDMER"}, /* Status tdm error , */\
{ 0x4070, "ISTNOCLK"}, /* Status lost clock , */\
{ 0x4080, "ISTBODNOK"}, /* Status BOD event , */\
{ 0x4400, "ICLVDDS"}, /* Clear POR , */\
{ 0x4410, "ICLBSTOC"}, /* Clear DCDC OCP , */\
{ 0x4420, "ICLOTDS"}, /* Clear OTP alarm , */\
{ 0x4430, "ICLOCPR"}, /* Clear ocp alarm , */\
{ 0x4440, "ICLUVDS"}, /* Clear UVP alarm , */\
{ 0x4450, "ICLMANALARM"}, /* Clear manager Alarm state , */\
{ 0x4460, "ICLTDMER"}, /* Clear tdm error , */\
{ 0x4470, "ICLNOCLK"}, /* Clear lost clk , */\
{ 0x4480, "ICLBODNOK"}, /* Clear BOD event , */\
{ 0x4800, "IEVDDS"}, /* Enable por , */\
{ 0x4810, "IEBSTOC"}, /* Enable DCDC OCP , */\
{ 0x4820, "IEOTDS"}, /* Enable OTP alarm , */\
{ 0x4830, "IEOCPR"}, /* Enable ocp alarm , */\
{ 0x4840, "IEUVDS"}, /* Enable UVP alarm , */\
{ 0x4850, "IEMANALARM"}, /* Enable nanager Alarm state , */\
{ 0x4860, "IETDMER"}, /* Enable tdm error , */\
{ 0x4870, "IENOCLK"}, /* Enable lost clk , */\
{ 0x4880, "IEBODNOK"}, /* Enable BOD trigger , */\
{ 0x4c00, "IPOVDDS"}, /* Polarity por , */\
{ 0x4c10, "IPOBSTOC"}, /* Polarity DCDC OCP , */\
{ 0x4c20, "IPOOTDS"}, /* Polarity OTP alarm , */\
{ 0x4c30, "IPOOCPR"}, /* Polarity ocp alarm , */\
{ 0x4c40, "IPOUVDS"}, /* Polarity UVP alarm , */\
{ 0x4c50, "IPOMANALARM"}, /* Polarity nanager Alarm state , */\
{ 0x4c60, "IPOTDMER"}, /* Polarity tdm error , */\
{ 0x4c70, "IPONOCLK"}, /* Polarity lost clk , */\
{ 0x4c80, "IPOBODNOK"}, /* Polarity BOD trigger , */\
{ 0x5001, "BSSCR"}, /* Battery Safeguard attack time (with K = 1 at sample rate fs of 32kHz, 44,1 kHz or 48kHz ; with K = 2 at sample rate fs 16 kHz . With K =0.5 at sample rate of 96 kHz), */\
{ 0x5023, "BSST"}, /* Battery Safeguard threshold voltage level , */\
{ 0x5061, "BSSRL"}, /* Battery Safeguard maximum reduction , */\
{ 0x50e0, "BSSR"}, /* Battery voltage read out , */\
{ 0x50f0, "BSSBY"}, /* Bypass battery safeguard , */\
{ 0x5100, "BSSS"}, /* Vbat prot steepness , */\
{ 0x5150, "HPFBYP"}, /* Bypass HPF , */\
{ 0x5170, "DPSA"}, /* Enable DPSA , */\
{ 0x5222, "CLIPCTRL"}, /* Clip control setting , */\
{ 0x5257, "AMPGAIN"}, /* Amplifier gain , */\
{ 0x52d0, "SLOPEE"}, /* Enables slope control , */\
{ 0x52e0, "SLOPESET"}, /* Slope speed setting (bin. coded) , */\
{ 0x52f0, "BYPDLYLINE"}, /* Bypass the interpolator delay line , */\
{ 0x5f23, "TDMDCG"}, /* Second channel gain in case of stereo using a single coil. (Total gain depending on INPLEV). (In case of mono OR stereo using 2 separate DCDC channel 1 should be disabled using TDMDCE), */\
{ 0x5f63, "TDMSPKG"}, /* Total gain depending on INPLEV setting (channel 0), */\
{ 0x60e1, "IPM"}, /* Idle power mode control , */\
{ 0x62e1, "LNMODE"}, /* ctrl select mode , */\
{ 0x64e1, "LPM1MODE"}, /* low power mode control , */\
{ 0x6802, "TDMSRCMAP"}, /* tdm source mapping , */\
{ 0x6831, "TDMSRCAS"}, /* Sensed value A , */\
{ 0x6851, "TDMSRCBS"}, /* Sensed value B , */\
{ 0x6871, "TDMSRCACLIP"}, /* clip information (analog /digital) for source0 , */\
{ 0x6891, "TDMSRCBCLIP"}, /* clip information (analog /digital) for source1 , */\
{ 0x6e00, "LP0"}, /* Idle power mode , */\
{ 0x6e10, "LP1"}, /* low power mode 1 detection , */\
{ 0x6e20, "LA"}, /* low amplitude detection , */\
{ 0x6e30, "VDDPH"}, /* vddp greater than vbat , */\
{ 0x6f02, "DELCURCOMP"}, /* delay to allign compensation signal with current sense signal, */\
{ 0x6f40, "SIGCURCOMP"}, /* polarity of compensation for current sense , */\
{ 0x6f50, "ENCURCOMP"}, /* enable current sense compensation , */\
{ 0x6f72, "LVLCLPPWM"}, /* set the amount of pwm pulse that may be skipped before clip-flag is triggered, */\
{ 0x7003, "DCMCC"}, /* Max coil current , */\
{ 0x7041, "DCCV"}, /* Slope compensation current, represents LxF (inductance x frequency) value , */\
{ 0x7060, "DCIE"}, /* Adaptive boost mode , */\
{ 0x7070, "DCSR"}, /* Soft ramp up/down , */\
{ 0x7085, "DCOVL"}, /* Threshold level to activate active overshoot control, */\
{ 0x70e0, "DCDIS"}, /* DCDC on/off , */\
{ 0x70f0, "DCPWM"}, /* DCDC PWM only mode , */\
{ 0x7430, "DCTRACK"}, /* Boost algorithm selection, effective only when boost_intelligent is set to 1, */\
{ 0x7444, "DCTRIP"}, /* 1st Adaptive boost trip levels, effective only when DCIE is set to 1, */\
{ 0x7494, "DCHOLD"}, /* Hold time for DCDC booster, effective only when boost_intelligent is set to 1, */\
{ 0x74e0, "DCINT"}, /* Selection of data for adaptive boost algorithm, effective only when boost_intelligent is set to 1, */\
{ 0x7534, "DCTRIP2"}, /* 2nd Adaptive boost trip levels, effective only when DCIE is set to 1, */\
{ 0x7584, "DCTRIPT"}, /* Track Adaptive boost trip levels, effective only when boost_intelligent is set to 1, */\
{ 0x75f0, "DCTRIPHYSTE"}, /* Enable hysteresis on booster trip levels , */\
{ 0x7635, "DCVOF"}, /* First boost voltage level , */\
{ 0x7695, "DCVOS"}, /* Second boost voltage level , */\
{ 0xa107, "MTPK"}, /* MTP KEY2 register , */\
{ 0xa200, "KEY1LOCKED"}, /* Indicates KEY1 is locked , */\
{ 0xa210, "KEY2LOCKED"}, /* Indicates KEY2 is locked , */\
{ 0xa302, "MTPADDR"}, /* MTP address from I2C register for read/writing mtp in manual single word mode, */\
{ 0xa50f, "MTPRDMSB"}, /* MSB word of MTP manual read data , */\
{ 0xa60f, "MTPRDLSB"}, /* LSB word of MTP manual read data , */\
{ 0xa70f, "MTPWRMSB"}, /* MSB word of write data for MTP manual write , */\
{ 0xa80f, "MTPWRLSB"}, /* LSB word of write data for MTP manual write , */\
{ 0xb108, "EXTTS"}, /* External temperature (C) , */\
{ 0xb190, "TROS"}, /* Select temp Speaker calibration , */\
{ 0xcd05, "PLLINSI"}, /* PLL INSELI - PLL direct bandwidth control mode only with pll_bandsel set to 1, */\
{ 0xcd64, "PLLINSP"}, /* PLL INSELP - PLL direct bandwidth control mode only with pll_bandsel set to 1, */\
{ 0xcdb3, "PLLINSR"}, /* PLL INSELR - PLL direct bandwidth control mode only with pll_bandsel set to 1, */\
{ 0xcdf0, "PLLBDSEL"}, /* PLL bandwidth selection control, USE WITH CAUTION , */\
{ 0xce09, "PLLNDEC"}, /* PLL NDEC in direct control mode only, use_direct_pll_ctrl set to 1, */\
{ 0xcea0, "PLLMDECM"}, /* MSB of PLL MDEC in direct control mode only, use_direct_pll_ctrl set to 1, */\
{ 0xceb0, "PLLBP"}, /* PLL bypass control during functional mode , */\
{ 0xcec0, "PLLDI"}, /* PLL directi control in direct control mode only, use_direct_pll_ctrl set to 1, */\
{ 0xced0, "PLLDO"}, /* PLL directo control in direct control mode only, use_direct_pll_ctrl set to 1, */\
{ 0xcee0, "PLLCLKSTB"}, /* PLL FRM clock stable control in direct control mode only, use_direct_pll_ctrl set to 1, */\
{ 0xcef0, "PLLFRM"}, /* PLL free running mode control in functional mode , */\
{ 0xcf0f, "PLLMDECL"}, /* Bits 15..0 of PLL MDEC in direct control mode only, use_direct_pll_ctrl set to 1, */\
{ 0xd006, "PLLPDEC"}, /* PLL PDEC in direct control mode only, use_direct_pll_ctrl set to 1, */\
{ 0xd070, "PLLDCTRL"}, /* Enabled PLL direct control mode, overrules the PLL LUT with I2C register values, */\
{ 0xd090, "PLLLIMOFF"}, /* PLL up limiter control in PLL direct bandwidth control mode, pll_bandsel set to 1, */\
{ 0xd0a2, "PLLSTRTM"}, /* PLL startup time selection control , */\
{ 0xe00f, "SWPROFIL"}, /* Software profile data , */\
{ 0xe10f, "SWVSTEP"}, /* Software vstep information , */\
{ 0xf000, "MTPOTC"}, /* Calibration schedule , */\
{ 0xf010, "MTPEX"}, /* Calibration Ron executed , */\
{ 0xf020, "DCMCCAPI"}, /* Calibration current limit DCDC , */\
{ 0xf030, "DCMCCSB"}, /* Sign bit for delta calibration current limit DCDC , */\
{ 0xf042, "USERDEF"}, /* Calibration delta current limit DCDC , */\
{ 0xf078, "CUSTINFO"}, /* Reserved space for allowing customer to store speaker information, */\
{ 0xf50f, "R25C"}, /* Ron resistance of speaker coil , */\
{ 0xffff,"Unknown bitfield enum" } /* not found */\
};
#define TFA9878_BITNAMETABLE static tfaBfName_t Tfa9878BitNames[]= {\
{ 0x0, "powerdown"}, /* Powerdown selection , */\
{ 0x10, "reset"}, /* I2C Reset - Auto clear , */\
{ 0x30, "enbl_amplifier"}, /* Activate Amplifier , */\
{ 0x40, "enbl_boost"}, /* Activate DC-to-DC converter , */\
{ 0x71, "int_pad_io"}, /* Interrupt config , */\
{ 0x90, "fs_pulse_sel"}, /* Audio sample reference , */\
{ 0xb0, "bypass_ocp"}, /* Bypass OCP , */\
{ 0xc0, "test_ocp"}, /* OCP testing control , */\
{ 0xd0, "sel_man_wait_time"}, /* Manager wait time selection control , */\
{ 0x101, "vamp_sel1"}, /* Amplifier input selection , */\
{ 0x120, "src_set_configured"}, /* I2C configured , */\
{ 0x131, "vamp_sel2"}, /* VAMP_OUT2 input selection , */\
{ 0x160, "disable_mute_time_out"}, /* Time out SB mute sequence , */\
{ 0x170, "man_enbl_brown"}, /* Reaction on BOD , */\
{ 0x180, "bod_enbl"}, /* Enable BOD (only in direct control mode) , */\
{ 0x190, "bod_hyst_enbl"}, /* Enable Hysteresis of BOD , */\
{ 0x1a1, "bod_delay_set"}, /* BOD filter , */\
{ 0x1c1, "bod_lvl_set"}, /* BOD threshold , */\
{ 0x1e0, "unprotect_faim"}, /* Control for FAIM protection , */\
{ 0x1f0, "disable_frcbst"}, /* disable boost control with FRCBST , */\
{ 0x203, "audio_fs"}, /* Sample rate (fs) , */\
{ 0x240, "input_level"}, /* TDM output attenuation , */\
{ 0x255, "cs_frac_delay"}, /* V/I Fractional delay , */\
{ 0x2b1, "amp_input_sel"}, /* amp input selection , */\
{ 0x2d0, "pdm_rate"}, /* Pdm rate , */\
{ 0x30f, "device_rev"}, /* Revision info , */\
{ 0x401, "pll_clkin_sel"}, /* PLL external ref clock , */\
{ 0x420, "pll_clkin_sel_osc"}, /* PLL internal ref clock , */\
{ 0x432, "sw_clk_sel"}, /* Sound Wire clock frequnecy , */\
{ 0x460, "enbl_osc_auto_off"}, /* Internal osc off at PWDN , */\
{ 0x480, "enbl_fs_sync"}, /* Enable FS synchronisation for clock divider , */\
{ 0x490, "enbl_clkref_sync"}, /* Enable PLL reference clock synchronisation for clock divider, */\
{ 0x4a0, "override_auto_sel_osc"}, /* override automatic OSC selection mechanism , */\
{ 0x4b0, "sw_sync_sel"}, /* Selection SW signal reference for Stream Synchronization , */\
{ 0x500, "disable_cgu_sync_cgate"}, /* Clock gating control for CGU synchronisation module, */\
{ 0x510, "force_spkr_clk"}, /* force active the speaker sub-system clock when in idle power, */\
{ 0x5c0, "enbl_faim_ss"}, /* Sub-system FAIM , */\
{ 0x707, "clkchk_th_lo"}, /* Clock check Low Threshold , */\
{ 0x787, "clkchk_th_hi"}, /* Clock check Higher Threshold , */\
{ 0x802, "ctrl_on2off_criterion"}, /* Amplifier on-off criteria for shutdown , */\
{ 0xe07, "ctrl_digtoana"}, /* Spare control from digital to analog , */\
{ 0xf0f, "hidden_code"}, /* 5A6Bh, 23147d to access registers (default for engineering), */\
{ 0x1000, "flag_por"}, /* POR , */\
{ 0x1010, "flag_bst_ocpok"}, /* DCDC OCP nmos (sticky register , clear on read) , */\
{ 0x1020, "flag_otpok"}, /* OTP alarm (sticky register , clear on read) , */\
{ 0x1030, "flag_ocp_alarm"}, /* OCP amplifier (sticky register , clear on read), */\
{ 0x1040, "flag_uvpok"}, /* UVP alarm (sticky register , clear on read) , */\
{ 0x1050, "flag_man_alarm_state"}, /* Alarm state , */\
{ 0x1060, "flag_clocks_stable"}, /* Clocks stable , */\
{ 0x1070, "flag_mtp_busy"}, /* MTP busy , */\
{ 0x1080, "flag_lost_clk"}, /* Lost clock (sticky register , clear on read) , */\
{ 0x1090, "flag_bod_vddd_nok"}, /* BOD Flag - VDD NOT OK , */\
{ 0x10a0, "flag_tdm_error"}, /* TDM error , */\
{ 0x1100, "flag_bst_bstcur"}, /* DCDC current limiting , */\
{ 0x1110, "flag_bst_hiz"}, /* DCDC active (sticky register , clear on read) , */\
{ 0x1120, "flag_bst_peakcur"}, /* Indicates current is max in DC-to-DC converter , */\
{ 0x1130, "flag_bst_voutcomp"}, /* DCDC level 1x , */\
{ 0x1140, "flag_bst_voutcomp86"}, /* DCDC level 1.14x , */\
{ 0x1150, "flag_bst_voutcomp93"}, /* DCDC level 1.07x , */\
{ 0x1160, "flag_pll_lock"}, /* PLL lock , */\
{ 0x1180, "flag_tdm_lut_error"}, /* TDM LUT error , */\
{ 0x11c0, "flag_clk_out_of_range"}, /* External clock status , */\
{ 0x11d0, "flag_engage"}, /* Amplifier engage , */\
{ 0x11e0, "flag_enbl_amp"}, /* Amplifier enable , */\
{ 0x11f0, "flag_enbl_ref"}, /* References enable , */\
{ 0x1300, "flag_ocpokbp"}, /* OCPOK pmos B , */\
{ 0x1310, "flag_ocpokap"}, /* OCPOK pmos A , */\
{ 0x1320, "flag_ocpokbn"}, /* OCPOK nmos B , */\
{ 0x1330, "flag_ocpokan"}, /* OCPOK nmos A , */\
{ 0x1380, "flag_ovpok"}, /* OVP alarm , */\
{ 0x1390, "flag_clip"}, /* Amplifier clipping , */\
{ 0x13a0, "flag_adc10_ready"}, /* Control ADC , */\
{ 0x13c0, "flag_man_wait_src_settings"}, /* Wait HW I2C settings , */\
{ 0x13e0, "flag_man_start_mute_audio"}, /* Audio mute sequence , */\
{ 0x13f0, "flag_man_operating_state"}, /* Operating state , */\
{ 0x1402, "flag_tdm_status"}, /* TDM status bits , */\
{ 0x1433, "man_state"}, /* Device manager status , */\
{ 0x1473, "amp_ctrl_state"}, /* Amplifier control status , */\
{ 0x14b1, "status_bst_mode"}, /* DCDC mode status bits , */\
{ 0x1509, "bat_adc"}, /* Battery voltage (V) , */\
{ 0x1608, "temp_adc"}, /* IC Temperature (C) , */\
{ 0x1709, "vddp_adc"}, /* IC VDDP voltage ( 1023*VDDP/13 V) , */\
{ 0x2000, "tdm_enable"}, /* Enable interface , */\
{ 0x2013, "tdm_nb_of_slots"}, /* N-slots in Frame , */\
{ 0x2060, "tdm_clk_inversion"}, /* Reception data to BCK clock , */\
{ 0x2073, "tdm_fs_ws_length"}, /* FS length , */\
{ 0x20b0, "tdm_fs_ws_polarity"}, /* FS polarity , */\
{ 0x20c3, "tdm_nbck"}, /* N-BCK's in FS , */\
{ 0x2144, "tdm_slot_length"}, /* N-bits in slot , */\
{ 0x2194, "tdm_bits_remaining"}, /* N-bits remaining , */\
{ 0x21e0, "tdm_data_delay"}, /* data delay to FS , */\
{ 0x21f0, "tdm_data_adjustment"}, /* data adjustment , */\
{ 0x2201, "tdm_audio_sample_compression"}, /* Received audio compression , */\
{ 0x2224, "tdm_sample_size"}, /* Sample size per slot , */\
{ 0x2271, "tdm_txdata_format"}, /* Format unused bits , */\
{ 0x2291, "tdm_txdata_format_unused_slot_sd0"}, /* Format unused slots DATAO , */\
{ 0x2300, "tdm_sink0_enable"}, /* Control audio tdm channel in 0 , */\
{ 0x2310, "tdm_sink1_enable"}, /* Control audio tdm channel in 1 , */\
{ 0x2330, "tdm_source0_enable"}, /* current sense vbat temperature and vddp feedback , */\
{ 0x2340, "tdm_source1_enable"}, /* Voltage sense vbat temperature and vddp feedback , */\
{ 0x2603, "tdm_sink0_slot"}, /* tdm slot for sink 0 , */\
{ 0x2643, "tdm_sink1_slot"}, /* tdm slot for sink 1 , */\
{ 0x26c3, "tdm_source0_slot"}, /* Slot Position of current sense vbat temperature and vddp feedback, */\
{ 0x2703, "tdm_source1_slot"}, /* Slot Position of Voltage sense vbat temperature and vddp feedback, */\
{ 0x4000, "int_out_flag_por"}, /* Status POR , */\
{ 0x4010, "int_out_flag_bst_ocpok"}, /* Status DCDC OCP , */\
{ 0x4020, "int_out_flag_otpok"}, /* Status OTP alarm , */\
{ 0x4030, "int_out_flag_ocp_alarm"}, /* Status ocp alarm , */\
{ 0x4040, "int_out_flag_uvpok"}, /* Status UVP alarm , */\
{ 0x4050, "int_out_flag_man_alarm_state"}, /* Status nanager Alarm state , */\
{ 0x4060, "int_out_flag_tdm_error"}, /* Status tdm error , */\
{ 0x4070, "int_out_flag_lost_clk"}, /* Status lost clock , */\
{ 0x4080, "int_out_flag_bod_vddd_nok"}, /* Status BOD event , */\
{ 0x4400, "int_in_flag_por"}, /* Clear POR , */\
{ 0x4410, "int_in_flag_bst_ocpok"}, /* Clear DCDC OCP , */\
{ 0x4420, "int_in_flag_otpok"}, /* Clear OTP alarm , */\
{ 0x4430, "int_in_flag_ocp_alarm"}, /* Clear ocp alarm , */\
{ 0x4440, "int_in_flag_uvpok"}, /* Clear UVP alarm , */\
{ 0x4450, "int_in_flag_man_alarm_state"}, /* Clear manager Alarm state , */\
{ 0x4460, "int_in_flag_tdm_error"}, /* Clear tdm error , */\
{ 0x4470, "int_in_flag_lost_clk"}, /* Clear lost clk , */\
{ 0x4480, "int_in_flag_bod_vddd_nok"}, /* Clear BOD event , */\
{ 0x4800, "int_enable_flag_por"}, /* Enable por , */\
{ 0x4810, "int_enable_flag_bst_ocpok"}, /* Enable DCDC OCP , */\
{ 0x4820, "int_enable_flag_otpok"}, /* Enable OTP alarm , */\
{ 0x4830, "int_enable_flag_ocp_alarm"}, /* Enable ocp alarm , */\
{ 0x4840, "int_enable_flag_uvpok"}, /* Enable UVP alarm , */\
{ 0x4850, "int_enable_flag_man_alarm_state"}, /* Enable nanager Alarm state , */\
{ 0x4860, "int_enable_flag_tdm_error"}, /* Enable tdm error , */\
{ 0x4870, "int_enable_flag_lost_clk"}, /* Enable lost clk , */\
{ 0x4880, "int_enable_flag_bod_vddd_nok"}, /* Enable BOD trigger , */\
{ 0x4c00, "int_polarity_flag_por"}, /* Polarity por , */\
{ 0x4c10, "int_polarity_flag_bst_ocpok"}, /* Polarity DCDC OCP , */\
{ 0x4c20, "int_polarity_flag_otpok"}, /* Polarity OTP alarm , */\
{ 0x4c30, "int_polarity_flag_ocp_alarm"}, /* Polarity ocp alarm , */\
{ 0x4c40, "int_polarity_flag_uvpok"}, /* Polarity UVP alarm , */\
{ 0x4c50, "int_polarity_flag_man_alarm_state"}, /* Polarity nanager Alarm state , */\
{ 0x4c60, "int_polarity_flag_tdm_error"}, /* Polarity tdm error , */\
{ 0x4c70, "int_polarity_flag_lost_clk"}, /* Polarity lost clk , */\
{ 0x4c80, "int_polarity_flag_bod_vddd_nok"}, /* Polarity BOD trigger , */\
{ 0x5001, "vbat_prot_attack_time"}, /* Battery Safeguard attack time (with K = 1 at sample rate fs of 32kHz, 44,1 kHz or 48kHz ; with K = 2 at sample rate fs 16 kHz . With K =0.5 at sample rate of 96 kHz), */\
{ 0x5023, "vbat_prot_thlevel"}, /* Battery Safeguard threshold voltage level , */\
{ 0x5061, "vbat_prot_max_reduct"}, /* Battery Safeguard maximum reduction , */\
{ 0x50d0, "rst_min_vbat"}, /* Reset clipper - Auto clear , */\
{ 0x50e0, "sel_vbat"}, /* Battery voltage read out , */\
{ 0x50f0, "bypass_clipper"}, /* Bypass battery safeguard , */\
{ 0x5100, "batsense_steepness"}, /* Vbat prot steepness , */\
{ 0x5150, "bypass_hp"}, /* Bypass HPF , */\
{ 0x5170, "enbl_dpsa"}, /* Enable DPSA , */\
{ 0x5222, "ctrl_cc"}, /* Clip control setting , */\
{ 0x5257, "gain"}, /* Amplifier gain , */\
{ 0x52d0, "ctrl_slopectrl"}, /* Enables slope control , */\
{ 0x52e0, "ctrl_slope"}, /* Slope speed setting (bin. coded) , */\
{ 0x52f0, "bypass_dly_line"}, /* Bypass the interpolator delay line , */\
{ 0x5301, "dpsa_level"}, /* DPSA threshold levels , */\
{ 0x5321, "dpsa_release"}, /* DPSA Release time , */\
{ 0x5350, "bypass_lp"}, /* Bypass the low pass filter inside temperature sensor, */\
{ 0x5400, "first_order_mode"}, /* Overrule to 1st order mode of control stage when clipping, */\
{ 0x5430, "icomp_engage"}, /* Engage of icomp , */\
{ 0x5440, "ctrl_kickback"}, /* Prevent double pulses of output stage , */\
{ 0x5450, "icomp_engage_overrule"}, /* To overrule the functional icomp_engage signal during validation, */\
{ 0x5463, "ctrl_dem"}, /* Enable DEM icomp and DEM one bit dac , */\
{ 0x5500, "bypass_ctrlloop"}, /* Switch amplifier into open loop configuration , */\
{ 0x5513, "ctrl_dem_mismatch"}, /* Enable DEM icomp mismatch for testing , */\
{ 0x5552, "dpsa_drive"}, /* Drive setting (bin. coded) , */\
{ 0x5600, "ref_iref_enbl"}, /* Enable of reference current for OCP , */\
{ 0x5631, "ref_irefdist_set_ctrl"}, /* Scaling of reference current for OCP , */\
{ 0x5652, "ref_irefdist_test_enbl"}, /* Enable of test-function of distribution of reference current, used for OCP. When enabled, the current will to to anamux iso powerstages. Using e.g. 011 it will add the current of powerstage P and N., */\
{ 0x570a, "enbl_amp"}, /* Switch on the class-D power sections, each part of the analog sections can be switched on/off individually, */\
{ 0x57b0, "enbl_engage"}, /* Enables/engage power stage and control loop , */\
{ 0x57c0, "enbl_engage_pst"}, /* Enables/engage power stage and control loop , */\
{ 0x5810, "hard_mute"}, /* Hard mute - PWM , */\
{ 0x5844, "pwm_delay"}, /* PWM delay bits to set the delay, clockd is 1/(k*2048*fs), */\
{ 0x5890, "reclock_pwm"}, /* Reclock the pwm signal inside analog , */\
{ 0x58a0, "reclock_voltsense"}, /* Reclock the voltage sense pwm signal , */\
{ 0x58c0, "enbl_pwm_phase_shift"}, /* Control for pwm phase shift , */\
{ 0x5900, "pwm_clk_sel"}, /* Control for selection for PWM delay line source , */\
{ 0x5910, "sel_pwm_delay_src"}, /* Control for selection for PWM delay line source , */\
{ 0x5f23, "ctrl_attl"}, /* Second channel gain in case of stereo using a single coil. (Total gain depending on INPLEV). (In case of mono OR stereo using 2 separate DCDC channel 1 should be disabled using TDMDCE), */\
{ 0x5f63, "ctrl_attr"}, /* Total gain depending on INPLEV setting (channel 0), */\
{ 0x6005, "idle_power_cal_offset"}, /* Idle power mode detector ctrl cal_offset from gain module , */\
{ 0x6065, "idle_power_zero_lvl"}, /* IIdle power mode zero crossing detection level , */\
{ 0x60e1, "idle_power_mode"}, /* Idle power mode control , */\
{ 0x6105, "idle_power_threshold_lvl"}, /* Idle power mode amplitude trigger level , */\
{ 0x6165, "idle_power_hold_time"}, /* Idle power mode detector ctrl hold time before low audio is reckoned to be low audio, */\
{ 0x61c0, "disable_idle_power_mode"}, /* Idle power mode detector control , */\
{ 0x6265, "zero_lvl"}, /* low noise gain switch zero trigger level , */\
{ 0x62c1, "ctrl_fb_resistor"}, /* Select amplifier feedback resistor connection , */\
{ 0x62e1, "lownoisegain_mode"}, /* ctrl select mode , */\
{ 0x6305, "threshold_lvl"}, /* low noise gain switch trigger level , */\
{ 0x6365, "hold_time"}, /* ctrl hold time before low audio is reckoned to be low audio, */\
{ 0x6405, "lpm1_cal_offset"}, /* low power mode1 detector ctrl cal_offset from gain module , */\
{ 0x6465, "lpm1_zero_lvl"}, /* low power mode1 zero crossing detection level , */\
{ 0x64e1, "lpm1_mode"}, /* low power mode control , */\
{ 0x6505, "lpm1_threshold_lvl"}, /* low power mode1 amplitude trigger level , */\
{ 0x6565, "lpm1_hold_time"}, /* low power mode1 detector ctrl hold time before low audio is reckoned to be low audio, */\
{ 0x65c0, "disable_low_power_mode"}, /* low power mode1 detector control , */\
{ 0x6600, "dcdc_pfm20khz_limit"}, /* DCDC in PFM mode pwm mode is activated each 50us to force a pwm pulse, */\
{ 0x6611, "dcdc_ctrl_maxzercnt"}, /* DCDC. Number of zero current flags to count before going to pfm mode, */\
{ 0x6656, "dcdc_vbat_delta_detect"}, /* Threshold before booster is reacting on a delta Vbat (in PFM mode) by temporarily switching to PWM mode, */\
{ 0x66c0, "dcdc_ignore_vbat"}, /* Ignore an increase on Vbat , */\
{ 0x6700, "enbl_minion"}, /* Enables minion (small) power stage , */\
{ 0x6713, "vth_vddpvbat"}, /* select vddp-vbat thres signal , */\
{ 0x6750, "lpen_vddpvbat"}, /* select vddp-vbat filtred vs unfiltered compare , */\
{ 0x6761, "ctrl_rfb"}, /* Feedback resistor selection - I2C direct mode , */\
{ 0x6802, "tdm_source_mapping"}, /* tdm source mapping , */\
{ 0x6831, "tdm_sourcea_frame_sel"}, /* Sensed value A , */\
{ 0x6851, "tdm_sourceb_frame_sel"}, /* Sensed value B , */\
{ 0x6871, "tdm_source0_clip_sel"}, /* clip information (analog /digital) for source0 , */\
{ 0x6891, "tdm_source1_clip_sel"}, /* clip information (analog /digital) for source1 , */\
{ 0x6a02, "rst_min_vbat_delay"}, /* rst_min_vbat delay (nb fs) , */\
{ 0x6b00, "disable_auto_engage"}, /* disable auto engange , */\
{ 0x6b10, "disable_engage"}, /* disable engange , */\
{ 0x6c02, "ns_hp2ln_criterion"}, /* 0..7 zeroes at ns as threshold to swap from high_power to low_noise, */\
{ 0x6c32, "ns_ln2hp_criterion"}, /* 0..7 zeroes at ns as threshold to swap from low_noise to high_power, */\
{ 0x6c69, "spare_out"}, /* spare_out , */\
{ 0x6d0f, "spare_in"}, /* spare_in , */\
{ 0x6e00, "flag_idle_power_mode"}, /* Idle power mode , */\
{ 0x6e10, "flag_lp_detect_mode1"}, /* low power mode 1 detection , */\
{ 0x6e20, "flag_low_amplitude"}, /* low amplitude detection , */\
{ 0x6e30, "flag_vddp_gt_vbat"}, /* vddp greater than vbat , */\
{ 0x6f02, "cursense_comp_delay"}, /* delay to allign compensation signal with current sense signal, */\
{ 0x6f40, "cursense_comp_sign"}, /* polarity of compensation for current sense , */\
{ 0x6f50, "enbl_cursense_comp"}, /* enable current sense compensation , */\
{ 0x6f72, "pwms_clip_lvl"}, /* set the amount of pwm pulse that may be skipped before clip-flag is triggered, */\
{ 0x7003, "boost_cur"}, /* Max coil current , */\
{ 0x7041, "bst_slpcmplvl"}, /* Slope compensation current, represents LxF (inductance x frequency) value , */\
{ 0x7060, "boost_intel"}, /* Adaptive boost mode , */\
{ 0x7070, "boost_speed"}, /* Soft ramp up/down , */\
{ 0x7085, "overshoot_correction_lvl"}, /* Threshold level to activate active overshoot control, */\
{ 0x70e0, "dcdcoff_mode"}, /* DCDC on/off , */\
{ 0x70f0, "dcdc_pwmonly"}, /* DCDC PWM only mode , */\
{ 0x7104, "bst_drive"}, /* Binary coded drive setting for boost converter power stage, */\
{ 0x7151, "bst_scalecur"}, /* For testing direct control scale current , */\
{ 0x7174, "bst_slopecur"}, /* For testing direct control slope current , */\
{ 0x71c1, "bst_slope"}, /* Boost slope speed , */\
{ 0x71e0, "bst_bypass_bstcur"}, /* Bypass control for boost current settings , */\
{ 0x71f0, "bst_bypass_bstfoldback"}, /* Bypass control for boost foldback , */\
{ 0x7200, "enbl_bst_engage"}, /* Enable power stage dcdc controller , */\
{ 0x7210, "enbl_bst_hizcom"}, /* Enable hiz comparator , */\
{ 0x7220, "enbl_bst_peak2avg"}, /* Enable boost peak2avg functionality , */\
{ 0x7230, "enbl_bst_peakcur"}, /* Enable peak current , */\
{ 0x7240, "enbl_bst_power"}, /* Enable line of the powerstage , */\
{ 0x7250, "enbl_bst_slopecur"}, /* Enable bit of max-current dac , */\
{ 0x7260, "enbl_bst_voutcomp"}, /* Enable vout comparators , */\
{ 0x7270, "enbl_bst_voutcomp86"}, /* Enable vout-86 comparators , */\
{ 0x7280, "enbl_bst_voutcomp93"}, /* Enable vout-93 comparators , */\
{ 0x7290, "enbl_bst_windac"}, /* Enable window dac , */\
{ 0x72a5, "bst_windac"}, /* for testing direct control windac , */\
{ 0x7300, "boost_alg"}, /* Control for boost adaptive loop gain , */\
{ 0x7311, "boost_loopgain"}, /* DCDC boost loopgain setting , */\
{ 0x7331, "bst_freq"}, /* DCDC boost frequency control , */\
{ 0x7360, "bst_use_new_zercur_detect"}, /* Enable new zero current detection for boost control, */\
{ 0x7430, "boost_track"}, /* Boost algorithm selection, effective only when boost_intelligent is set to 1, */\
{ 0x7444, "boost_trip_lvl_1st"}, /* 1st Adaptive boost trip levels, effective only when DCIE is set to 1, */\
{ 0x7494, "boost_hold_time"}, /* Hold time for DCDC booster, effective only when boost_intelligent is set to 1, */\
{ 0x74e0, "sel_dcdc_envelope_8fs"}, /* Selection of data for adaptive boost algorithm, effective only when boost_intelligent is set to 1, */\
{ 0x74f0, "ignore_flag_voutcomp86"}, /* Determines the maximum PWM frequency be the most efficient in relation to the Booster inductor value, */\
{ 0x7534, "boost_trip_lvl_2nd"}, /* 2nd Adaptive boost trip levels, effective only when DCIE is set to 1, */\
{ 0x7584, "boost_trip_lvl_track"}, /* Track Adaptive boost trip levels, effective only when boost_intelligent is set to 1, */\
{ 0x75f0, "enbl_trip_hyst"}, /* Enable hysteresis on booster trip levels , */\
{ 0x7635, "frst_boost_voltage"}, /* First boost voltage level , */\
{ 0x7695, "scnd_boost_voltage"}, /* Second boost voltage level , */\
{ 0x8050, "cs_gain_control"}, /* Current sense gain control , */\
{ 0x8060, "cs_bypass_gc"}, /* Bypasses the CS gain correction , */\
{ 0x8087, "cs_gain"}, /* Current sense gain , */\
{ 0x8210, "invertpwm"}, /* Current sense common mode feedback pwm invert control, */\
{ 0x8305, "cs_ktemp"}, /* Current sense temperature compensation trimming (1 - VALUE*TEMP)*signal, */\
{ 0x8364, "cs_ktemp2"}, /* Second order temperature compensation coefficient , */\
{ 0x8400, "cs_adc_bsoinv"}, /* Bitstream inversion for current sense ADC , */\
{ 0x8440, "cs_adc_nortz"}, /* Return to zero for current sense ADC , */\
{ 0x8490, "cs_adc_slowdel"}, /* Select delay for current sense ADC (internal decision circuitry), */\
{ 0x8510, "cs_classd_tran_skip"}, /* Skip current sense connection during a classD amplifier transition, */\
{ 0x8530, "cs_inn_short"}, /* Short current sense negative to common mode , */\
{ 0x8540, "cs_inp_short"}, /* Short current sense positive to common mode , */\
{ 0x8550, "cs_ldo_bypass"}, /* Bypass current sense LDO , */\
{ 0x8560, "cs_ldo_pulldown"}, /* Pull down current sense LDO, only valid if left_enbl_cs_ldo is high, */\
{ 0x8574, "cs_ldo_voset"}, /* Current sense LDO voltage level setting (two's complement), */\
{ 0x8700, "enbl_cs_adc"}, /* Enable current sense ADC , */\
{ 0x8710, "enbl_cs_inn1"}, /* Enable connection of current sense negative1 , */\
{ 0x8720, "enbl_cs_inn2"}, /* Enable connection of current sense negative2 , */\
{ 0x8730, "enbl_cs_inp1"}, /* Enable connection of current sense positive1 , */\
{ 0x8740, "enbl_cs_inp2"}, /* Enable connection of current sense positive2 , */\
{ 0x8750, "enbl_cs_ldo"}, /* Enable current sense LDO , */\
{ 0x8780, "enbl_cs_vbatldo"}, /* Enable of current sense LDO , */\
{ 0x8790, "enbl_dc_filter"}, /* Control for enabling the DC blocking filter for voltage and current sense, */\
{ 0x8850, "vs_gain_control"}, /* Voltage sense gain control , */\
{ 0x8860, "vs_bypass_gc"}, /* Bypasses the VS gain correction , */\
{ 0x8887, "vs_gain"}, /* voltage sense gain , */\
{ 0x8c00, "vs_adc_bsoinv"}, /* Bitstream inversion for voltage sense ADC , */\
{ 0x8c40, "vs_adc_nortz"}, /* Return to zero for voltage sense ADC , */\
{ 0x8c90, "vs_adc_slowdel"}, /* Select delay for voltage sense ADC (internal decision circuitry), */\
{ 0x8d30, "vs_inn_short"}, /* Short voltage sense negative to common mode , */\
{ 0x8d40, "vs_inp_short"}, /* Short voltage sense positive to common mode , */\
{ 0x8d50, "vs_ldo_bypass"}, /* Bypass voltage sense LDO , */\
{ 0x8d60, "vs_ldo_pulldown"}, /* Pull down voltage sense LDO, only valid if left_enbl_cs_ldo is high, */\
{ 0x8d74, "vs_ldo_voset"}, /* Voltage sense LDO voltage level setting (two's complement), */\
{ 0x8f00, "enbl_vs_adc"}, /* Enable voltage sense ADC (Direct Control only only others done by manager), */\
{ 0x8f10, "enbl_vs_inn1"}, /* Enable connection of voltage sense negative1 , */\
{ 0x8f20, "enbl_vs_inn2"}, /* Enable connection of voltage sense negative2 , */\
{ 0x8f30, "enbl_vs_inp1"}, /* Enable connection of voltage sense positive1 , */\
{ 0x8f40, "enbl_vs_inp2"}, /* Enable connection of voltage sense positive2 , */\
{ 0x8f50, "enbl_vs_ldo"}, /* Enable voltage sense LDO (Direct Control only only others done by manager), */\
{ 0x8f80, "enbl_vs_vbatldo"}, /* Enable of voltage sense LDO (Direct Control only others done by manager), */\
{ 0xa007, "mtpkey1"}, /* 5Ah, 90d To access KEY1_Protected registers (Default for engineering), */\
{ 0xa107, "mtpkey2"}, /* MTP KEY2 register , */\
{ 0xa200, "key01_locked"}, /* Indicates KEY1 is locked , */\
{ 0xa210, "key02_locked"}, /* Indicates KEY2 is locked , */\
{ 0xa302, "mtp_man_address_in"}, /* MTP address from I2C register for read/writing mtp in manual single word mode, */\
{ 0xa330, "man_copy_mtp_to_iic"}, /* Start copying single word from mtp to I2C mtp register, */\
{ 0xa340, "man_copy_iic_to_mtp"}, /* Start copying single word from I2C mtp register to mtp, */\
{ 0xa350, "auto_copy_mtp_to_iic"}, /* Start copying all the data from mtp to I2C mtp registers, */\
{ 0xa360, "auto_copy_iic_to_mtp"}, /* Start copying data from I2C mtp registers to mtp , */\
{ 0xa400, "faim_set_clkws"}, /* Sets the faim controller clock wait state register, */\
{ 0xa410, "faim_sel_evenrows"}, /* All even rows of the faim are selected, active high, */\
{ 0xa420, "faim_sel_oddrows"}, /* All odd rows of the faim are selected, all rows in combination with sel_evenrows, */\
{ 0xa430, "faim_program_only"}, /* Skip the erase access at wr_faim command (write-program-marginread), */\
{ 0xa440, "faim_erase_only"}, /* Skip the program access at wr_faim command (write-erase-marginread), */\
{ 0xa50f, "mtp_man_data_out_msb"}, /* MSB word of MTP manual read data , */\
{ 0xa60f, "mtp_man_data_out_lsb"}, /* LSB word of MTP manual read data , */\
{ 0xa70f, "mtp_man_data_in_msb"}, /* MSB word of write data for MTP manual write , */\
{ 0xa80f, "mtp_man_data_in_lsb"}, /* LSB word of write data for MTP manual write , */\
{ 0xb010, "bypass_ocpcounter"}, /* Bypass OCP Counter , */\
{ 0xb020, "bypass_glitchfilter"}, /* Bypass glitch filter , */\
{ 0xb030, "bypass_ovp"}, /* Bypass OVP , */\
{ 0xb040, "bypass_uvp"}, /* Bypass UVP , */\
{ 0xb050, "bypass_otp"}, /* Bypass OTP , */\
{ 0xb060, "bypass_lost_clk"}, /* Bypass lost clock detector , */\
{ 0xb070, "ctrl_vpalarm"}, /* vpalarm (uvp ovp handling) , */\
{ 0xb087, "ocp_threshold"}, /* OCP threshold level , */\
{ 0xb108, "ext_temp"}, /* External temperature (C) , */\
{ 0xb190, "ext_temp_sel"}, /* Select temp Speaker calibration , */\
{ 0xc000, "use_direct_ctrls"}, /* Direct control to overrule several functions for testing, */\
{ 0xc010, "rst_datapath"}, /* Direct control for datapath reset , */\
{ 0xc020, "rst_cgu"}, /* Direct control for cgu reset , */\
{ 0xc038, "enbl_ref"}, /* Switch on the analog references, each part of the references can be switched on/off individually, */\
{ 0xc0c0, "use_direct_vs_ctrls"}, /* voltage sense Direct control to overrule several functions for testing, */\
{ 0xc0d0, "enbl_ringo"}, /* Enable the ring oscillator for test purpose , */\
{ 0xc0e0, "enbl_pll"}, /* Enables PLL in I2C direct control mode only , */\
{ 0xc0f0, "enbl_fro"}, /* Enables FRO8M in I2C direct control mode only , */\
{ 0xc100, "enbl_tsense"}, /* Temperature sensor enable control - I2C direct mode, */\
{ 0xc110, "tsense_hibias"}, /* Bit to set the biasing in temp sensor to high , */\
{ 0xc120, "enbl_flag_vbg"}, /* Enable flagging of bandgap out of control , */\
{ 0xc20f, "abist_offset"}, /* Offset control for ABIST testing (two's complement), */\
{ 0xc300, "bypasslatch"}, /* Bypass latch , */\
{ 0xc311, "sourcea"}, /* Set OUTA to , */\
{ 0xc331, "sourceb"}, /* Set OUTB to , */\
{ 0xc350, "inverta"}, /* Invert pwma test signal , */\
{ 0xc360, "invertb"}, /* Invert pwmb test signal , */\
{ 0xc374, "pulselength"}, /* Pulse length setting test input for amplifier (clock d - k*2048*fs ), */\
{ 0xc3c0, "tdm_enable_loopback"}, /* TDM loopback test , */\
{ 0xc400, "bst_bypasslatch"}, /* Bypass latch in boost converter , */\
{ 0xc411, "bst_source"}, /* Sets the source of the pwmbst output to boost converter input for testing, */\
{ 0xc430, "bst_invertb"}, /* Invert pwmbst test signal , */\
{ 0xc444, "bst_pulselength"}, /* Pulse length setting test input for boost converter , */\
{ 0xc490, "test_bst_ctrlsthv"}, /* Test mode for boost control stage , */\
{ 0xc4a0, "test_bst_iddq"}, /* IDDQ testing in power stage of boost converter , */\
{ 0xc4b0, "test_bst_rdson"}, /* RDSON testing - boost power stage , */\
{ 0xc4c0, "test_bst_cvi"}, /* CVI testing - boost power stage , */\
{ 0xc4d0, "test_bst_ocp"}, /* Boost OCP. For old ocp (ctrl_reversebst is 0), For new ocp (ctrl_reversebst is 1), */\
{ 0xc4e0, "test_bst_sense"}, /* Test option for the sense NMOS in booster for current mode control., */\
{ 0xc500, "test_cvi"}, /* Analog BIST, switch choose which transistor will be used as current source (also cross coupled sources possible), */\
{ 0xc510, "test_discrete"}, /* Test function noise measurement , */\
{ 0xc520, "test_iddq"}, /* Set the power stages in iddq mode for gate stress., */\
{ 0xc540, "test_rdson"}, /* Analog BIST, switch to enable Rdson measurement , */\
{ 0xc550, "test_sdelta"}, /* Analog BIST, noise test , */\
{ 0xc570, "test_enbl_cs"}, /* Enable for digimux mode of current sense , */\
{ 0xc580, "test_enbl_vs"}, /* Enable for digimux mode of voltage sense , */\
{ 0xc600, "enbl_pwm_dcc"}, /* Enables direct control of pwm duty cycle for DCDC power stage, */\
{ 0xc613, "pwm_dcc_cnt"}, /* Control pwm duty cycle when enbl_pwm_dcc is 1 , */\
{ 0xc650, "enbl_ldo_stress"}, /* Enable stress of internal supply voltages powerstages, */\
{ 0xc707, "digimuxa_sel"}, /* DigimuxA input selection control routed to DATAO (see Digimux list for details), */\
{ 0xc787, "digimuxb_sel"}, /* DigimuxB input selection control routed to INT (see Digimux list for details), */\
{ 0xc807, "digimuxc_sel"}, /* DigimuxC input selection control routed to ADS1 (see Digimux list for details), */\
{ 0xc981, "int_ehs"}, /* Speed/load setting for INT IO cell, clk or data mode range (see SLIMMF IO cell datasheet), */\
{ 0xc9c0, "hs_mode"}, /* I2C high speed mode control , */\
{ 0xc9d1, "sw_hs_mode"}, /* Speed/load setting for SW IO cell, clk or data mode range (see SWMF IO cell datasheet), */\
{ 0xca00, "enbl_anamux1"}, /* Enable anamux1 , */\
{ 0xca10, "enbl_anamux2"}, /* Enable anamux2 , */\
{ 0xca20, "enbl_anamux3"}, /* Enable anamux3 , */\
{ 0xca30, "enbl_anamux4"}, /* Enable anamux4 , */\
{ 0xca74, "anamux1"}, /* Anamux selection control - anamux on TEST1 , */\
{ 0xcac0, "open_frcbst_ensw_switch"}, /* Save test2 configuration before enable anamux2 (open test2 switch and save test2 setting) , */\
{ 0xcb04, "anamux2"}, /* Anamux selection control - anamux on FRCBST/TEST2 , */\
{ 0xcb53, "anamux3"}, /* Anamux selection control - anamux on VSN/TEST3 , */\
{ 0xcba3, "anamux4"}, /* Anamux selection control - anamux on VSP/TEST4 , */\
{ 0xcd05, "pll_inseli"}, /* PLL INSELI - PLL direct bandwidth control mode only with pll_bandsel set to 1, */\
{ 0xcd64, "pll_inselp"}, /* PLL INSELP - PLL direct bandwidth control mode only with pll_bandsel set to 1, */\
{ 0xcdb3, "pll_inselr"}, /* PLL INSELR - PLL direct bandwidth control mode only with pll_bandsel set to 1, */\
{ 0xcdf0, "pll_bandsel"}, /* PLL bandwidth selection control, USE WITH CAUTION , */\
{ 0xce09, "pll_ndec"}, /* PLL NDEC in direct control mode only, use_direct_pll_ctrl set to 1, */\
{ 0xcea0, "pll_mdec_msb"}, /* MSB of PLL MDEC in direct control mode only, use_direct_pll_ctrl set to 1, */\
{ 0xceb0, "pll_bypass"}, /* PLL bypass control during functional mode , */\
{ 0xcec0, "pll_directi"}, /* PLL directi control in direct control mode only, use_direct_pll_ctrl set to 1, */\
{ 0xced0, "pll_directo"}, /* PLL directo control in direct control mode only, use_direct_pll_ctrl set to 1, */\
{ 0xcee0, "pll_frm_clockstable"}, /* PLL FRM clock stable control in direct control mode only, use_direct_pll_ctrl set to 1, */\
{ 0xcef0, "pll_frm"}, /* PLL free running mode control in functional mode , */\
{ 0xcf0f, "pll_mdec_lsb"}, /* Bits 15..0 of PLL MDEC in direct control mode only, use_direct_pll_ctrl set to 1, */\
{ 0xd006, "pll_pdec"}, /* PLL PDEC in direct control mode only, use_direct_pll_ctrl set to 1, */\
{ 0xd070, "use_direct_pll_ctrl"}, /* Enabled PLL direct control mode, overrules the PLL LUT with I2C register values, */\
{ 0xd090, "pll_limup_off"}, /* PLL up limiter control in PLL direct bandwidth control mode, pll_bandsel set to 1, */\
{ 0xd0a2, "sel_pll_startup_time"}, /* PLL startup time selection control , */\
{ 0xd10f, "tsig_freq_lsb"}, /* Internal sinus test generator frequency control , */\
{ 0xd202, "tsig_freq_msb"}, /* Select internal sinus test generator, frequency control msb bits, */\
{ 0xd230, "inject_tsig"}, /* Control bit to switch to internal sinus test generator, */\
{ 0xd283, "tsig_gain"}, /* Test signal gain , */\
{ 0xd300, "adc10_reset"}, /* Reset for ADC10 - I2C direct control mode , */\
{ 0xd311, "adc10_test"}, /* Test mode selection signal for ADC10 - I2C direct control mode, */\
{ 0xd332, "adc10_sel"}, /* Select the input to convert for ADC10 - I2C direct control mode, */\
{ 0xd364, "adc10_prog_sample"}, /* ADC10 program sample setting - I2C direct control mode, */\
{ 0xd3b0, "adc10_enbl"}, /* Enable ADC10 - I2C direct control mode , */\
{ 0xd3c0, "bypass_lp_vbat"}, /* Bypass control for Low pass filter in batt sensor , */\
{ 0xd409, "data_adc10_tempbat"}, /* ADC 10 data output data for testing , */\
{ 0xd507, "ctrl_digtoana_hidden"}, /* Spare digital to analog control bits - Hidden , */\
{ 0xd580, "enbl_clk_out_of_range"}, /* Clock out of range , */\
{ 0xd721, "datao_ehs"}, /* Speed/load setting for DATAO IO cell, clk or data mode range (see SLIMMF IO cell datasheet), */\
{ 0xd740, "bck_ehs"}, /* High-speed and standard/fast mode selection for BCK IO cell (see IIC3V3 IO cell datasheet), */\
{ 0xd750, "datai_ehs"}, /* High-speed and standard/fast mode selection for DATAI IO cell (see IIC3V3 IO cell datasheet), */\
{ 0xd800, "source_in_testmode"}, /* tdm source in test mode (return only current and voltage sense), */\
{ 0xd810, "gainatt_tdm_feedback"}, /* gainatt feedback to tdm , */\
{ 0xd822, "test_parametric_io"}, /* test io parametric , */\
{ 0xd850, "ctrl_bst_clk_lp1"}, /* boost clock control in low power mode1 , */\
{ 0xd861, "test_spare_out1"}, /* test spare out 1 , */\
{ 0xd880, "bst_dcmbst"}, /* dcm boost , */\
{ 0xd890, "gainatt_sw_feedback"}, /* gainatt feedback to sw , */\
{ 0xd8c3, "test_spare_out2"}, /* test spare out 1 , */\
{ 0xd900, "enbl_frocal"}, /* Enable FRO calibration , */\
{ 0xd910, "start_fro_calibration"}, /* Start FRO8 Calibration , */\
{ 0xd920, "enbl_irefcal"}, /* Enable IREF calibration , */\
{ 0xd930, "start_iref_calibration"}, /* Start IREF Calibration , */\
{ 0xda00, "fro_calibration_done"}, /* FRO8 Calibration done - Read Only , */\
{ 0xda15, "fro_auto_trim_val"}, /* Calibration value from Auto Calibration block, to be written into MTP - Read Only, */\
{ 0xda80, "iref_calibration_done"}, /* IREF Calibration done - Read Only , */\
{ 0xda94, "iref_auto_trim_val"}, /* Calibration value from Auto Calibration block, to be written into MTP - Read Only, */\
{ 0xdae0, "iref_calibration_error"}, /* IREF Calibration done - Read Only , */\
{ 0xe00f, "sw_profile"}, /* Software profile data , */\
{ 0xe10f, "sw_vstep"}, /* Software vstep information , */\
{ 0xf000, "calibration_onetime"}, /* Calibration schedule , */\
{ 0xf010, "calibr_ron_done"}, /* Calibration Ron executed , */\
{ 0xf020, "calibr_dcdc_api_calibrate"}, /* Calibration current limit DCDC , */\
{ 0xf030, "calibr_dcdc_delta_sign"}, /* Sign bit for delta calibration current limit DCDC , */\
{ 0xf042, "calibr_dcdc_delta"}, /* Calibration delta current limit DCDC , */\
{ 0xf078, "calibr_speaker_info"}, /* Reserved space for allowing customer to store speaker information, */\
{ 0xf105, "calibr_vout_offset"}, /* DCDC offset calibration 2's complement (key1 protected), */\
{ 0xf169, "spare_mtp1_15_6"}, /* SPARE , */\
{ 0xf203, "calibr_gain"}, /* HW gain module (2's complement) , */\
{ 0xf245, "calibr_offset"}, /* Offset for amplifier, HW gain module (2's complement), */\
{ 0xf2a4, "optimal_pwm_delay"}, /* PWM delay bits to set the delay, clockd is 1/(k*2048*fs), */\
{ 0xf2f0, "enbl_optimal_pwm_delay"}, /* optimized pwm delay function enabled , */\
{ 0xf307, "calibr_gain_vs1"}, /* Voltage sense gain when external voltage sensing input is selected, */\
{ 0xf387, "calibr_gain_vs2"}, /* Voltage sense gain when internal voltage sensing input is selected, */\
{ 0xf407, "vs_trim1"}, /* VS Trimming when external voltage sensing input is selected, */\
{ 0xf487, "vs_trim2"}, /* VS Trimming when internal voltage sensing input is selected, */\
{ 0xf50f, "calibr_R25C_R"}, /* Ron resistance of speaker coil , */\
{ 0xf607, "calibr_gain_cs"}, /* Current sense gain (signed two's complement format), */\
{ 0xf687, "spare_mpt6_15_06"}, /* SPARE , */\
{ 0xf706, "ctrl_offset_a"}, /* Offset of level shifter A , */\
{ 0xf770, "spare_mtp7_07"}, /* SPARE , */\
{ 0xf786, "ctrl_offset_b"}, /* Offset of amplifier level shifter B , */\
{ 0xf7f0, "spare_mtp7_15"}, /* SPARE , */\
{ 0xf806, "htol_iic_addr"}, /* 7-bit I2C address to be used during HTOL testing , */\
{ 0xf870, "htol_iic_addr_en"}, /* HTOL I2C address enable control , */\
{ 0xf884, "calibr_temp_offset"}, /* Temperature offset 2's compliment (key1 protected), */\
{ 0xf8d2, "calibr_temp_gain"}, /* Temperature gain 2's compliment (key1 protected) , */\
{ 0xf900, "mtp_lock_dcdcoff_mode"}, /* Disable function dcdcoff_mode , */\
{ 0xf910, "spare_mtp9_1"}, /* SPARE , */\
{ 0xf920, "mtp_lock_bypass_clipper"}, /* Disable function bypass_clipper , */\
{ 0xf930, "mtp_lock_max_dcdc_voltage"}, /* Force Boost in follower mode , */\
{ 0xf943, "calibr_vbg_trim"}, /* Bandgap trimming control , */\
{ 0xf980, "spare_mtp9_8"}, /* SPARE , */\
{ 0xf990, "mtp_enbl_pwm_delay_clock_gating"}, /* pwm delay clock auto gating , */\
{ 0xf9a0, "mtp_enbl_ocp_clock_gating"}, /* ocpclock auto gating , */\
{ 0xf9b0, "mtp_gate_cgu_clock_for_test"}, /* cgu test clock control , */\
{ 0xf9c0, "mtp_tdm_pad_sel"}, /* tdm pad selection , */\
{ 0xf9d2, "spare_mtp9_15_12"}, /* MTP-control FW - See Firmware I2C API document for details, */\
{ 0xfa0f, "mtpdataA"}, /* MTPdataA (key1 protected) , */\
{ 0xfb0f, "mtpdataB"}, /* MTPdataB (key1 protected) , */\
{ 0xfc0f, "mtpdataC"}, /* MTPdataC (key1 protected) , */\
{ 0xfd0f, "mtpdataD"}, /* MTPdataD (key1 protected) , */\
{ 0xfe0f, "mtpdataE"}, /* MTPdataE (key1 protected) , */\
{ 0xff05, "fro_trim"}, /* 8 MHz oscillator trim code , */\
{ 0xff61, "fro_shortnwell"}, /* Short 4 or 6 n-well resistors , */\
{ 0xff81, "fro_boost"}, /* Self bias current selection , */\
{ 0xffa4, "calibr_iref_trim"}, /* Trimming control of reference current for OCP , */\
{ 0xffff,"Unknown bitfield enum" } /* not found */\
};
enum tfa9878_irq {
tfa9878_irq_stvdds = 0,
tfa9878_irq_stbstoc = 1,
tfa9878_irq_stotds = 2,
tfa9878_irq_stocpr = 3,
tfa9878_irq_stuvds = 4,
tfa9878_irq_stmanalarm = 5,
tfa9878_irq_sttdmer = 6,
tfa9878_irq_stnoclk = 7,
tfa9878_irq_stbodnok = 8,
tfa9878_irq_max = 9,
tfa9878_irq_all = -1 /* all irqs */};
#define TFA9878_IRQ_NAMETABLE static tfaIrqName_t Tfa9878IrqNames[]= {\
{ 0, "STVDDS"},\
{ 1, "STBSTOC"},\
{ 2, "STOTDS"},\
{ 3, "STOCPR"},\
{ 4, "STUVDS"},\
{ 5, "STMANALARM"},\
{ 6, "STTDMER"},\
{ 7, "STNOCLK"},\
{ 8, "STBODNOK"},\
{ 9, "9"},\
};
#endif /* _TFA9878_TFAFIELDNAMES_H */

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/*
* Copyright (C) 2014-2020 NXP Semiconductors, All Rights Reserved.
* Copyright 2020 GOODIX
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
*/
/** Filename: Tfa9887_TfaFieldnames.h
* This file was generated automatically on 04/14/15 at 10:23:40.
* Source file: TFA9897N1B_I2C_list_URT_source_v34_87Only.xls
*/
#define TFA9887_I2CVERSION 34
#define TFA9895_I2CVERSION 34
#define TFA9887_NAMETABLE static tfaBfName_t Tfa9887DatasheetNames[]= {\
{ 0x402, "I2SF"}, /* I2SFormat data 1 input: , */\
{ 0x431, "CHS12"}, /* ChannelSelection data1 input (In CoolFlux) , */\
{ 0x450, "CHS3"}, /* ChannelSelection data 2 input (coolflux input, the DCDC converter gets the other signal), */\
{ 0x461, "CHSA"}, /* Input selection for amplifier , */\
{ 0x4b0, "I2SDOE"}, /* Enable data output , */\
{ 0x4c3, "I2SSR"}, /* sample rate setting , */\
{ 0x500, "BSSBY"}, /* , */\
{ 0x511, "BSSCR"}, /* 00 = 0.56 dB/Sample , */\
{ 0x532, "BSST"}, /* 000 = 2.92V , */\
{ 0x5f0, "I2SDOC"}, /* selection data out , */\
{ 0xa02, "DOLS"}, /* Output selection dataout left channel , */\
{ 0xa32, "DORS"}, /* Output selection dataout right channel , */\
{ 0xa62, "SPKL"}, /* Selection speaker induction , */\
{ 0xa91, "SPKR"}, /* Selection speaker impedance , */\
{ 0xab3, "DCFG"}, /* DCDC speaker current compensation gain , */\
{ 0x4134, "PWMDEL"}, /* PWM DelayBits to set the delay , */\
{ 0x4180, "PWMSH"}, /* PWM Shape , */\
{ 0x4190, "PWMRE"}, /* PWM Bitlength in noise shaper , */\
{ 0x48e1, "TCC"}, /* sample & hold track time: , */\
{ 0xffff,"Unknown bitfield enum" } /* not found */\
};
#define TFA9887_BITNAMETABLE static tfaBfName_t Tfa9887BitNames[]= {\
{ 0x402, "i2s_seti"}, /* I2SFormat data 1 input: , */\
{ 0x431, "chan_sel1"}, /* ChannelSelection data1 input (In CoolFlux) , */\
{ 0x450, "lr_sw_i2si2"}, /* ChannelSelection data 2 input (coolflux input, the DCDC converter gets the other signal), */\
{ 0x461, "input_sel"}, /* Input selection for amplifier , */\
{ 0x4b0, "enbl_datao"}, /* Enable data output , */\
{ 0x4c3, "i2s_fs"}, /* sample rate setting , */\
{ 0x500, "bypass_clipper"}, /* , */\
{ 0x511, "vbat_prot_attacktime[1:0]"}, /* 00 = 0.56 dB/Sample , */\
{ 0x532, "vbat_prot_thlevel[2:0]"}, /* 000 = 2.92V , */\
{ 0x5d0, "reset_min_vbat"}, /* to reset the clipper via I2C in case the CF is bypassed, */\
{ 0x5f0, "datao_sel"}, /* selection data out , */\
{ 0xa02, "sel_i2so_l"}, /* Output selection dataout left channel , */\
{ 0xa32, "sel_i2so_r"}, /* Output selection dataout right channel , */\
{ 0xa62, "ctrl_spkr_coil"}, /* Selection speaker induction , */\
{ 0xa91, "ctrl_spr_res"}, /* Selection speaker impedance , */\
{ 0xab3, "ctrl_dcdc_spkr_i_comp_gain"}, /* DCDC speaker current compensation gain , */\
{ 0xaf0, "ctrl_dcdc_spkr_i_comp_sign"}, /* DCDC speaker current compensation sign , */\
{ 0x4100, "bypass_hp"}, /* bypass_hp, to bypass the hp filter byhind the CoolFlux, */\
{ 0x4110, "hard_mute"}, /* hard mute setting in HW , */\
{ 0x4120, "soft_mute"}, /* Soft mute setting in HW , */\
{ 0x4134, "PWM_Delay[4:0]"}, /* PWM DelayBits to set the delay , */\
{ 0x4180, "PWM_Shape"}, /* PWM Shape , */\
{ 0x4190, "PWM_BitLength"}, /* PWM Bitlength in noise shaper , */\
{ 0x4800, "ctrl_negin"}, /* , */\
{ 0x4810, "ctrl_cs_sein"}, /* , */\
{ 0x4820, "ctrl_coincidencecs"}, /* HIGH => Prevent dcdc switching during clk_cs_clksh, */\
{ 0x4876, "delay_se_neg[6:0]"}, /* delayshiftse2 , */\
{ 0x48e1, "ctrl_cs_ttrack[1:0]"}, /* sample & hold track time: , */\
{ 0xffff,"Unknown bitfield enum" } /* not found */\
};

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techpack/audio/asoc/codecs/tfa98xx/inc/tfa9890_tfafieldnames.h Executable file
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/*
* Copyright (C) 2014-2020 NXP Semiconductors, All Rights Reserved.
* Copyright 2020 GOODIX
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
*/
/** Filename: Tfa9890_TfaFieldnames.h
* This file was generated automatically on 04/07/15 at 14:46:37.
* Source file: TFA9897N1B_I2C_list_URT_source_v34_90Only.xls
*/
#define TFA9890_I2CVERSION 34
#define TFA9890_NAMETABLE static tfaBfName_t Tfa9890DatasheetNames[]= {\
{ 0x402, "I2SF"}, /* I2SFormat data 1 input: , */\
{ 0x431, "CHS12"}, /* ChannelSelection data1 input (In CoolFlux) , */\
{ 0x450, "CHS3"}, /* ChannelSelection data 2 input (coolflux input, the DCDC converter gets the other signal), */\
{ 0x461, "CHSA"}, /* Input selection for amplifier , */\
{ 0x481, "I2SDOC"}, /* selection data out , */\
{ 0x4a0, "DISP"}, /* idp protection , */\
{ 0x4b0, "I2SDOE"}, /* Enable data output , */\
{ 0x4c3, "I2SSR"}, /* sample rate setting , */\
{ 0x732, "DCMCC"}, /* Max boost coil current - step of 500 mA , */\
{ 0x9c0, "CCFD"}, /* Selection CoolFlux Clock , */\
{ 0x9d0, "ISEL"}, /* selection input 1 or 2 , */\
{ 0xa02, "DOLS"}, /* Output selection dataout left channel , */\
{ 0xa32, "DORS"}, /* Output selection dataout right channel , */\
{ 0xa62, "SPKL"}, /* Selection speaker induction , */\
{ 0xa91, "SPKR"}, /* Selection speaker impedance , */\
{ 0xab3, "DCFG"}, /* DCDC speaker current compensation gain , */\
{ 0xf00, "VDDD"}, /* mask flag_por for interupt generation , */\
{ 0xf10, "OTDD"}, /* mask flag_otpok for interupt generation , */\
{ 0xf20, "OVDD"}, /* mask flag_ovpok for interupt generation , */\
{ 0xf30, "UVDD"}, /* mask flag_uvpok for interupt generation , */\
{ 0xf40, "OCDD"}, /* mask flag_ocp_alarm for interupt generation , */\
{ 0xf50, "CLKD"}, /* mask flag_clocks_stable for interupt generation , */\
{ 0xf60, "DCCD"}, /* mask flag_pwrokbst for interupt generation , */\
{ 0xf70, "SPKD"}, /* mask flag_cf_speakererror for interupt generation , */\
{ 0xf80, "WDD"}, /* mask flag_watchdog_reset for interupt generation , */\
{ 0xf90, "LCLK"}, /* mask flag_lost_clk for interupt generation , */\
{ 0xfe0, "INT"}, /* enabling interrupt , */\
{ 0xff0, "INTP"}, /* Setting polarity interupt , */\
{ 0x8f0f, "VERSION"}, /* (key1 protected) , */\
{ 0xffff,"Unknown bitfield enum" } /* not found */\
};
#define TFA9890_BITNAMETABLE static tfaBfName_t Tfa9890BitNames[]= {\
{ 0x402, "i2s_seti"}, /* I2SFormat data 1 input: , */\
{ 0x431, "chan_sel1"}, /* ChannelSelection data1 input (In CoolFlux) , */\
{ 0x450, "lr_sw_i2si2"}, /* ChannelSelection data 2 input (coolflux input, the DCDC converter gets the other signal), */\
{ 0x461, "input_sel"}, /* Input selection for amplifier , */\
{ 0x481, "datao_sel"}, /* selection data out , */\
{ 0x4a0, "disable_idp"}, /* idp protection , */\
{ 0x4b0, "enbl_datao"}, /* Enable data output , */\
{ 0x4c3, "i2s_fs"}, /* sample rate setting , */\
{ 0x732, "ctrl_bstcur"}, /* Max boost coil current - step of 500 mA , */\
{ 0x9c0, "sel_cf_clk"}, /* Selection CoolFlux Clock , */\
{ 0x9d0, "intf_sel"}, /* selection input 1 or 2 , */\
{ 0xa02, "sel_i2so_l"}, /* Output selection dataout left channel , */\
{ 0xa32, "sel_i2so_r"}, /* Output selection dataout right channel , */\
{ 0xa62, "ctrl_spkr_coil"}, /* Selection speaker induction , */\
{ 0xa91, "ctrl_spr_res"}, /* Selection speaker impedance , */\
{ 0xab3, "ctrl_dcdc_spkr_i_comp_gain"}, /* DCDC speaker current compensation gain , */\
{ 0xaf0, "ctrl_dcdc_spkr_i_comp_sign"}, /* DCDC speaker current compensation sign , */\
{ 0xf00, "flag_por_mask"}, /* mask flag_por for interupt generation , */\
{ 0xf10, "flag_otpok_mask"}, /* mask flag_otpok for interupt generation , */\
{ 0xf20, "flag_ovpok_mask"}, /* mask flag_ovpok for interupt generation , */\
{ 0xf30, "flag_uvpok_mask"}, /* mask flag_uvpok for interupt generation , */\
{ 0xf40, "flag_ocp_alarm_mask"}, /* mask flag_ocp_alarm for interupt generation , */\
{ 0xf50, "flag_clocks_stable_mask"}, /* mask flag_clocks_stable for interupt generation , */\
{ 0xf60, "flag_pwrokbst_mask"}, /* mask flag_pwrokbst for interupt generation , */\
{ 0xf70, "flag_cf_speakererror_mask"}, /* mask flag_cf_speakererror for interupt generation , */\
{ 0xf80, "flag_watchdog_reset_mask"}, /* mask flag_watchdog_reset for interupt generation , */\
{ 0xf90, "flag_lost_clk_mask"}, /* mask flag_lost_clk for interupt generation , */\
{ 0xfe0, "enable_interrupt"}, /* enabling interrupt , */\
{ 0xff0, "invert_int_polarity"}, /* Setting polarity interupt , */\
{ 0x4700, "switch_fb"}, /* switch_fb , */\
{ 0x4713, "se_hyst"}, /* se_hyst , */\
{ 0x4754, "se_level"}, /* se_level , */\
{ 0x47a5, "ktemp"}, /* temperature compensation trimming , */\
{ 0x8f0f, "production_data6"}, /* (key1 protected) , */\
{ 0xffff,"Unknown bitfield enum" } /* not found */\
};

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techpack/audio/asoc/codecs/tfa98xx/inc/tfa9891_tfafieldnames.h Executable file
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/*
* Copyright (C) 2014-2020 NXP Semiconductors, All Rights Reserved.
* Copyright 2020 GOODIX
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
*/
/*
* tfa9891_tfafieldnames.h
*
* Created on: Jul 16, 2015
* Author: wim
*/
#ifndef TFA_INC_TFA9891_TFAFIELDNAMES_H_
#define TFA_INC_TFA9891_TFAFIELDNAMES_H_
/** Filename: Tfa9891_TfaFieldnames.h
* This file was generated automatically on 07/16/15 at 15:00:02.
* Source file: TFA9891_I2C_list_V13.xls
*/
#define TFA9891_I2CVERSION 13
#define TFA9891_NAMETABLE static tfaBfName_t Tfa9891DatasheetNames[]= {\
{ 0x0, "VDDS"}, /* POR , */\
{ 0x10, "PLLS"}, /* PLL , */\
{ 0x20, "OTDS"}, /* OTP , */\
{ 0x30, "OVDS"}, /* OVP , */\
{ 0x40, "UVDS"}, /* UVP , */\
{ 0x50, "OCDS"}, /* OCP , */\
{ 0x60, "CLKS"}, /* Clocks , */\
{ 0x70, "CLIPS"}, /* CLIP , */\
{ 0x80, "MTPB"}, /* MTP , */\
{ 0x90, "DCCS"}, /* BOOST , */\
{ 0xa0, "SPKS"}, /* Speaker , */\
{ 0xb0, "ACS"}, /* cold start flag , */\
{ 0xc0, "SWS"}, /* flag engage , */\
{ 0xd0, "WDS"}, /* flag watchdog reset , */\
{ 0xe0, "AMPS"}, /* amplifier is enabled by manager , */\
{ 0xf0, "AREFS"}, /* references are enabled by manager , */\
{ 0x109, "BATS"}, /* Battery voltage readout; 0[V]..5.5[V] , */\
{ 0x208, "TEMPS"}, /* Temperature readout , */\
{ 0x307, "REV"}, /* Device Revision , */\
{ 0x402, "I2SF"}, /* I2SFormat data 1 input , */\
{ 0x431, "CHS12"}, /* ChannelSelection data1 input (In CoolFlux) , */\
{ 0x450, "CHS3"}, /* Channel Selection data 2 input (coolflux input, the DCDC converter gets the other signal), */\
{ 0x461, "CHSA"}, /* Input selection for amplifier , */\
{ 0x481, "I2SDOC"}, /* Selection for I2S data out , */\
{ 0x4a0, "DISP"}, /* idp protection , */\
{ 0x4b0, "I2SDOE"}, /* Enable data output , */\
{ 0x4c3, "I2SSR"}, /* sample rate setting , */\
{ 0x501, "BSSCR"}, /* ProtectionAttackTime , */\
{ 0x523, "BSST"}, /* ProtectionThreshold , */\
{ 0x561, "BSSRL"}, /* ProtectionMaximumReduction , */\
{ 0x582, "BSSRR"}, /* Protection Release Timer , */\
{ 0x5b1, "BSSHY"}, /* ProtectionHysterese , */\
{ 0x5e0, "BSSR"}, /* battery voltage for I2C read out only , */\
{ 0x5f0, "BSSBY"}, /* bypass clipper battery protection , */\
{ 0x600, "DPSA"}, /* Enable dynamic powerstage activation , */\
{ 0x613, "AMPSL"}, /* control slope , */\
{ 0x650, "CFSM"}, /* Soft mute in CoolFlux , */\
{ 0x670, "BSSS"}, /* batsensesteepness , */\
{ 0x687, "VOL"}, /* volume control (in CoolFlux) , */\
{ 0x702, "DCVO"}, /* Boost voltage , */\
{ 0x732, "DCMCC"}, /* Max boost coil current , */\
{ 0x7a0, "DCIE"}, /* Adaptive boost mode , */\
{ 0x7b0, "DCSR"}, /* Soft RampUp/Down mode for DCDC controller , */\
{ 0x800, "TROS"}, /* select external temperature also the ext_temp will be put on the temp read out , */\
{ 0x818, "EXTTS"}, /* external temperature setting to be given by host , */\
{ 0x900, "PWDN"}, /* ON/OFF , */\
{ 0x910, "I2CR"}, /* I2CReset , */\
{ 0x920, "CFE"}, /* EnableCoolFlux , */\
{ 0x930, "AMPE"}, /* EnableAmplifier , */\
{ 0x940, "DCA"}, /* EnableBoost , */\
{ 0x950, "SBSL"}, /* Coolflux configured , */\
{ 0x960, "AMPC"}, /* Selection on how AmplifierEnabling , */\
{ 0x970, "DCDIS"}, /* DCDC not connected , */\
{ 0x980, "PSDR"}, /* Iddq test amplifier , */\
{ 0x991, "DCCV"}, /* Coil Value , */\
{ 0x9b1, "CCFD"}, /* Selection CoolFluxClock , */\
{ 0x9d0, "ISEL"}, /* Interface Selection , */\
{ 0x9e0, "IPLL"}, /* selection input PLL for lock , */\
{ 0xa02, "DOLS"}, /* Output selection dataout left channel , */\
{ 0xa32, "DORS"}, /* Output selection dataout right channel , */\
{ 0xa62, "SPKL"}, /* Selection speaker induction , */\
{ 0xa91, "SPKR"}, /* Selection speaker impedance , */\
{ 0xab3, "DCFG"}, /* DCDC speaker current compensation gain , */\
{ 0xb07, "MTPK"}, /* MTP KEY2 register , */\
{ 0xf00, "VDDD"}, /* mask flag_por for interupt generation , */\
{ 0xf10, "OTDD"}, /* mask flag_otpok for interupt generation , */\
{ 0xf20, "OVDD"}, /* mask flag_ovpok for interupt generation , */\
{ 0xf30, "UVDD"}, /* mask flag_uvpok for interupt generation , */\
{ 0xf40, "OCDD"}, /* mask flag_ocp_alarm for interupt generation , */\
{ 0xf50, "CLKD"}, /* mask flag_clocks_stable for interupt generation , */\
{ 0xf60, "DCCD"}, /* mask flag_pwrokbst for interupt generation , */\
{ 0xf70, "SPKD"}, /* mask flag_cf_speakererror for interupt generation , */\
{ 0xf80, "WDD"}, /* mask flag_watchdog_reset for interupt generation , */\
{ 0xfe0, "INT"}, /* enabling interrupt , */\
{ 0xff0, "INTP"}, /* Setting polarity interupt , */\
{ 0x1000, "PDMSEL"}, /* Audio input interface mode , */\
{ 0x1010, "I2SMOUTEN"}, /* I2S Master enable (CLK and WS pads) , */\
{ 0x1021, "PDMORSEL"}, /* PDM Output right channel source selection , */\
{ 0x1041, "PDMOLSEL"}, /* PDM Output Left/Mono channel source selection , */\
{ 0x1061, "PADSEL"}, /* Output interface mode and ball selection , */\
{ 0x1100, "PDMOSDEN"}, /* Secure delay Cell , */\
{ 0x1110, "PDMOSDCF"}, /* Rising Falling Resync control Mux , */\
{ 0x1140, "SAAMEN"}, /* Speaker As a Mic feature ON/OFF , */\
{ 0x1150, "SAAMLPEN"}, /* speaker_as_mic low power mode (only in PDM_out mode), */\
{ 0x1160, "PDMOINTEN"}, /* PDM output interpolation ratio , */\
{ 0x1203, "PDMORG1"}, /* PDM Interpolator Right Channel DS4 G1 Gain Value , */\
{ 0x1243, "PDMORG2"}, /* PDM Interpolator Right Channel DS4 G2 Gain Value , */\
{ 0x1303, "PDMOLG1"}, /* PDM Interpolator Left Channel DS4 G1 Gain Value , */\
{ 0x1343, "PDMOLG2"}, /* PDM Interpolator Left Channel DS4 G2 Gain Value , */\
{ 0x2202, "SAAMGAIN"}, /* pga gain , */\
{ 0x2250, "SAAMPGACTRL"}, /* 0 = active input common mode voltage source at the attenuator/PGA level, */\
{ 0x2500, "PLLCCOSEL"}, /* pll cco frequency , */\
{ 0x4600, "CSBYPGC"}, /* bypass_gc, bypasses the CS gain correction , */\
{ 0x4900, "CLIP"}, /* Bypass clip control (function depending on digimux clip_x), */\
{ 0x4910, "CLIP2"}, /* Bypass clip control (function depending on digimux clip_x), */\
{ 0x62b0, "CIMTP"}, /* start copying all the data from i2cregs_mtp to mtp [Key 2 protected], */\
{ 0x7000, "RST"}, /* Reset CoolFlux DSP , */\
{ 0x7011, "DMEM"}, /* Target memory for access , */\
{ 0x7030, "AIF"}, /* Autoincrement-flag for memory-address , */\
{ 0x7040, "CFINT"}, /* Interrupt CoolFlux DSP , */\
{ 0x7087, "REQ"}, /* request for access (8 channels) , */\
{ 0x710f, "MADD"}, /* memory-address to be accessed , */\
{ 0x720f, "MEMA"}, /* activate memory access (24- or 32-bits data is written/read to/from memory, */\
{ 0x7307, "ERR"}, /* cf error Flags , */\
{ 0x7387, "ACK"}, /* acknowledge of requests (8 channels")" , */\
{ 0x8000, "MTPOTC"}, /* Calibration schedule (key2 protected) , */\
{ 0x8010, "MTPEX"}, /* (key2 protected) calibration of Ron has been executed, */\
{ 0x8045, "SWPROFIL" },\
{ 0x80a5, "SWVSTEP" },\
{ 0xffff,"Unknown bitfield enum" } /* not found */\
};
#define TFA9891_BITNAMETABLE static tfaBfName_t Tfa9891BitNames[]= {\
{ 0x0, "POR"}, /* POR , */\
{ 0x10, "PLL_LOCK"}, /* PLL , */\
{ 0x20, "flag_otpok"}, /* OTP , */\
{ 0x30, "flag_ovpok"}, /* OVP , */\
{ 0x40, "flag_uvpok"}, /* UVP , */\
{ 0x50, "flag_OCP_alarm"}, /* OCP , */\
{ 0x60, "flag_clocks_stable"}, /* Clocks , */\
{ 0x70, "CLIP"}, /* CLIP , */\
{ 0x80, "mtp_busy"}, /* MTP , */\
{ 0x90, "flag_pwrokbst"}, /* BOOST , */\
{ 0xa0, "flag_cf_speakererror"}, /* Speaker , */\
{ 0xb0, "flag_cold_started"}, /* cold start flag , */\
{ 0xc0, "flag_engage"}, /* flag engage , */\
{ 0xd0, "flag_watchdog_reset"}, /* flag watchdog reset , */\
{ 0xe0, "flag_enbl_amp"}, /* amplifier is enabled by manager , */\
{ 0xf0, "flag_enbl_ref"}, /* references are enabled by manager , */\
{ 0x109, "bat_adc"}, /* Battery voltage readout; 0[V]..5.5[V] , */\
{ 0x208, "temp_adc"}, /* Temperature readout , */\
{ 0x307, "rev_reg"}, /* Device Revision , */\
{ 0x402, "i2s_seti"}, /* I2SFormat data 1 input , */\
{ 0x431, "chan_sel1"}, /* ChannelSelection data1 input (In CoolFlux) , */\
{ 0x450, "lr_sw_i2si2"}, /* Channel Selection data 2 input (coolflux input, the DCDC converter gets the other signal), */\
{ 0x461, "input_sel"}, /* Input selection for amplifier , */\
{ 0x481, "datao_sel"}, /* Selection for I2S data out , */\
{ 0x4a0, "disable_idp"}, /* idp protection , */\
{ 0x4b0, "enbl_datao"}, /* Enable data output , */\
{ 0x4c3, "i2s_fs"}, /* sample rate setting , */\
{ 0x501, "vbat_prot_attacktime"}, /* ProtectionAttackTime , */\
{ 0x523, "vbat_prot_thlevel"}, /* ProtectionThreshold , */\
{ 0x561, "vbat_prot_max_reduct"}, /* ProtectionMaximumReduction , */\
{ 0x582, "vbat_prot_release_t"}, /* Protection Release Timer , */\
{ 0x5b1, "vbat_prot_hysterese"}, /* ProtectionHysterese , */\
{ 0x5d0, "reset_min_vbat"}, /* reset clipper , */\
{ 0x5e0, "sel_vbat"}, /* battery voltage for I2C read out only , */\
{ 0x5f0, "bypass_clipper"}, /* bypass clipper battery protection , */\
{ 0x600, "dpsa"}, /* Enable dynamic powerstage activation , */\
{ 0x613, "ctrl_slope"}, /* control slope , */\
{ 0x650, "cf_mute"}, /* Soft mute in CoolFlux , */\
{ 0x660, "sel_other_vamp"}, /* Input selection for the second channel of the DCDC inteligent mode detector, */\
{ 0x670, "ctrl_batsensesteepness"}, /* batsensesteepness , */\
{ 0x687, "vol"}, /* volume control (in CoolFlux) , */\
{ 0x702, "ctrl_bstvolt"}, /* Boost voltage , */\
{ 0x732, "ctrl_bstcur"}, /* Max boost coil current , */\
{ 0x761, "ctrl_slopebst_1_0"}, /* Setting for the slope of the boost converter power stage, */\
{ 0x781, "ctrl_slopebst_3_2"}, /* Setting for the part of the power transistor voltage to be used in peak current mode control, */\
{ 0x7a0, "boost_intel"}, /* Adaptive boost mode , */\
{ 0x7b0, "boost_speed"}, /* Soft RampUp/Down mode for DCDC controller , */\
{ 0x7c1, "ctrl_delay_comp_dcdc"}, /* delay compensation in current patg compared to delay in the audio path (relative) , */\
{ 0x7e0, "boost_input"}, /* Selection intelligent boost detector input , */\
{ 0x7f0, "ctrl_supplysense"}, /* ADC10 input selection , */\
{ 0x800, "ext_temp_sel"}, /* select external temperature also the ext_temp will be put on the temp read out , */\
{ 0x818, "ext_temp"}, /* external temperature setting to be given by host , */\
{ 0x8a0, "ctrl_spk_coilpvp_bst"}, /* Peak voltage protection boost converter , */\
{ 0x8b2, "ctrl_dcdc_synchronisation"}, /* DCDC synchronisation off + 7 positions , */\
{ 0x8e0, "ctrl_cs_samplevalid"}, /* sample valid moment for CS in single sample moment mode, */\
{ 0x900, "PowerDown"}, /* ON/OFF , */\
{ 0x910, "reset"}, /* I2CReset , */\
{ 0x920, "enbl_coolflux"}, /* EnableCoolFlux , */\
{ 0x930, "enbl_amplifier"}, /* EnableAmplifier , */\
{ 0x940, "enbl_boost"}, /* EnableBoost , */\
{ 0x950, "cf_configured"}, /* Coolflux configured , */\
{ 0x960, "sel_enbl_amplifier"}, /* Selection on how AmplifierEnabling , */\
{ 0x970, "dcdcoff_mode"}, /* DCDC not connected , */\
{ 0x980, "cttr_iddqtest"}, /* Iddq test amplifier , */\
{ 0x991, "ctrl_coil_value"}, /* Coil Value , */\
{ 0x9b1, "ctrl_sel_cf_clock"}, /* Selection CoolFluxClock , */\
{ 0x9d0, "intf_sel"}, /* Interface Selection , */\
{ 0x9e0, "sel_ws_bck"}, /* selection input PLL for lock , */\
{ 0xa02, "sel_i2so_l"}, /* Output selection dataout left channel , */\
{ 0xa32, "sel_i2so_r"}, /* Output selection dataout right channel , */\
{ 0xa62, "ctrl_spkr_coil"}, /* Selection speaker induction , */\
{ 0xa91, "ctrl_spr_res"}, /* Selection speaker impedance , */\
{ 0xab3, "ctrl_dcdc_spkr_i_comp_gain"}, /* DCDC speaker current compensation gain , */\
{ 0xaf0, "ctrl_dcdc_spkr_i_comp_sign"}, /* DCDC speaker current compensation sign , */\
{ 0xb07, "MTP_key2"}, /* MTP KEY2 register , */\
{ 0xc0c, "clk_sync_delay"}, /* Delay count for clock synchronisation , */\
{ 0xcf0, "enbl_clk_sync"}, /* Enable CGU clock synchronisation , */\
{ 0xd0c, "adc_sync_delay"}, /* Delay count for ADC synchronisation , */\
{ 0xdf0, "enable_adc_sync"}, /* Enable ADC synchronisation , */\
{ 0xe00, "bypass_dcdc_curr_prot"}, /* to switch off dcdc reduction with bat prot , */\
{ 0xe24, "ctrl_digtoana6_2"}, /* for extra connections digital to analog , */\
{ 0xe70, "switch_on_icomp"}, /* icomp dem switch , */\
{ 0xe87, "reserve_reg_1_7_0"}, /* reserved , */\
{ 0xf00, "flag_por_mask"}, /* mask flag_por for interupt generation , */\
{ 0xf10, "flag_otpok_mask"}, /* mask flag_otpok for interupt generation , */\
{ 0xf20, "flag_ovpok_mask"}, /* mask flag_ovpok for interupt generation , */\
{ 0xf30, "flag_uvpok_mask"}, /* mask flag_uvpok for interupt generation , */\
{ 0xf40, "flag_ocp_alarm_mask"}, /* mask flag_ocp_alarm for interupt generation , */\
{ 0xf50, "flag_clocks_stable_mask"}, /* mask flag_clocks_stable for interupt generation , */\
{ 0xf60, "flag_pwrokbst_mask"}, /* mask flag_pwrokbst for interupt generation , */\
{ 0xf70, "flag_cf_speakererror_mask"}, /* mask flag_cf_speakererror for interupt generation , */\
{ 0xf80, "flag_watchdog_reset_mask"}, /* mask flag_watchdog_reset for interupt generation , */\
{ 0xf90, "flag_lost_clk_mask"}, /* mask flag_lost_clk for interupt generation , */\
{ 0xfe0, "enable_interrupt"}, /* enabling interrupt , */\
{ 0xff0, "invert_int_polarity"}, /* Setting polarity interupt , */\
{ 0x1000, "pdm_i2s_input"}, /* Audio input interface mode , */\
{ 0x1010, "I2S_master_ena"}, /* I2S Master enable (CLK and WS pads) , */\
{ 0x1021, "pdm_out_sel_r"}, /* PDM Output right channel source selection , */\
{ 0x1041, "pdm_out_sel_l"}, /* PDM Output Left/Mono channel source selection , */\
{ 0x1061, "micdat_out_sel"}, /* Output interface mode and ball selection , */\
{ 0x1100, "secure_dly"}, /* Secure delay Cell , */\
{ 0x1110, "d_out_valid_rf_mux"}, /* Rising Falling Resync control Mux , */\
{ 0x1140, "Speak_As_Mic_en"}, /* Speaker As a Mic feature ON/OFF , */\
{ 0x1150, "speak_as_mic_lp_mode"}, /* speaker_as_mic low power mode (only in PDM_out mode), */\
{ 0x1160, "pdm_out_rate"}, /* PDM output interpolation ratio , */\
{ 0x1203, "ds4_g1_r"}, /* PDM Interpolator Right Channel DS4 G1 Gain Value , */\
{ 0x1243, "ds4_g2_r"}, /* PDM Interpolator Right Channel DS4 G2 Gain Value , */\
{ 0x1303, "ds4_g1_l"}, /* PDM Interpolator Left Channel DS4 G1 Gain Value , */\
{ 0x1343, "ds4_g2_l"}, /* PDM Interpolator Left Channel DS4 G2 Gain Value , */\
{ 0x1400, "clk_secure_dly"}, /* Secure delay Cell on clock path , */\
{ 0x1410, "data_secure_dly"}, /* Secure delay Cell enable on PDM data path , */\
{ 0x2202, "Ctrl_saam_pga_gain"}, /* pga gain , */\
{ 0x2250, "ctrl_saam_pga_src"}, /* 0 = active input common mode voltage source at the attenuator/PGA level, */\
{ 0x2300, "flag_saam_spare"}, /* spare flag , */\
{ 0x2400, "ctrl_saam_pga_tm"}, /* enables PGA test mode , */\
{ 0x2500, "pll_fcco"}, /* pll cco frequency , */\
{ 0x3000, "flag_hi_small"}, /* positive small window dcdc converter , */\
{ 0x3010, "flag_hi_large"}, /* positive large window dcdc converter , */\
{ 0x3020, "flag_lo_small"}, /* negative small window dcdc converter , */\
{ 0x3030, "flag_lo_large"}, /* negative large window dcdc converter , */\
{ 0x3040, "flag_voutcomp"}, /* flag_voutcomp, indication Vset is larger than Vbat, */\
{ 0x3050, "flag_voutcomp93"}, /* flag_voutcomp93, indication Vset is larger than 1.07* Vbat , */\
{ 0x3060, "flag_voutcomp86"}, /* flag_voutcomp86, indication Vset is larger than 1.14* Vbat , */\
{ 0x3070, "flag_hiz"}, /* flag_hiz, indication Vbst is larger than Vbat , */\
{ 0x3080, "flag_hi_peak"}, /* flag_hi_peak, indication hi_peak , */\
{ 0x3090, "flag_ocpokbst"}, /* flag_ocpokbst, indication no over current in boost converter pmos switch, */\
{ 0x30a0, "flag_peakcur"}, /* flag_peakcur, indication current is max in dcdc converter, */\
{ 0x30b0, "flag_ocpokap"}, /* flag_ocpokap, indication no over current in amplifier "a" pmos output stage, */\
{ 0x30c0, "flag_ocpokan"}, /* flag_ocpokan, indication no over current in amplifier "a" nmos output stage, */\
{ 0x30d0, "flag_ocpokbp"}, /* flag_ocpokbp, indication no over current in amplifier "b" pmos output stage, */\
{ 0x30e0, "flag_ocpokbn"}, /* flag_ocpokbn, indication no over current in amplifier"b" nmos output stage, */\
{ 0x30f0, "lost_clk"}, /* lost_clk, lost clock indication CGU , */\
{ 0x310f, "mtp_man_data_out"}, /* single word read from MTP (manual copy) , */\
{ 0x3200, "key01_locked"}, /* key01_locked, indication key 1 is locked , */\
{ 0x3210, "key02_locked"}, /* key02_locked, indication key 2 is locked , */\
{ 0x3225, "mtp_ecc_tcout"}, /* mtp_ecc_tcout , */\
{ 0x3280, "mtpctrl_valid_test_rd"}, /* mtp test readout for read , */\
{ 0x3290, "mtpctrl_valid_test_wr"}, /* mtp test readout for write , */\
{ 0x32a0, "flag_in_alarm_state"}, /* alarm state , */\
{ 0x32b0, "mtp_ecc_err2"}, /* two or more bit errors detected in MTP, can not reconstruct value, */\
{ 0x32c0, "mtp_ecc_err1"}, /* one bit error detected in MTP, reconstructed value, */\
{ 0x32d0, "mtp_mtp_hvf"}, /* high voltage ready flag for MTP , */\
{ 0x32f0, "mtp_zero_check_fail"}, /* zero check failed (tbd) for MTP , */\
{ 0x3300, "flag_adc10_ready"}, /* flag_adc10_ready, indication adc10 is ready , */\
{ 0x3310, "flag_clipa_high"}, /* flag_clipa_high, indication pmos amplifier "a" is clipping, */\
{ 0x3320, "flag_clipa_low"}, /* flag_clipa_low, indication nmos amplifier "a" is clipping, */\
{ 0x3330, "flag_clipb_high"}, /* flag_clipb_high, indication pmos amplifier "b" is clipping, */\
{ 0x3340, "flag_clipb_low"}, /* flag_clipb_low, indication nmos amplifier "b" is clipping, */\
{ 0x3359, "data_adc10_tempbat"}, /* adc 10 data output for testing , */\
{ 0x33f0, "flag_vddd_comp_nok"}, /* power switch flag 2 for testing , */\
{ 0x400f, "hid_code"}, /* hidden code , */\
{ 0x4100, "bypass_hp"}, /* Bypass_High Pass Filter , */\
{ 0x4110, "hard_mute"}, /* Hard Mute , */\
{ 0x4120, "soft_mute"}, /* Soft Mute , */\
{ 0x4134, "PWM_Delay"}, /* PWM DelayBits to set the delay , */\
{ 0x4180, "PWM_Shape"}, /* PWM Shape , */\
{ 0x4190, "PWM_BitLength"}, /* PWM Bitlength in noise shaper , */\
{ 0x4207, "ctrl_drive"}, /* drive bits to select amount of power stages amplifier, */\
{ 0x4281, "dpsalevel"}, /* DPSA Threshold level , */\
{ 0x42a1, "dpsa_release"}, /* DPSA Release time , */\
{ 0x42c0, "ctrl_coincidence"}, /* Prevent simultaneously switching of output stage , */\
{ 0x42d0, "ctrl_kickback"}, /* Prevent double pulses of output stage , */\
{ 0x42e0, "ctrl_test_sdeltaoffset"}, /* ctrl_test_sdeltaoffset , */\
{ 0x42f0, "ctrl_test_sdeltaclk"}, /* ctrl_test_sdeltaclk , */\
{ 0x4309, "ctrl_drivebst"}, /* Drive bits to select the powertransistor sections boost converter, */\
{ 0x43a0, "ctrl_ocptestbst"}, /* Boost OCP. , */\
{ 0x43c0, "enbl_hi_peak"}, /* enable for high peak comparator , */\
{ 0x43d0, "test_abistfft_enbl"}, /* FFT coolflux , */\
{ 0x43e0, "ctrl_sensetest_amp"}, /* sensetest amplifier , */\
{ 0x43f0, "test_bcontrol"}, /* test _bcontrol , */\
{ 0x4400, "ctrl_reversebst"}, /* OverCurrent Protection selection of power stage boost converter, */\
{ 0x4410, "ctrl_sensetest"}, /* Test option for the sense NMOS in booster for current mode control., */\
{ 0x4420, "enbl_engagebst"}, /* Enable power stage dcdc controller , */\
{ 0x4430, "enbl_hi_small"}, /* Enable bit of hi (small) comparator , */\
{ 0x4440, "enbl_hi_large"}, /* Enable bit of hi (large) comparator , */\
{ 0x4450, "enbl_lo_small"}, /* Enable bit of lo (small) comparator , */\
{ 0x4460, "enbl_lo_large"}, /* Enable bit of lo (large) comparator , */\
{ 0x4470, "enbl_slopecur"}, /* Enable bit of max-current dac , */\
{ 0x4480, "enbl_voutcomp"}, /* Enable vout comparators , */\
{ 0x4490, "enbl_voutcomp93"}, /* Enable vout-93 comparators , */\
{ 0x44a0, "enbl_voutcomp86"}, /* Enable vout-86 comparators , */\
{ 0x44b0, "enbl_hizcom"}, /* Enable hiz comparator , */\
{ 0x44c0, "enbl_pcdac"}, /* Enable peak current dac , */\
{ 0x44d0, "enbl_pccomp"}, /* Enable peak current comparator , */\
{ 0x44e0, "enbl_windac"}, /* Enable window dac , */\
{ 0x44f0, "enbl_powerbst"}, /* Enable line of the powerstage , */\
{ 0x4507, "ocp_thr"}, /* ocp_thr threshold level for OCP , */\
{ 0x4580, "bypass_glitchfilter"}, /* Bypass glitchfilter , */\
{ 0x4590, "bypass_ovp"}, /* Bypass OVP , */\
{ 0x45a0, "bypass_uvp"}, /* Bypass UVP , */\
{ 0x45b0, "bypass_otp"}, /* Bypass OTP , */\
{ 0x45c0, "bypass_ocp"}, /* Bypass OCP , */\
{ 0x45d0, "bypass_ocpcounter"}, /* BypassOCPCounter , */\
{ 0x45e0, "bypass_lost_clk"}, /* Bypasslost_clk detector , */\
{ 0x45f0, "vpalarm"}, /* vpalarm (uvp ovp handling) , */\
{ 0x4600, "bypass_gc"}, /* bypass_gc, bypasses the CS gain correction , */\
{ 0x4610, "cs_gain_control"}, /* gain control by means of MTP or i2c , */\
{ 0x4627, "cs_gain"}, /* + / - 128 steps in steps of 1/4 % 2's compliment , */\
{ 0x46a0, "bypass_lp"}, /* bypass Low-Pass filter in temperature sensor , */\
{ 0x46b0, "bypass_pwmcounter"}, /* bypass_pwmcounter , */\
{ 0x46c0, "ctrl_cs_negfixed"}, /* does not switch to neg , */\
{ 0x46d2, "ctrl_cs_neghyst"}, /* switches to neg depending on level , */\
{ 0x4700, "switch_fb"}, /* switch_fb , */\
{ 0x4713, "se_hyst"}, /* se_hyst , */\
{ 0x4754, "se_level"}, /* se_level , */\
{ 0x47a5, "ktemp"}, /* temperature compensation trimming , */\
{ 0x4800, "ctrl_negin"}, /* negin , */\
{ 0x4810, "ctrl_cs_sein"}, /* cs_sein , */\
{ 0x4820, "ctrl_coincidencecs"}, /* Coincidence current sense , */\
{ 0x4830, "ctrl_iddqtestbst"}, /* for iddq testing in powerstage of boost convertor , */\
{ 0x4840, "ctrl_coincidencebst"}, /* Switch protection on to prevent simultaniously switching power stages bst and amp, */\
{ 0x4851, "clock_sh_sel"}, /* Clock SH selection , */\
{ 0x4876, "delay_se_neg"}, /* delay of se and neg , */\
{ 0x48e1, "ctrl_cs_ttrack"}, /* sample & hold track time , */\
{ 0x4900, "ctrl_bypassclip"}, /* Bypass clip control (function depending on digimux clip_x), */\
{ 0x4910, "ctrl_bypassclip2"}, /* Bypass clip control (function depending on digimux clip_x), */\
{ 0x4920, "ctrl_clkgateCFoff"}, /* to disable clock gating in the coolflux , */\
{ 0x4930, "ctrl_testabst"}, /* testabst , */\
{ 0x4940, "ctrl_clipfast"}, /* clock switch for battery protection clipper, it switches back to old frequency, */\
{ 0x4950, "ctrl_cs_8ohm"}, /* 8 ohm mode for current sense (gain mode) , */\
{ 0x4960, "reserved"}, /* reserved , */\
{ 0x4974, "delay_clock_sh"}, /* delay_sh, tunes S7H delay , */\
{ 0x49c0, "inv_clksh"}, /* Invert the sample/hold clock for current sense ADC, */\
{ 0x49d0, "inv_neg"}, /* Invert neg signal , */\
{ 0x49e0, "inv_se"}, /* Invert se signal , */\
{ 0x49f0, "setse"}, /* switches between Single Ende and differentail mode, */\
{ 0x4a12, "ctrl_adc10_sel"}, /* select the input to convert the 10b ADC , */\
{ 0x4a60, "ctrl_adc10_reset"}, /* Global asynchronous reset (active HIGH) 10 bit ADC, */\
{ 0x4a81, "ctrl_adc10_test"}, /* Test mode selection signal 10 bit ADC , */\
{ 0x4aa0, "ctrl_bypass_lp_vbat"}, /* lp filter in batt sensor , */\
{ 0x4ae0, "ctrl_dc_offset"}, /* switch offset control on/off, is decimator offset control, */\
{ 0x4af0, "ctrl_tsense_hibias"}, /* bit to set the biasing in temp sensor to high , */\
{ 0x4b00, "ctrl_adc13_iset"}, /* Micadc Setting of current consumption. Debug use only, */\
{ 0x4b14, "ctrl_adc13_gain"}, /* Micadc gain setting (2-compl) , */\
{ 0x4b61, "ctrl_adc13_slowdel"}, /* Micadc Delay setting for internal clock. Debug use only, */\
{ 0x4b83, "ctrl_adc13_offset"}, /* Micadc ADC offset setting , */\
{ 0x4bc0, "ctrl_adc13_bsoinv"}, /* Micadc bit stream output invert mode for test , */\
{ 0x4bd0, "ctrl_adc13_resonator_enable"}, /* Micadc Give extra SNR with less stability. Debug use only, */\
{ 0x4be0, "ctrl_testmicadc"}, /* Mux at input of MICADC for test purpose , */\
{ 0x4c0f, "ctrl_offset"}, /* offset control for ABIST testing , */\
{ 0x4d05, "ctrl_windac"}, /* for testing direct control windac , */\
{ 0x4d65, "ctrl_peakcur"}, /* Control peakcur , */\
{ 0x4dc3, "pwm_dcc_cnt"}, /* control pwm duty cycle when enbl_pwm_dcc is 1 , */\
{ 0x4e04, "ctrl_slopecur"}, /* for testing direct control slopecur , */\
{ 0x4e53, "ctrl_dem"}, /* dyn element matching control, rest of codes are optional, */\
{ 0x4e93, "ctrl_demmismatch"}, /* dyn element matching add offset , */\
{ 0x4ed0, "enbl_pwm_dcc"}, /* to enable direct control of pwm duty cycle , */\
{ 0x5007, "gain"}, /* gain setting of the gain multiplier gain need to increase with factor 1.41 (3dB), */\
{ 0x5081, "ctrl_sourceb"}, /* Set OUTB to , */\
{ 0x50a1, "ctrl_sourcea"}, /* Set OUTA to , */\
{ 0x50c1, "ctrl_sourcebst"}, /* Sets the source of the pwmbst output to boost converter input for testing, */\
{ 0x50e1, "ctrl_test_mono"}, /* ABIST mode to add both amplifier halfs as stereo or one amplifier half as mono, */\
{ 0x5104, "pulselengthbst"}, /* pulselength setting test input for boost converter , */\
{ 0x5150, "ctrl_bypasslatchbst"}, /* bypass_latch in boost converter , */\
{ 0x5160, "invertbst"}, /* invert pwmbst test signal , */\
{ 0x5174, "pulselength"}, /* pulselength setting test input for amplifier , */\
{ 0x51c0, "ctrl_bypasslatch"}, /* bypass_latch in boost convert , */\
{ 0x51d0, "invertb"}, /* invert pwmb test signal , */\
{ 0x51e0, "inverta"}, /* invert pwma test signal , */\
{ 0x51f0, "ctrl_bypass_ctrlloop"}, /* bypass_ctrlloop bypasses the control loop of the amplifier, */\
{ 0x5200, "ctrl_test_discrete"}, /* tbd for rdson testing , */\
{ 0x5210, "ctrl_test_rdsona"}, /* tbd for rdson testing , */\
{ 0x5220, "ctrl_test_rdsonb"}, /* tbd for rdson testing , */\
{ 0x5230, "ctrl_test_rdsonbst"}, /* tbd for rdson testing , */\
{ 0x5240, "ctrl_test_cvia"}, /* tbd for rdson testing , */\
{ 0x5250, "ctrl_test_cvib"}, /* tbd for rdson testing , */\
{ 0x5260, "ctrl_test_cvibst"}, /* tbd for rdson testing , */\
{ 0x5290, "test_bypass_pwmdiscretea"}, /* for testing ( ABIST) , */\
{ 0x52a0, "test_bypass_pwmdiscreteb"}, /* for testing ( ABIST) , */\
{ 0x52b0, "ctrl_clipc_forcehigh"}, /* test signal for clipcontrol , */\
{ 0x52c0, "ctrl_clipc_forcelow"}, /* test signal for clipcontrol , */\
{ 0x52d0, "ctrl_test_sdelta"}, /* for testing ( ABIST) , */\
{ 0x52e0, "ctrl_test_swhvp"}, /* for testing ( ABIST) , */\
{ 0x52f0, "test_gain_reduction"}, /* test gain reduction , */\
{ 0x5303, "ctrl_digimux_out_test1"}, /* Digimux TEST1 out , */\
{ 0x5343, "ctrl_digimux_out_test2"}, /* Digimux TEST2 out. output flag_clipa_low depending on cntr_bypassclip setting, */\
{ 0x5383, "ctrl_digimux_out_data1"}, /* Digimux DATA1 out (output flag_clipb_high depending on cntr_bypassclip setting), */\
{ 0x53c3, "ctrl_digimux_out_data3"}, /* Digimux DATA3 out (output flag_clipx_x depending on cntr_bypassclip setting), */\
{ 0x5400, "hs_mode"}, /* hs_mode, high speed mode I2C bus , */\
{ 0x5412, "test_parametric_io"}, /* test_parametric_io for testing pads , */\
{ 0x5440, "enbl_ringo"}, /* enbl_ringo, for test purpose to check with ringo , */\
{ 0x5480, "ctrl_cliplevel"}, /* Clip level , */\
{ 0x5491, "ctrl_anamux_sel"}, /* anamux selection , */\
{ 0x54b0, "test_vdddsw_dio"}, /* to overrule the power switches for memory , */\
{ 0x54c0, "ctrl_bypass_diosw_ovp"}, /* To disable the overvoltage protection of vddd_dio_sw, */\
{ 0x54d0, "test_vddd_sw"}, /* test vdd sw , */\
{ 0x54e0, "test_vddd_sw_comp"}, /* test vdd sw comp , */\
{ 0x550e, "enbl_amp"}, /* enbl_amp for testing to enable all analoge blocks in amplifier, */\
{ 0x55f0, "fr_fsp"}, /* extr free running clock mode for testing , */\
{ 0x5600, "use_direct_ctrls"}, /* use_direct_ctrls, to overrule several functions direct for testing, */\
{ 0x5610, "rst_datapath"}, /* rst_datapath, datapath reset , */\
{ 0x5620, "rst_cgu"}, /* rst_cgu, cgu reset , */\
{ 0x5637, "enbl_ref"}, /* for testing to enable all analoge blocks in references, */\
{ 0x56b0, "enbl_engage"}, /* Enable output stage amplifier , */\
{ 0x56c0, "use_direct_clk_ctrl"}, /* use_direct_clk_ctrl, to overrule several functions direct for testing, */\
{ 0x56d0, "use_direct_pll_ctrl"}, /* use_direct_pll_ctrl, to overrule several functions direct for test, */\
{ 0x56e0, "use_direct_ctrls_2"}, /* use_direct_sourseamp_ctrls, to overrule several functions direct for testing, */\
{ 0x5707, "ctrl_anamux_out_test1"}, /* Anamux control , */\
{ 0x5782, "ctrl_zero"}, /* Bandwith control feedbackloop , */\
{ 0x57b0, "enbl_ldo_stress"}, /* LDO stress function frinch capacitors , */\
{ 0x57c0, "ctrl_ocptest"}, /* ctrl_ocptest, deactivates the over current protection in the power stages of the amplifier. The ocp flag signals stay active., */\
{ 0x57e0, "ctrl_otptest"}, /* otptest, test mode otp amplifier , */\
{ 0x57f0, "ctrl_reverse"}, /* CTRL revers , */\
{ 0x5802, "pll_mdec_msb"}, /* most significant bits pll_mdec , */\
{ 0x5833, "pll_selr"}, /* pll_selr , */\
{ 0x5874, "pll_selp"}, /* pll_selp , */\
{ 0x58c3, "pll_seli"}, /* pll_seli , */\
{ 0x5900, "pll_psel"}, /* pll_psel , */\
{ 0x5910, "use_direct_pll_psel"}, /* use_direct_pll_psel , */\
{ 0x5923, "nbck"}, /* NBCK , */\
{ 0x5960, "auto_nbck"}, /* AUTO_NBCK , */\
{ 0x5970, "pll_frm"}, /* pll_frm , */\
{ 0x5980, "pll_directi"}, /* pll_directi , */\
{ 0x5990, "pll_directo"}, /* pll_directo , */\
{ 0x59a0, "enbl_PLL"}, /* enbl_PLL , */\
{ 0x59b0, "sel_clkout"}, /* SEL_CLKOUT , */\
{ 0x59e0, "fr_lost_clk"}, /* fr_lost_clk , */\
{ 0x59f0, "pll_bypass"}, /* pll_bypass , */\
{ 0x5a0f, "tsig_freq"}, /* tsig_freq, internal sinus test generator, frequency control, */\
{ 0x5b02, "tsig_freq_msb"}, /* select internal sinus test generator, frequency control msb bits, */\
{ 0x5b30, "inject_tsig"}, /* inject_tsig, control bit to switch to internal sinus test generator, */\
{ 0x5b44, "ctrl_adc10_prog_sample"}, /* control ADC10 , */\
{ 0x5c01, "pll_ndec_msb"}, /* most significant bits of pll_ndec , */\
{ 0x5c2d, "pll_mdec"}, /* bits 13..0 of pll_mdec , */\
{ 0x5d06, "pll_pdec"}, /* pll_pdec , */\
{ 0x5d87, "pll_ndec"}, /* bits 7..0 of pll_ndec , */\
{ 0x5e00, "pdm_ch_sel_reg"}, /* PDM channel selection , */\
{ 0x5e10, "pdm_iis_rst_reg"}, /* PDM Interface reset , */\
{ 0x5e20, "clk_src_sel_reg"}, /* WS Source Selection , */\
{ 0x5e70, "pdm_resync_bypass"}, /* PDM resynchronization bypass , */\
{ 0x6007, "MTP_key1"}, /* MTP Key1 , */\
{ 0x6185, "mtp_ecc_tcin"}, /* Mtp_ecc_tcin , */\
{ 0x6203, "mtp_man_address_in"}, /* address from i2cregs for writing one word single mtp, */\
{ 0x6260, "mtp_ecc_eeb"}, /* enable code bit generation (active low!) , */\
{ 0x6270, "mtp_ecc_ecb"}, /* enable correction signal (active low!) , */\
{ 0x6280, "man_copy_mtp_to_iic"}, /* start copying single word from mtp to i2cregs_mtp , */\
{ 0x6290, "man_copy_iic_to_mtp"}, /* start copying single word from i2cregs_mtp to mtp [Key 1 protected], */\
{ 0x62a0, "auto_copy_mtp_to_iic"}, /* start copying all the data from mtp to i2cregs_mtp, */\
{ 0x62b0, "auto_copy_iic_to_mtp"}, /* start copying all the data from i2cregs_mtp to mtp [Key 2 protected], */\
{ 0x62d2, "mtp_speed_mode"}, /* Speed mode , */\
{ 0x6340, "mtp_dircet_enable"}, /* mtp_direct_enable (key1 protected) , */\
{ 0x6350, "mtp_direct_wr"}, /* mtp_direct_wr (key1 protected) direct value for mtp pin wr. To be enabled via iic2mtp_mtp_direct_enable, */\
{ 0x6360, "mtp_direct_rd"}, /* mtp_direct_rd (key1 protected) direct value for mtp pin rd. To be enabled via iic2mtp_mtp_direct_enable, */\
{ 0x6370, "mtp_direct_rst"}, /* mtp_direct_rst (key1 protected) direct value for mtp pin rst. To be enabled via iic2mtp_mtp_direct_enable, */\
{ 0x6380, "mtp_direct_ers"}, /* mtp_direct_ers (key1 protected) direct value for mtp pin ers. To be enabled via iic2mtp_mtp_direct_enable, */\
{ 0x6390, "mtp_direct_prg"}, /* mtp_direct_prg (key1 protected) direct value for mtp pin prg. To be enabled via iic2mtp_mtp_direct_enable, */\
{ 0x63a0, "mtp_direct_epp"}, /* mtp_direct_epp (key1 protected) direct value for mtp pin epp. To be enabled via iic2mtp_mtp_direct_enable, */\
{ 0x63b4, "mtp_direct_test"}, /* mtp_direct_test (key1 protected) , */\
{ 0x640f, "mtp_man_data_in"}, /* single wordt be written to MTP (manual copy) , */\
{ 0x7000, "cf_rst_dsp"}, /* Reset CoolFlux DSP , */\
{ 0x7011, "cf_dmem"}, /* Target memory for access , */\
{ 0x7030, "cf_aif"}, /* Autoincrement-flag for memory-address , */\
{ 0x7040, "cf_int"}, /* Interrupt CoolFlux DSP , */\
{ 0x7087, "cf_req"}, /* request for access (8 channels) , */\
{ 0x710f, "cf_madd"}, /* memory-address to be accessed , */\
{ 0x720f, "cf_mema"}, /* activate memory access (24- or 32-bits data is written/read to/from memory, */\
{ 0x7307, "cf_err"}, /* cf error Flags , */\
{ 0x7387, "cf_ack"}, /* acknowledge of requests (8 channels")" , */\
{ 0x8000, "calibration_onetime"}, /* Calibration schedule (key2 protected) , */\
{ 0x8010, "calibr_ron_done"}, /* (key2 protected) calibration of Ron has been executed, */\
{ 0x8105, "calibr_vout_offset"}, /* calibr_vout_offset (DCDCoffset) 2's compliment (key1 protected), */\
{ 0x8163, "calibr_delta_gain"}, /* delta gain for vamp (alpha) 2's compliment (key1 protected), */\
{ 0x81a5, "calibr_offs_amp"}, /* offset for vamp (Ampoffset) 2's compliment (key1 protected), */\
{ 0x8207, "calibr_gain_cs"}, /* gain current sense (Imeasalpha) 2's compliment (key1 protected), */\
{ 0x8284, "calibr_temp_offset"}, /* temperature offset 2's compliment (key1 protected), */\
{ 0x82d2, "calibr_temp_gain"}, /* temperature gain 2's compliment (key1 protected) , */\
{ 0x830f, "calibr_ron"}, /* Ron resistance of coil (key1 protected) , */\
{ 0x8406, "ctrl_offset_a"}, /* Offset of amplifier level shifter , */\
{ 0x8486, "ctrl_offset_b"}, /* Offset of amplifier level shifter , */\
{ 0x850f, "type_bits_HW"}, /* HW Bits , */\
{ 0x860f, "type_bits1_SW"}, /* MTP-control SW1 , */\
{ 0x870f, "type_bits2_SW"}, /* MTP-control SW2 , */\
{ 0x8a0f, "production_data1"}, /* (key1 protected) , */\
{ 0x8b0f, "production_data2"}, /* (key1 protected) , */\
{ 0x8c0f, "production_data3"}, /* (key1 protected) , */\
{ 0x8d0f, "production_data4"}, /* (key1 protected) , */\
{ 0x8e0f, "production_data5"}, /* (key1 protected) , */\
{ 0x8f0f, "production_data6"}, /* (key1 protected) , */\
{ 0xffff,"Unknown bitfield enum" } /* not found */\
};
#endif /* TFA_INC_TFA9891_TFAFIELDNAMES_H_ */

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/*
* Copyright (C) 2014-2020 NXP Semiconductors, All Rights Reserved.
* Copyright 2020 GOODIX
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
*/
/** Filename: tfa9896_tfafieldnames.h
* This file was generated automatically on 08/15/16 at 09:43:38.
* Source file: TFA9896_N1B1_I2C_regmap_V16.xlsx
*/
#ifndef _TFA9896_TFAFIELDNAMES_H
#define _TFA9896_TFAFIELDNAMES_H
#define TFA9896_I2CVERSION 16
typedef enum TFA9896BfEnumList {
TFA9896_BF_VDDS = 0x0000, /*!< Power-on-reset flag (auto clear by reading) */
TFA9896_BF_PLLS = 0x0010, /*!< PLL lock to programmed frequency */
TFA9896_BF_OTDS = 0x0020, /*!< Over Temperature Protection alarm */
TFA9896_BF_OVDS = 0x0030, /*!< Over Voltage Protection alarm */
TFA9896_BF_UVDS = 0x0040, /*!< Under Voltage Protection alarm */
TFA9896_BF_OCDS = 0x0050, /*!< Over Current Protection alarm */
TFA9896_BF_CLKS = 0x0060, /*!< Clocks stable flag */
TFA9896_BF_CLIPS = 0x0070, /*!< Amplifier clipping */
TFA9896_BF_MTPB = 0x0080, /*!< MTP busy copying data to/from I2C registers */
TFA9896_BF_NOCLK = 0x0090, /*!< lost clock detection (reference input clock) */
TFA9896_BF_SPKS = 0x00a0, /*!< Speaker error */
TFA9896_BF_ACS = 0x00b0, /*!< Cold Start required */
TFA9896_BF_SWS = 0x00c0, /*!< Amplifier engage (Amp Switching) */
TFA9896_BF_WDS = 0x00d0, /*!< watchdog reset (activates reset) */
TFA9896_BF_AMPS = 0x00e0, /*!< Amplifier is enabled by manager */
TFA9896_BF_AREFS = 0x00f0, /*!< References are enabled by manager */
TFA9896_BF_BATS = 0x0109, /*!< Battery voltage from ADC readout */
TFA9896_BF_TEMPS = 0x0208, /*!< Temperature readout from the temperature sensor ( C) */
TFA9896_BF_REV = 0x030f, /*!< Device revision information */
TFA9896_BF_RCV = 0x0420, /*!< Enable receiver mode */
TFA9896_BF_CHS12 = 0x0431, /*!< Channel Selection TDM input for Coolflux */
TFA9896_BF_INPLVL= 0x0450, /*!< Input level selection attenuator ( */
TFA9896_BF_CHSA = 0x0461, /*!< Input selection for amplifier */
TFA9896_BF_AUDFS = 0x04c3, /*!< Audio sample rate setting */
TFA9896_BF_BSSCR = 0x0501, /*!< Batteery protection attack time */
TFA9896_BF_BSST = 0x0523, /*!< Battery protection threshold level */
TFA9896_BF_BSSRL = 0x0561, /*!< Battery protection maximum reduction */
TFA9896_BF_BSSRR = 0x0582, /*!< Battery protection release time */
TFA9896_BF_BSSHY = 0x05b1, /*!< Battery Protection Hysteresis */
TFA9896_BF_BSSR = 0x05e0, /*!< Battery voltage value for read out (only) */
TFA9896_BF_BSSBY = 0x05f0, /*!< Bypass clipper battery protection */
TFA9896_BF_DPSA = 0x0600, /*!< Enable dynamic powerstage activation (DPSA) */
TFA9896_BF_ATTEN = 0x0613, /*!< Gain attenuation setting */
TFA9896_BF_CFSM = 0x0650, /*!< Soft mute in CoolFlux */
TFA9896_BF_BSSS = 0x0670, /*!< Battery sense steepness */
TFA9896_BF_VOL = 0x0687, /*!< Coolflux volume control */
TFA9896_BF_DCVO2 = 0x0702, /*!< Second Boost Voltage */
TFA9896_BF_DCMCC = 0x0733, /*!< Max boost coil current - step of 175 mA */
TFA9896_BF_DCVO1 = 0x0772, /*!< First Boost Voltage */
TFA9896_BF_DCIE = 0x07a0, /*!< Adaptive boost mode */
TFA9896_BF_DCSR = 0x07b0, /*!< Soft Rampup/down mode for DCDC controller */
TFA9896_BF_DCPAVG= 0x07c0, /*!< ctrl_peak2avg for analog part of DCDC */
TFA9896_BF_DCPWM = 0x07d0, /*!< DCDC PWM only mode */
TFA9896_BF_TROS = 0x0800, /*!< Selection ambient temperature for speaker calibration */
TFA9896_BF_EXTTS = 0x0818, /*!< External temperature for speaker calibration (C) */
TFA9896_BF_PWDN = 0x0900, /*!< powerdown selection */
TFA9896_BF_I2CR = 0x0910, /*!< All I2C registers reset to default */
TFA9896_BF_CFE = 0x0920, /*!< Enable CoolFlux */
TFA9896_BF_AMPE = 0x0930, /*!< Enable Amplifier */
TFA9896_BF_DCA = 0x0940, /*!< Enable DCDC Boost converter */
TFA9896_BF_SBSL = 0x0950, /*!< Coolflux configured */
TFA9896_BF_AMPC = 0x0960, /*!< Selection if Coolflux enables amplifier */
TFA9896_BF_DCDIS = 0x0970, /*!< DCDC boost converter not connected */
TFA9896_BF_PSDR = 0x0980, /*!< IDDQ amplifier test selection */
TFA9896_BF_INTPAD= 0x09c1, /*!< INT pad (interrupt bump output) configuration */
TFA9896_BF_IPLL = 0x09e0, /*!< PLL input reference clock selection */
TFA9896_BF_DCTRIP= 0x0a04, /*!< Adaptive boost trip levels (effective only when boost_intel is set to 1) */
TFA9896_BF_DCHOLD= 0x0a54, /*!< Hold time for DCDC booster (effective only when boost_intel is set to 1) */
TFA9896_BF_MTPK = 0x0b07, /*!< KEY2 to access key2 protected registers (default for engineering) */
TFA9896_BF_CVFDLY= 0x0c25, /*!< Fractional delay adjustment between current and voltage sense */
TFA9896_BF_OPENMTP= 0x0ec0, /*!< Enable programming of the MTP memory */
TFA9896_BF_TDMPRF= 0x1011, /*!< TDM usecase selection control */
TFA9896_BF_TDMEN = 0x1030, /*!< TDM interface enable */
TFA9896_BF_TDMCKINV= 0x1040, /*!< TDM clock inversion, receive on */
TFA9896_BF_TDMFSLN= 0x1053, /*!< TDM FS length */
TFA9896_BF_TDMFSPOL= 0x1090, /*!< TDM FS polarity (start frame) */
TFA9896_BF_TDMSAMSZ= 0x10a4, /*!< TDM sample size for all TDM sinks and sources */
TFA9896_BF_TDMSLOTS= 0x1103, /*!< TDM number of slots */
TFA9896_BF_TDMSLLN= 0x1144, /*!< TDM slot length */
TFA9896_BF_TDMBRMG= 0x1194, /*!< TDM bits remaining after the last slot */
TFA9896_BF_TDMDDEL= 0x11e0, /*!< TDM data delay */
TFA9896_BF_TDMDADJ= 0x11f0, /*!< TDM data adjustment */
TFA9896_BF_TDMTXFRM= 0x1201, /*!< TDM TXDATA format */
TFA9896_BF_TDMUUS0= 0x1221, /*!< TDM TXDATA format unused slot SD0 */
TFA9896_BF_TDMUUS1= 0x1241, /*!< TDM TXDATA format unused slot SD1 */
TFA9896_BF_TDMSI0EN= 0x1270, /*!< TDM sink0 enable */
TFA9896_BF_TDMSI1EN= 0x1280, /*!< TDM sink1 enable */
TFA9896_BF_TDMSI2EN= 0x1290, /*!< TDM sink2 enable */
TFA9896_BF_TDMSO0EN= 0x12a0, /*!< TDM source0 enable */
TFA9896_BF_TDMSO1EN= 0x12b0, /*!< TDM source1 enable */
TFA9896_BF_TDMSO2EN= 0x12c0, /*!< TDM source2 enable */
TFA9896_BF_TDMSI0IO= 0x12d0, /*!< TDM sink0 IO selection */
TFA9896_BF_TDMSI1IO= 0x12e0, /*!< TDM sink1 IO selection */
TFA9896_BF_TDMSI2IO= 0x12f0, /*!< TDM sink2 IO selection */
TFA9896_BF_TDMSO0IO= 0x1300, /*!< TDM source0 IO selection */
TFA9896_BF_TDMSO1IO= 0x1310, /*!< TDM source1 IO selection */
TFA9896_BF_TDMSO2IO= 0x1320, /*!< TDM source2 IO selection */
TFA9896_BF_TDMSI0SL= 0x1333, /*!< TDM sink0 slot position [GAIN IN] */
TFA9896_BF_TDMSI1SL= 0x1373, /*!< TDM sink1 slot position [CH1 IN] */
TFA9896_BF_TDMSI2SL= 0x13b3, /*!< TDM sink2 slot position [CH2 IN] */
TFA9896_BF_TDMSO0SL= 0x1403, /*!< TDM source0 slot position [GAIN OUT] */
TFA9896_BF_TDMSO1SL= 0x1443, /*!< TDM source1 slot position [Voltage Sense] */
TFA9896_BF_TDMSO2SL= 0x1483, /*!< TDM source2 slot position [Current Sense] */
TFA9896_BF_NBCK = 0x14c3, /*!< TDM NBCK bit clock ratio */
TFA9896_BF_INTOVDDS= 0x2000, /*!< flag_por_int_out */
TFA9896_BF_INTOPLLS= 0x2010, /*!< flag_pll_lock_int_out */
TFA9896_BF_INTOOTDS= 0x2020, /*!< flag_otpok_int_out */
TFA9896_BF_INTOOVDS= 0x2030, /*!< flag_ovpok_int_out */
TFA9896_BF_INTOUVDS= 0x2040, /*!< flag_uvpok_int_out */
TFA9896_BF_INTOOCDS= 0x2050, /*!< flag_ocp_alarm_int_out */
TFA9896_BF_INTOCLKS= 0x2060, /*!< flag_clocks_stable_int_out */
TFA9896_BF_INTOCLIPS= 0x2070, /*!< flag_clip_int_out */
TFA9896_BF_INTOMTPB= 0x2080, /*!< mtp_busy_int_out */
TFA9896_BF_INTONOCLK= 0x2090, /*!< flag_lost_clk_int_out */
TFA9896_BF_INTOSPKS= 0x20a0, /*!< flag_cf_speakererror_int_out */
TFA9896_BF_INTOACS= 0x20b0, /*!< flag_cold_started_int_out */
TFA9896_BF_INTOSWS= 0x20c0, /*!< flag_engage_int_out */
TFA9896_BF_INTOWDS= 0x20d0, /*!< flag_watchdog_reset_int_out */
TFA9896_BF_INTOAMPS= 0x20e0, /*!< flag_enbl_amp_int_out */
TFA9896_BF_INTOAREFS= 0x20f0, /*!< flag_enbl_ref_int_out */
TFA9896_BF_INTOERR= 0x2200, /*!< flag_cfma_err_int_out */
TFA9896_BF_INTOACK= 0x2210, /*!< flag_cfma_ack_int_out */
TFA9896_BF_INTIVDDS= 0x2300, /*!< flag_por_int_in */
TFA9896_BF_INTIPLLS= 0x2310, /*!< flag_pll_lock_int_in */
TFA9896_BF_INTIOTDS= 0x2320, /*!< flag_otpok_int_in */
TFA9896_BF_INTIOVDS= 0x2330, /*!< flag_ovpok_int_in */
TFA9896_BF_INTIUVDS= 0x2340, /*!< flag_uvpok_int_in */
TFA9896_BF_INTIOCDS= 0x2350, /*!< flag_ocp_alarm_int_in */
TFA9896_BF_INTICLKS= 0x2360, /*!< flag_clocks_stable_int_in */
TFA9896_BF_INTICLIPS= 0x2370, /*!< flag_clip_int_in */
TFA9896_BF_INTIMTPB= 0x2380, /*!< mtp_busy_int_in */
TFA9896_BF_INTINOCLK= 0x2390, /*!< flag_lost_clk_int_in */
TFA9896_BF_INTISPKS= 0x23a0, /*!< flag_cf_speakererror_int_in */
TFA9896_BF_INTIACS= 0x23b0, /*!< flag_cold_started_int_in */
TFA9896_BF_INTISWS= 0x23c0, /*!< flag_engage_int_in */
TFA9896_BF_INTIWDS= 0x23d0, /*!< flag_watchdog_reset_int_in */
TFA9896_BF_INTIAMPS= 0x23e0, /*!< flag_enbl_amp_int_in */
TFA9896_BF_INTIAREFS= 0x23f0, /*!< flag_enbl_ref_int_in */
TFA9896_BF_INTIERR= 0x2500, /*!< flag_cfma_err_int_in */
TFA9896_BF_INTIACK= 0x2510, /*!< flag_cfma_ack_int_in */
TFA9896_BF_INTENVDDS= 0x2600, /*!< flag_por_int_enable */
TFA9896_BF_INTENPLLS= 0x2610, /*!< flag_pll_lock_int_enable */
TFA9896_BF_INTENOTDS= 0x2620, /*!< flag_otpok_int_enable */
TFA9896_BF_INTENOVDS= 0x2630, /*!< flag_ovpok_int_enable */
TFA9896_BF_INTENUVDS= 0x2640, /*!< flag_uvpok_int_enable */
TFA9896_BF_INTENOCDS= 0x2650, /*!< flag_ocp_alarm_int_enable */
TFA9896_BF_INTENCLKS= 0x2660, /*!< flag_clocks_stable_int_enable */
TFA9896_BF_INTENCLIPS= 0x2670, /*!< flag_clip_int_enable */
TFA9896_BF_INTENMTPB= 0x2680, /*!< mtp_busy_int_enable */
TFA9896_BF_INTENNOCLK= 0x2690, /*!< flag_lost_clk_int_enable */
TFA9896_BF_INTENSPKS= 0x26a0, /*!< flag_cf_speakererror_int_enable */
TFA9896_BF_INTENACS= 0x26b0, /*!< flag_cold_started_int_enable */
TFA9896_BF_INTENSWS= 0x26c0, /*!< flag_engage_int_enable */
TFA9896_BF_INTENWDS= 0x26d0, /*!< flag_watchdog_reset_int_enable */
TFA9896_BF_INTENAMPS= 0x26e0, /*!< flag_enbl_amp_int_enable */
TFA9896_BF_INTENAREFS= 0x26f0, /*!< flag_enbl_ref_int_enable */
TFA9896_BF_INTENERR= 0x2800, /*!< flag_cfma_err_int_enable */
TFA9896_BF_INTENACK= 0x2810, /*!< flag_cfma_ack_int_enable */
TFA9896_BF_INTPOLVDDS= 0x2900, /*!< flag_por_int_pol */
TFA9896_BF_INTPOLPLLS= 0x2910, /*!< flag_pll_lock_int_pol */
TFA9896_BF_INTPOLOTDS= 0x2920, /*!< flag_otpok_int_pol */
TFA9896_BF_INTPOLOVDS= 0x2930, /*!< flag_ovpok_int_pol */
TFA9896_BF_INTPOLUVDS= 0x2940, /*!< flag_uvpok_int_pol */
TFA9896_BF_INTPOLOCDS= 0x2950, /*!< flag_ocp_alarm_int_pol */
TFA9896_BF_INTPOLCLKS= 0x2960, /*!< flag_clocks_stable_int_pol */
TFA9896_BF_INTPOLCLIPS= 0x2970, /*!< flag_clip_int_pol */
TFA9896_BF_INTPOLMTPB= 0x2980, /*!< mtp_busy_int_pol */
TFA9896_BF_INTPOLNOCLK= 0x2990, /*!< flag_lost_clk_int_pol */
TFA9896_BF_INTPOLSPKS= 0x29a0, /*!< flag_cf_speakererror_int_pol */
TFA9896_BF_INTPOLACS= 0x29b0, /*!< flag_cold_started_int_pol */
TFA9896_BF_INTPOLSWS= 0x29c0, /*!< flag_engage_int_pol */
TFA9896_BF_INTPOLWDS= 0x29d0, /*!< flag_watchdog_reset_int_pol */
TFA9896_BF_INTPOLAMPS= 0x29e0, /*!< flag_enbl_amp_int_pol */
TFA9896_BF_INTPOLAREFS= 0x29f0, /*!< flag_enbl_ref_int_pol */
TFA9896_BF_INTPOLERR= 0x2b00, /*!< flag_cfma_err_int_pol */
TFA9896_BF_INTPOLACK= 0x2b10, /*!< flag_cfma_ack_int_pol */
TFA9896_BF_CLIP = 0x4900, /*!< Bypass clip control */
TFA9896_BF_CIMTP = 0x62b0, /*!< Start copying data from I2C mtp registers to mtp */
TFA9896_BF_RST = 0x7000, /*!< Reset CoolFlux DSP */
TFA9896_BF_DMEM = 0x7011, /*!< Target memory for access */
TFA9896_BF_AIF = 0x7030, /*!< Auto increment flag for memory-address */
TFA9896_BF_CFINT = 0x7040, /*!< CF Interrupt - auto clear */
TFA9896_BF_REQ = 0x7087, /*!< CF request for accessing the 8 channels */
TFA9896_BF_MADD = 0x710f, /*!< Memory address */
TFA9896_BF_MEMA = 0x720f, /*!< Activate memory access */
TFA9896_BF_ERR = 0x7307, /*!< CF error flags */
TFA9896_BF_ACK = 0x7387, /*!< CF acknowledgement of the requests channels */
TFA9896_BF_MTPOTC= 0x8000, /*!< Calibration schedule selection */
TFA9896_BF_MTPEX = 0x8010, /*!< Calibration of RON status bit */
} TFA9896BfEnumList_t;
#define TFA9896_NAMETABLE static tfaBfName_t Tfa9896DatasheetNames[]= {\
{ 0x0, "VDDS"}, /* Power-on-reset flag (auto clear by reading) , */\
{ 0x10, "PLLS"}, /* PLL lock to programmed frequency , */\
{ 0x20, "OTDS"}, /* Over Temperature Protection alarm , */\
{ 0x30, "OVDS"}, /* Over Voltage Protection alarm , */\
{ 0x40, "UVDS"}, /* Under Voltage Protection alarm , */\
{ 0x50, "OCDS"}, /* Over Current Protection alarm , */\
{ 0x60, "CLKS"}, /* Clocks stable flag , */\
{ 0x70, "CLIPS"}, /* Amplifier clipping , */\
{ 0x80, "MTPB"}, /* MTP busy copying data to/from I2C registers , */\
{ 0x90, "NOCLK"}, /* lost clock detection (reference input clock) , */\
{ 0xa0, "SPKS"}, /* Speaker error , */\
{ 0xb0, "ACS"}, /* Cold Start required , */\
{ 0xc0, "SWS"}, /* Amplifier engage (Amp Switching) , */\
{ 0xd0, "WDS"}, /* watchdog reset (activates reset) , */\
{ 0xe0, "AMPS"}, /* Amplifier is enabled by manager , */\
{ 0xf0, "AREFS"}, /* References are enabled by manager , */\
{ 0x109, "BATS"}, /* Battery voltage from ADC readout , */\
{ 0x208, "TEMPS"}, /* Temperature readout from the temperature sensor ( C), */\
{ 0x30f, "REV"}, /* Device revision information , */\
{ 0x420, "RCV"}, /* Enable receiver mode , */\
{ 0x431, "CHS12"}, /* Channel Selection TDM input for Coolflux , */\
{ 0x450, "INPLVL"}, /* Input level selection attenuator ( , */\
{ 0x461, "CHSA"}, /* Input selection for amplifier , */\
{ 0x4c3, "AUDFS"}, /* Audio sample rate setting , */\
{ 0x501, "BSSCR"}, /* Batteery protection attack time , */\
{ 0x523, "BSST"}, /* Battery protection threshold level , */\
{ 0x561, "BSSRL"}, /* Battery protection maximum reduction , */\
{ 0x582, "BSSRR"}, /* Battery protection release time , */\
{ 0x5b1, "BSSHY"}, /* Battery Protection Hysteresis , */\
{ 0x5e0, "BSSR"}, /* Battery voltage value for read out (only) , */\
{ 0x5f0, "BSSBY"}, /* Bypass clipper battery protection , */\
{ 0x600, "DPSA"}, /* Enable dynamic powerstage activation (DPSA) , */\
{ 0x613, "ATTEN"}, /* Gain attenuation setting , */\
{ 0x650, "CFSM"}, /* Soft mute in CoolFlux , */\
{ 0x670, "BSSS"}, /* Battery sense steepness , */\
{ 0x687, "VOL"}, /* Coolflux volume control , */\
{ 0x702, "DCVO2"}, /* Second Boost Voltage , */\
{ 0x733, "DCMCC"}, /* Max boost coil current - step of 175 mA , */\
{ 0x772, "DCVO1"}, /* First Boost Voltage , */\
{ 0x7a0, "DCIE"}, /* Adaptive boost mode , */\
{ 0x7b0, "DCSR"}, /* Soft Rampup/down mode for DCDC controller , */\
{ 0x7c0, "DCPAVG"}, /* ctrl_peak2avg for analog part of DCDC , */\
{ 0x7d0, "DCPWM"}, /* DCDC PWM only mode , */\
{ 0x800, "TROS"}, /* Selection ambient temperature for speaker calibration , */\
{ 0x818, "EXTTS"}, /* External temperature for speaker calibration (C) , */\
{ 0x900, "PWDN"}, /* powerdown selection , */\
{ 0x910, "I2CR"}, /* All I2C registers reset to default , */\
{ 0x920, "CFE"}, /* Enable CoolFlux , */\
{ 0x930, "AMPE"}, /* Enable Amplifier , */\
{ 0x940, "DCA"}, /* Enable DCDC Boost converter , */\
{ 0x950, "SBSL"}, /* Coolflux configured , */\
{ 0x960, "AMPC"}, /* Selection if Coolflux enables amplifier , */\
{ 0x970, "DCDIS"}, /* DCDC boost converter not connected , */\
{ 0x980, "PSDR"}, /* IDDQ amplifier test selection , */\
{ 0x9c1, "INTPAD"}, /* INT pad (interrupt bump output) configuration , */\
{ 0x9e0, "IPLL"}, /* PLL input reference clock selection , */\
{ 0xa04, "DCTRIP"}, /* Adaptive boost trip levels (effective only when boost_intel is set to 1), */\
{ 0xa54, "DCHOLD"}, /* Hold time for DCDC booster (effective only when boost_intel is set to 1), */\
{ 0xb07, "MTPK"}, /* KEY2 to access key2 protected registers (default for engineering), */\
{ 0xc25, "CVFDLY"}, /* Fractional delay adjustment between current and voltage sense, */\
{ 0xec0, "OPENMTP"}, /* Enable programming of the MTP memory , */\
{ 0x1011, "TDMPRF"}, /* TDM usecase selection control , */\
{ 0x1030, "TDMEN"}, /* TDM interface enable , */\
{ 0x1040, "TDMCKINV"}, /* TDM clock inversion, receive on , */\
{ 0x1053, "TDMFSLN"}, /* TDM FS length , */\
{ 0x1090, "TDMFSPOL"}, /* TDM FS polarity (start frame) , */\
{ 0x10a4, "TDMSAMSZ"}, /* TDM sample size for all TDM sinks and sources , */\
{ 0x1103, "TDMSLOTS"}, /* TDM number of slots , */\
{ 0x1144, "TDMSLLN"}, /* TDM slot length , */\
{ 0x1194, "TDMBRMG"}, /* TDM bits remaining after the last slot , */\
{ 0x11e0, "TDMDDEL"}, /* TDM data delay , */\
{ 0x11f0, "TDMDADJ"}, /* TDM data adjustment , */\
{ 0x1201, "TDMTXFRM"}, /* TDM TXDATA format , */\
{ 0x1221, "TDMUUS0"}, /* TDM TXDATA format unused slot SD0 , */\
{ 0x1241, "TDMUUS1"}, /* TDM TXDATA format unused slot SD1 , */\
{ 0x1270, "TDMSI0EN"}, /* TDM sink0 enable , */\
{ 0x1280, "TDMSI1EN"}, /* TDM sink1 enable , */\
{ 0x1290, "TDMSI2EN"}, /* TDM sink2 enable , */\
{ 0x12a0, "TDMSO0EN"}, /* TDM source0 enable , */\
{ 0x12b0, "TDMSO1EN"}, /* TDM source1 enable , */\
{ 0x12c0, "TDMSO2EN"}, /* TDM source2 enable , */\
{ 0x12d0, "TDMSI0IO"}, /* TDM sink0 IO selection , */\
{ 0x12e0, "TDMSI1IO"}, /* TDM sink1 IO selection , */\
{ 0x12f0, "TDMSI2IO"}, /* TDM sink2 IO selection , */\
{ 0x1300, "TDMSO0IO"}, /* TDM source0 IO selection , */\
{ 0x1310, "TDMSO1IO"}, /* TDM source1 IO selection , */\
{ 0x1320, "TDMSO2IO"}, /* TDM source2 IO selection , */\
{ 0x1333, "TDMSI0SL"}, /* TDM sink0 slot position [GAIN IN] , */\
{ 0x1373, "TDMSI1SL"}, /* TDM sink1 slot position [CH1 IN] , */\
{ 0x13b3, "TDMSI2SL"}, /* TDM sink2 slot position [CH2 IN] , */\
{ 0x1403, "TDMSO0SL"}, /* TDM source0 slot position [GAIN OUT] , */\
{ 0x1443, "TDMSO1SL"}, /* TDM source1 slot position [Voltage Sense] , */\
{ 0x1483, "TDMSO2SL"}, /* TDM source2 slot position [Current Sense] , */\
{ 0x14c3, "NBCK"}, /* TDM NBCK bit clock ratio , */\
{ 0x2000, "INTOVDDS"}, /* flag_por_int_out , */\
{ 0x2010, "INTOPLLS"}, /* flag_pll_lock_int_out , */\
{ 0x2020, "INTOOTDS"}, /* flag_otpok_int_out , */\
{ 0x2030, "INTOOVDS"}, /* flag_ovpok_int_out , */\
{ 0x2040, "INTOUVDS"}, /* flag_uvpok_int_out , */\
{ 0x2050, "INTOOCDS"}, /* flag_ocp_alarm_int_out , */\
{ 0x2060, "INTOCLKS"}, /* flag_clocks_stable_int_out , */\
{ 0x2070, "INTOCLIPS"}, /* flag_clip_int_out , */\
{ 0x2080, "INTOMTPB"}, /* mtp_busy_int_out , */\
{ 0x2090, "INTONOCLK"}, /* flag_lost_clk_int_out , */\
{ 0x20a0, "INTOSPKS"}, /* flag_cf_speakererror_int_out , */\
{ 0x20b0, "INTOACS"}, /* flag_cold_started_int_out , */\
{ 0x20c0, "INTOSWS"}, /* flag_engage_int_out , */\
{ 0x20d0, "INTOWDS"}, /* flag_watchdog_reset_int_out , */\
{ 0x20e0, "INTOAMPS"}, /* flag_enbl_amp_int_out , */\
{ 0x20f0, "INTOAREFS"}, /* flag_enbl_ref_int_out , */\
{ 0x2200, "INTOERR"}, /* flag_cfma_err_int_out , */\
{ 0x2210, "INTOACK"}, /* flag_cfma_ack_int_out , */\
{ 0x2300, "INTIVDDS"}, /* flag_por_int_in , */\
{ 0x2310, "INTIPLLS"}, /* flag_pll_lock_int_in , */\
{ 0x2320, "INTIOTDS"}, /* flag_otpok_int_in , */\
{ 0x2330, "INTIOVDS"}, /* flag_ovpok_int_in , */\
{ 0x2340, "INTIUVDS"}, /* flag_uvpok_int_in , */\
{ 0x2350, "INTIOCDS"}, /* flag_ocp_alarm_int_in , */\
{ 0x2360, "INTICLKS"}, /* flag_clocks_stable_int_in , */\
{ 0x2370, "INTICLIPS"}, /* flag_clip_int_in , */\
{ 0x2380, "INTIMTPB"}, /* mtp_busy_int_in , */\
{ 0x2390, "INTINOCLK"}, /* flag_lost_clk_int_in , */\
{ 0x23a0, "INTISPKS"}, /* flag_cf_speakererror_int_in , */\
{ 0x23b0, "INTIACS"}, /* flag_cold_started_int_in , */\
{ 0x23c0, "INTISWS"}, /* flag_engage_int_in , */\
{ 0x23d0, "INTIWDS"}, /* flag_watchdog_reset_int_in , */\
{ 0x23e0, "INTIAMPS"}, /* flag_enbl_amp_int_in , */\
{ 0x23f0, "INTIAREFS"}, /* flag_enbl_ref_int_in , */\
{ 0x2500, "INTIERR"}, /* flag_cfma_err_int_in , */\
{ 0x2510, "INTIACK"}, /* flag_cfma_ack_int_in , */\
{ 0x2600, "INTENVDDS"}, /* flag_por_int_enable , */\
{ 0x2610, "INTENPLLS"}, /* flag_pll_lock_int_enable , */\
{ 0x2620, "INTENOTDS"}, /* flag_otpok_int_enable , */\
{ 0x2630, "INTENOVDS"}, /* flag_ovpok_int_enable , */\
{ 0x2640, "INTENUVDS"}, /* flag_uvpok_int_enable , */\
{ 0x2650, "INTENOCDS"}, /* flag_ocp_alarm_int_enable , */\
{ 0x2660, "INTENCLKS"}, /* flag_clocks_stable_int_enable , */\
{ 0x2670, "INTENCLIPS"}, /* flag_clip_int_enable , */\
{ 0x2680, "INTENMTPB"}, /* mtp_busy_int_enable , */\
{ 0x2690, "INTENNOCLK"}, /* flag_lost_clk_int_enable , */\
{ 0x26a0, "INTENSPKS"}, /* flag_cf_speakererror_int_enable , */\
{ 0x26b0, "INTENACS"}, /* flag_cold_started_int_enable , */\
{ 0x26c0, "INTENSWS"}, /* flag_engage_int_enable , */\
{ 0x26d0, "INTENWDS"}, /* flag_watchdog_reset_int_enable , */\
{ 0x26e0, "INTENAMPS"}, /* flag_enbl_amp_int_enable , */\
{ 0x26f0, "INTENAREFS"}, /* flag_enbl_ref_int_enable , */\
{ 0x2800, "INTENERR"}, /* flag_cfma_err_int_enable , */\
{ 0x2810, "INTENACK"}, /* flag_cfma_ack_int_enable , */\
{ 0x2900, "INTPOLVDDS"}, /* flag_por_int_pol , */\
{ 0x2910, "INTPOLPLLS"}, /* flag_pll_lock_int_pol , */\
{ 0x2920, "INTPOLOTDS"}, /* flag_otpok_int_pol , */\
{ 0x2930, "INTPOLOVDS"}, /* flag_ovpok_int_pol , */\
{ 0x2940, "INTPOLUVDS"}, /* flag_uvpok_int_pol , */\
{ 0x2950, "INTPOLOCDS"}, /* flag_ocp_alarm_int_pol , */\
{ 0x2960, "INTPOLCLKS"}, /* flag_clocks_stable_int_pol , */\
{ 0x2970, "INTPOLCLIPS"}, /* flag_clip_int_pol , */\
{ 0x2980, "INTPOLMTPB"}, /* mtp_busy_int_pol , */\
{ 0x2990, "INTPOLNOCLK"}, /* flag_lost_clk_int_pol , */\
{ 0x29a0, "INTPOLSPKS"}, /* flag_cf_speakererror_int_pol , */\
{ 0x29b0, "INTPOLACS"}, /* flag_cold_started_int_pol , */\
{ 0x29c0, "INTPOLSWS"}, /* flag_engage_int_pol , */\
{ 0x29d0, "INTPOLWDS"}, /* flag_watchdog_reset_int_pol , */\
{ 0x29e0, "INTPOLAMPS"}, /* flag_enbl_amp_int_pol , */\
{ 0x29f0, "INTPOLAREFS"}, /* flag_enbl_ref_int_pol , */\
{ 0x2b00, "INTPOLERR"}, /* flag_cfma_err_int_pol , */\
{ 0x2b10, "INTPOLACK"}, /* flag_cfma_ack_int_pol , */\
{ 0x4900, "CLIP"}, /* Bypass clip control , */\
{ 0x62b0, "CIMTP"}, /* Start copying data from I2C mtp registers to mtp , */\
{ 0x7000, "RST"}, /* Reset CoolFlux DSP , */\
{ 0x7011, "DMEM"}, /* Target memory for access , */\
{ 0x7030, "AIF"}, /* Auto increment flag for memory-address , */\
{ 0x7040, "CFINT"}, /* CF Interrupt - auto clear , */\
{ 0x7087, "REQ"}, /* CF request for accessing the 8 channels , */\
{ 0x710f, "MADD"}, /* Memory address , */\
{ 0x720f, "MEMA"}, /* Activate memory access , */\
{ 0x7307, "ERR"}, /* CF error flags , */\
{ 0x7387, "ACK"}, /* CF acknowledgement of the requests channels , */\
{ 0x8000, "MTPOTC"}, /* Calibration schedule selection , */\
{ 0x8010, "MTPEX"}, /* Calibration of RON status bit , */\
{ 0x8045, "SWPROFIL" },\
{ 0x80a5, "SWVSTEP" },\
{ 0xffff,"Unknown bitfield enum" } /* not found */\
};
#define TFA9896_BITNAMETABLE static tfaBfName_t Tfa9896BitNames[]= {\
{ 0x0, "flag_por"}, /* Power-on-reset flag (auto clear by reading) , */\
{ 0x10, "flag_pll_lock"}, /* PLL lock to programmed frequency , */\
{ 0x20, "flag_otpok"}, /* Over Temperature Protection alarm , */\
{ 0x30, "flag_ovpok"}, /* Over Voltage Protection alarm , */\
{ 0x40, "flag_uvpok"}, /* Under Voltage Protection alarm , */\
{ 0x50, "flag_ocp_alarm"}, /* Over Current Protection alarm , */\
{ 0x60, "flag_clocks_stable"}, /* Clocks stable flag , */\
{ 0x70, "flag_clip"}, /* Amplifier clipping , */\
{ 0x80, "mtp_busy"}, /* MTP busy copying data to/from I2C registers , */\
{ 0x90, "flag_lost_clk"}, /* lost clock detection (reference input clock) , */\
{ 0xa0, "flag_cf_speakererror"}, /* Speaker error , */\
{ 0xb0, "flag_cold_started"}, /* Cold Start required , */\
{ 0xc0, "flag_engage"}, /* Amplifier engage (Amp Switching) , */\
{ 0xd0, "flag_watchdog_reset"}, /* watchdog reset (activates reset) , */\
{ 0xe0, "flag_enbl_amp"}, /* Amplifier is enabled by manager , */\
{ 0xf0, "flag_enbl_ref"}, /* References are enabled by manager , */\
{ 0x109, "bat_adc"}, /* Battery voltage from ADC readout , */\
{ 0x208, "temp_adc"}, /* Temperature readout from the temperature sensor ( C), */\
{ 0x30f, "device_rev"}, /* Device revision information , */\
{ 0x420, "ctrl_rcv"}, /* Enable receiver mode , */\
{ 0x431, "chan_sel"}, /* Channel Selection TDM input for Coolflux , */\
{ 0x450, "input_level"}, /* Input level selection attenuator ( , */\
{ 0x461, "vamp_sel"}, /* Input selection for amplifier , */\
{ 0x4c3, "audio_fs"}, /* Audio sample rate setting , */\
{ 0x501, "vbat_prot_attacktime"}, /* Batteery protection attack time , */\
{ 0x523, "vbat_prot_thlevel"}, /* Battery protection threshold level , */\
{ 0x561, "vbat_prot_max_reduct"}, /* Battery protection maximum reduction , */\
{ 0x582, "vbat_prot_release_t"}, /* Battery protection release time , */\
{ 0x5b1, "vbat_prot_hysterese"}, /* Battery Protection Hysteresis , */\
{ 0x5d0, "reset_min_vbat"}, /* Battery supply safeguard clipper reset ( if CF_DSP is bypassed), */\
{ 0x5e0, "sel_vbat"}, /* Battery voltage value for read out (only) , */\
{ 0x5f0, "bypass_clipper"}, /* Bypass clipper battery protection , */\
{ 0x600, "dpsa"}, /* Enable dynamic powerstage activation (DPSA) , */\
{ 0x613, "ctrl_att"}, /* Gain attenuation setting , */\
{ 0x650, "cf_mute"}, /* Soft mute in CoolFlux , */\
{ 0x670, "batsense_steepness"}, /* Battery sense steepness , */\
{ 0x687, "vol"}, /* Coolflux volume control , */\
{ 0x702, "scnd_boost_voltage"}, /* Second Boost Voltage , */\
{ 0x733, "boost_cur"}, /* Max boost coil current - step of 175 mA , */\
{ 0x772, "frst_boost_voltage"}, /* First Boost Voltage , */\
{ 0x7a0, "boost_intel"}, /* Adaptive boost mode , */\
{ 0x7b0, "boost_speed"}, /* Soft Rampup/down mode for DCDC controller , */\
{ 0x7c0, "boost_peak2avg"}, /* ctrl_peak2avg for analog part of DCDC , */\
{ 0x7d0, "dcdc_pwmonly"}, /* DCDC PWM only mode , */\
{ 0x7e0, "ignore_flag_voutcomp86"}, /* Ignore flag_voutcomp86 (flag from analog) , */\
{ 0x800, "ext_temp_sel"}, /* Selection ambient temperature for speaker calibration , */\
{ 0x818, "ext_temp"}, /* External temperature for speaker calibration (C) , */\
{ 0x900, "powerdown"}, /* powerdown selection , */\
{ 0x910, "reset"}, /* All I2C registers reset to default , */\
{ 0x920, "enbl_coolflux"}, /* Enable CoolFlux , */\
{ 0x930, "enbl_amplifier"}, /* Enable Amplifier , */\
{ 0x940, "enbl_boost"}, /* Enable DCDC Boost converter , */\
{ 0x950, "coolflux_configured"}, /* Coolflux configured , */\
{ 0x960, "sel_enbl_amplifier"}, /* Selection if Coolflux enables amplifier , */\
{ 0x970, "dcdcoff_mode"}, /* DCDC boost converter not connected , */\
{ 0x980, "iddqtest"}, /* IDDQ amplifier test selection , */\
{ 0x9c1, "int_pad_io"}, /* INT pad (interrupt bump output) configuration , */\
{ 0x9e0, "sel_fs_bck"}, /* PLL input reference clock selection , */\
{ 0x9f0, "sel_scl_cf_clock"}, /* Coolflux sub-system clock selection , */\
{ 0xa04, "boost_trip_lvl"}, /* Adaptive boost trip levels (effective only when boost_intel is set to 1), */\
{ 0xa54, "boost_hold_time"}, /* Hold time for DCDC booster (effective only when boost_intel is set to 1), */\
{ 0xaa1, "bst_slpcmplvl"}, /* Slope compensation current, represents LxF (inductance x frequency) value , */\
{ 0xb07, "mtpkey2"}, /* KEY2 to access key2 protected registers (default for engineering), */\
{ 0xc00, "enbl_volt_sense"}, /* Voltage sense enabling control bit , */\
{ 0xc10, "vsense_pwm_sel"}, /* Voltage sense source selection , */\
{ 0xc25, "vi_frac_delay"}, /* Fractional delay adjustment between current and voltage sense, */\
{ 0xc80, "sel_voltsense_out"}, /* TDM output data selection for AEC , */\
{ 0xc90, "vsense_bypass_avg"}, /* Voltage sense average block bypass , */\
{ 0xd05, "cf_frac_delay"}, /* Fractional delay adjustment between current and voltage sense by firmware, */\
{ 0xe00, "bypass_dcdc_curr_prot"}, /* Control to switch off dcdc current reduction with bat protection, */\
{ 0xe10, "bypass_ocp"}, /* Bypass OCP (digital IP block) , */\
{ 0xe20, "ocptest"}, /* ocptest (analog IP block) enable , */\
{ 0xe80, "disable_clock_sh_prot"}, /* Disable clock_sh protection , */\
{ 0xe92, "reserve_reg_15_09"}, /* Spare control bits for future usage , */\
{ 0xec0, "unprotect_mtp"}, /* Enable programming of the MTP memory , */\
{ 0xed2, "reserve_reg_15_13"}, /* Spare control bits for future usage , */\
{ 0xf00, "dcdc_pfm20khz_limit"}, /* DCDC in PFM mode forcing each 50us a pwm pulse , */\
{ 0xf11, "dcdc_ctrl_maxzercnt"}, /* DCDC number of zero current flags required to go to pfm mode, */\
{ 0xf36, "dcdc_vbat_delta_detect"}, /* DCDC threshold required on a delta Vbat (in PFM mode) switching to PWM mode, */\
{ 0xfa0, "dcdc_ignore_vbat"}, /* Ignore an increase on Vbat , */\
{ 0x1011, "tdm_usecase"}, /* TDM usecase selection control , */\
{ 0x1030, "tdm_enable"}, /* TDM interface enable , */\
{ 0x1040, "tdm_clk_inversion"}, /* TDM clock inversion, receive on , */\
{ 0x1053, "tdm_fs_ws_length"}, /* TDM FS length , */\
{ 0x1090, "tdm_fs_ws_polarity"}, /* TDM FS polarity (start frame) , */\
{ 0x10a4, "tdm_sample_size"}, /* TDM sample size for all TDM sinks and sources , */\
{ 0x1103, "tdm_nb_of_slots"}, /* TDM number of slots , */\
{ 0x1144, "tdm_slot_length"}, /* TDM slot length , */\
{ 0x1194, "tdm_bits_remaining"}, /* TDM bits remaining after the last slot , */\
{ 0x11e0, "tdm_data_delay"}, /* TDM data delay , */\
{ 0x11f0, "tdm_data_adjustment"}, /* TDM data adjustment , */\
{ 0x1201, "tdm_txdata_format"}, /* TDM TXDATA format , */\
{ 0x1221, "tdm_txdata_format_unused_slot_sd0"}, /* TDM TXDATA format unused slot SD0 , */\
{ 0x1241, "tdm_txdata_format_unused_slot_sd1"}, /* TDM TXDATA format unused slot SD1 , */\
{ 0x1270, "tdm_sink0_enable"}, /* TDM sink0 enable , */\
{ 0x1280, "tdm_sink1_enable"}, /* TDM sink1 enable , */\
{ 0x1290, "tdm_sink2_enable"}, /* TDM sink2 enable , */\
{ 0x12a0, "tdm_source0_enable"}, /* TDM source0 enable , */\
{ 0x12b0, "tdm_source1_enable"}, /* TDM source1 enable , */\
{ 0x12c0, "tdm_source2_enable"}, /* TDM source2 enable , */\
{ 0x12d0, "tdm_sink0_io"}, /* TDM sink0 IO selection , */\
{ 0x12e0, "tdm_sink1_io"}, /* TDM sink1 IO selection , */\
{ 0x12f0, "tdm_sink2_io"}, /* TDM sink2 IO selection , */\
{ 0x1300, "tdm_source0_io"}, /* TDM source0 IO selection , */\
{ 0x1310, "tdm_source1_io"}, /* TDM source1 IO selection , */\
{ 0x1320, "tdm_source2_io"}, /* TDM source2 IO selection , */\
{ 0x1333, "tdm_sink0_slot"}, /* TDM sink0 slot position [GAIN IN] , */\
{ 0x1373, "tdm_sink1_slot"}, /* TDM sink1 slot position [CH1 IN] , */\
{ 0x13b3, "tdm_sink2_slot"}, /* TDM sink2 slot position [CH2 IN] , */\
{ 0x1403, "tdm_source0_slot"}, /* TDM source0 slot position [GAIN OUT] , */\
{ 0x1443, "tdm_source1_slot"}, /* TDM source1 slot position [Voltage Sense] , */\
{ 0x1483, "tdm_source2_slot"}, /* TDM source2 slot position [Current Sense] , */\
{ 0x14c3, "tdm_nbck"}, /* TDM NBCK bit clock ratio , */\
{ 0x1500, "flag_tdm_lut_error"}, /* TDM LUT error flag , */\
{ 0x1512, "flag_tdm_status"}, /* TDM interface status bits , */\
{ 0x1540, "flag_tdm_error"}, /* TDM interface error indicator , */\
{ 0x1551, "status_bst_mode"}, /* DCDC mode status bits , */\
{ 0x2000, "flag_por_int_out"}, /* flag_por_int_out , */\
{ 0x2010, "flag_pll_lock_int_out"}, /* flag_pll_lock_int_out , */\
{ 0x2020, "flag_otpok_int_out"}, /* flag_otpok_int_out , */\
{ 0x2030, "flag_ovpok_int_out"}, /* flag_ovpok_int_out , */\
{ 0x2040, "flag_uvpok_int_out"}, /* flag_uvpok_int_out , */\
{ 0x2050, "flag_ocp_alarm_int_out"}, /* flag_ocp_alarm_int_out , */\
{ 0x2060, "flag_clocks_stable_int_out"}, /* flag_clocks_stable_int_out , */\
{ 0x2070, "flag_clip_int_out"}, /* flag_clip_int_out , */\
{ 0x2080, "mtp_busy_int_out"}, /* mtp_busy_int_out , */\
{ 0x2090, "flag_lost_clk_int_out"}, /* flag_lost_clk_int_out , */\
{ 0x20a0, "flag_cf_speakererror_int_out"}, /* flag_cf_speakererror_int_out , */\
{ 0x20b0, "flag_cold_started_int_out"}, /* flag_cold_started_int_out , */\
{ 0x20c0, "flag_engage_int_out"}, /* flag_engage_int_out , */\
{ 0x20d0, "flag_watchdog_reset_int_out"}, /* flag_watchdog_reset_int_out , */\
{ 0x20e0, "flag_enbl_amp_int_out"}, /* flag_enbl_amp_int_out , */\
{ 0x20f0, "flag_enbl_ref_int_out"}, /* flag_enbl_ref_int_out , */\
{ 0x2100, "flag_voutcomp_int_out"}, /* flag_voutcomp_int_out , */\
{ 0x2110, "flag_voutcomp93_int_out"}, /* flag_voutcomp93_int_out , */\
{ 0x2120, "flag_voutcomp86_int_out"}, /* flag_voutcomp86_int_out , */\
{ 0x2130, "flag_hiz_int_out"}, /* flag_hiz_int_out , */\
{ 0x2140, "flag_ocpokbst_int_out"}, /* flag_ocpokbst_int_out , */\
{ 0x2150, "flag_peakcur_int_out"}, /* flag_peakcur_int_out , */\
{ 0x2160, "flag_ocpokap_int_out"}, /* flag_ocpokap_int_out , */\
{ 0x2170, "flag_ocpokan_int_out"}, /* flag_ocpokan_int_out , */\
{ 0x2180, "flag_ocpokbp_int_out"}, /* flag_ocpokbp_int_out , */\
{ 0x2190, "flag_ocpokbn_int_out"}, /* flag_ocpokbn_int_out , */\
{ 0x21a0, "flag_adc10_ready_int_out"}, /* flag_adc10_ready_int_out , */\
{ 0x21b0, "flag_clipa_high_int_out"}, /* flag_clipa_high_int_out , */\
{ 0x21c0, "flag_clipa_low_int_out"}, /* flag_clipa_low_int_out , */\
{ 0x21d0, "flag_clipb_high_int_out"}, /* flag_clipb_high_int_out , */\
{ 0x21e0, "flag_clipb_low_int_out"}, /* flag_clipb_low_int_out , */\
{ 0x21f0, "flag_tdm_error_int_out"}, /* flag_tdm_error_int_out , */\
{ 0x2200, "flag_cfma_err_int_out"}, /* flag_cfma_err_int_out , */\
{ 0x2210, "flag_cfma_ack_int_out"}, /* flag_cfma_ack_int_out , */\
{ 0x2300, "flag_por_int_in"}, /* flag_por_int_in , */\
{ 0x2310, "flag_pll_lock_int_in"}, /* flag_pll_lock_int_in , */\
{ 0x2320, "flag_otpok_int_in"}, /* flag_otpok_int_in , */\
{ 0x2330, "flag_ovpok_int_in"}, /* flag_ovpok_int_in , */\
{ 0x2340, "flag_uvpok_int_in"}, /* flag_uvpok_int_in , */\
{ 0x2350, "flag_ocp_alarm_int_in"}, /* flag_ocp_alarm_int_in , */\
{ 0x2360, "flag_clocks_stable_int_in"}, /* flag_clocks_stable_int_in , */\
{ 0x2370, "flag_clip_int_in"}, /* flag_clip_int_in , */\
{ 0x2380, "mtp_busy_int_in"}, /* mtp_busy_int_in , */\
{ 0x2390, "flag_lost_clk_int_in"}, /* flag_lost_clk_int_in , */\
{ 0x23a0, "flag_cf_speakererror_int_in"}, /* flag_cf_speakererror_int_in , */\
{ 0x23b0, "flag_cold_started_int_in"}, /* flag_cold_started_int_in , */\
{ 0x23c0, "flag_engage_int_in"}, /* flag_engage_int_in , */\
{ 0x23d0, "flag_watchdog_reset_int_in"}, /* flag_watchdog_reset_int_in , */\
{ 0x23e0, "flag_enbl_amp_int_in"}, /* flag_enbl_amp_int_in , */\
{ 0x23f0, "flag_enbl_ref_int_in"}, /* flag_enbl_ref_int_in , */\
{ 0x2400, "flag_voutcomp_int_in"}, /* flag_voutcomp_int_in , */\
{ 0x2410, "flag_voutcomp93_int_in"}, /* flag_voutcomp93_int_in , */\
{ 0x2420, "flag_voutcomp86_int_in"}, /* flag_voutcomp86_int_in , */\
{ 0x2430, "flag_hiz_int_in"}, /* flag_hiz_int_in , */\
{ 0x2440, "flag_ocpokbst_int_in"}, /* flag_ocpokbst_int_in , */\
{ 0x2450, "flag_peakcur_int_in"}, /* flag_peakcur_int_in , */\
{ 0x2460, "flag_ocpokap_int_in"}, /* flag_ocpokap_int_in , */\
{ 0x2470, "flag_ocpokan_int_in"}, /* flag_ocpokan_int_in , */\
{ 0x2480, "flag_ocpokbp_int_in"}, /* flag_ocpokbp_int_in , */\
{ 0x2490, "flag_ocpokbn_int_in"}, /* flag_ocpokbn_int_in , */\
{ 0x24a0, "flag_adc10_ready_int_in"}, /* flag_adc10_ready_int_in , */\
{ 0x24b0, "flag_clipa_high_int_in"}, /* flag_clipa_high_int_in , */\
{ 0x24c0, "flag_clipa_low_int_in"}, /* flag_clipa_low_int_in , */\
{ 0x24d0, "flag_clipb_high_int_in"}, /* flag_clipb_high_int_in , */\
{ 0x24e0, "flag_clipb_low_int_in"}, /* flag_clipb_low_int_in , */\
{ 0x24f0, "flag_tdm_error_int_in"}, /* flag_tdm_error_int_in , */\
{ 0x2500, "flag_cfma_err_int_in"}, /* flag_cfma_err_int_in , */\
{ 0x2510, "flag_cfma_ack_int_in"}, /* flag_cfma_ack_int_in , */\
{ 0x2600, "flag_por_int_enable"}, /* flag_por_int_enable , */\
{ 0x2610, "flag_pll_lock_int_enable"}, /* flag_pll_lock_int_enable , */\
{ 0x2620, "flag_otpok_int_enable"}, /* flag_otpok_int_enable , */\
{ 0x2630, "flag_ovpok_int_enable"}, /* flag_ovpok_int_enable , */\
{ 0x2640, "flag_uvpok_int_enable"}, /* flag_uvpok_int_enable , */\
{ 0x2650, "flag_ocp_alarm_int_enable"}, /* flag_ocp_alarm_int_enable , */\
{ 0x2660, "flag_clocks_stable_int_enable"}, /* flag_clocks_stable_int_enable , */\
{ 0x2670, "flag_clip_int_enable"}, /* flag_clip_int_enable , */\
{ 0x2680, "mtp_busy_int_enable"}, /* mtp_busy_int_enable , */\
{ 0x2690, "flag_lost_clk_int_enable"}, /* flag_lost_clk_int_enable , */\
{ 0x26a0, "flag_cf_speakererror_int_enable"}, /* flag_cf_speakererror_int_enable , */\
{ 0x26b0, "flag_cold_started_int_enable"}, /* flag_cold_started_int_enable , */\
{ 0x26c0, "flag_engage_int_enable"}, /* flag_engage_int_enable , */\
{ 0x26d0, "flag_watchdog_reset_int_enable"}, /* flag_watchdog_reset_int_enable , */\
{ 0x26e0, "flag_enbl_amp_int_enable"}, /* flag_enbl_amp_int_enable , */\
{ 0x26f0, "flag_enbl_ref_int_enable"}, /* flag_enbl_ref_int_enable , */\
{ 0x2700, "flag_voutcomp_int_enable"}, /* flag_voutcomp_int_enable , */\
{ 0x2710, "flag_voutcomp93_int_enable"}, /* flag_voutcomp93_int_enable , */\
{ 0x2720, "flag_voutcomp86_int_enable"}, /* flag_voutcomp86_int_enable , */\
{ 0x2730, "flag_hiz_int_enable"}, /* flag_hiz_int_enable , */\
{ 0x2740, "flag_ocpokbst_int_enable"}, /* flag_ocpokbst_int_enable , */\
{ 0x2750, "flag_peakcur_int_enable"}, /* flag_peakcur_int_enable , */\
{ 0x2760, "flag_ocpokap_int_enable"}, /* flag_ocpokap_int_enable , */\
{ 0x2770, "flag_ocpokan_int_enable"}, /* flag_ocpokan_int_enable , */\
{ 0x2780, "flag_ocpokbp_int_enable"}, /* flag_ocpokbp_int_enable , */\
{ 0x2790, "flag_ocpokbn_int_enable"}, /* flag_ocpokbn_int_enable , */\
{ 0x27a0, "flag_adc10_ready_int_enable"}, /* flag_adc10_ready_int_enable , */\
{ 0x27b0, "flag_clipa_high_int_enable"}, /* flag_clipa_high_int_enable , */\
{ 0x27c0, "flag_clipa_low_int_enable"}, /* flag_clipa_low_int_enable , */\
{ 0x27d0, "flag_clipb_high_int_enable"}, /* flag_clipb_high_int_enable , */\
{ 0x27e0, "flag_clipb_low_int_enable"}, /* flag_clipb_low_int_enable , */\
{ 0x27f0, "flag_tdm_error_int_enable"}, /* flag_tdm_error_int_enable , */\
{ 0x2800, "flag_cfma_err_int_enable"}, /* flag_cfma_err_int_enable , */\
{ 0x2810, "flag_cfma_ack_int_enable"}, /* flag_cfma_ack_int_enable , */\
{ 0x2900, "flag_por_int_pol"}, /* flag_por_int_pol , */\
{ 0x2910, "flag_pll_lock_int_pol"}, /* flag_pll_lock_int_pol , */\
{ 0x2920, "flag_otpok_int_pol"}, /* flag_otpok_int_pol , */\
{ 0x2930, "flag_ovpok_int_pol"}, /* flag_ovpok_int_pol , */\
{ 0x2940, "flag_uvpok_int_pol"}, /* flag_uvpok_int_pol , */\
{ 0x2950, "flag_ocp_alarm_int_pol"}, /* flag_ocp_alarm_int_pol , */\
{ 0x2960, "flag_clocks_stable_int_pol"}, /* flag_clocks_stable_int_pol , */\
{ 0x2970, "flag_clip_int_pol"}, /* flag_clip_int_pol , */\
{ 0x2980, "mtp_busy_int_pol"}, /* mtp_busy_int_pol , */\
{ 0x2990, "flag_lost_clk_int_pol"}, /* flag_lost_clk_int_pol , */\
{ 0x29a0, "flag_cf_speakererror_int_pol"}, /* flag_cf_speakererror_int_pol , */\
{ 0x29b0, "flag_cold_started_int_pol"}, /* flag_cold_started_int_pol , */\
{ 0x29c0, "flag_engage_int_pol"}, /* flag_engage_int_pol , */\
{ 0x29d0, "flag_watchdog_reset_int_pol"}, /* flag_watchdog_reset_int_pol , */\
{ 0x29e0, "flag_enbl_amp_int_pol"}, /* flag_enbl_amp_int_pol , */\
{ 0x29f0, "flag_enbl_ref_int_pol"}, /* flag_enbl_ref_int_pol , */\
{ 0x2a00, "flag_voutcomp_int_pol"}, /* flag_voutcomp_int_pol , */\
{ 0x2a10, "flag_voutcomp93_int_pol"}, /* flag_voutcomp93_int_pol , */\
{ 0x2a20, "flag_voutcomp86_int_pol"}, /* flag_voutcomp86_int_pol , */\
{ 0x2a30, "flag_hiz_int_pol"}, /* flag_hiz_int_pol , */\
{ 0x2a40, "flag_ocpokbst_int_pol"}, /* flag_ocpokbst_int_pol , */\
{ 0x2a50, "flag_peakcur_int_pol"}, /* flag_peakcur_int_pol , */\
{ 0x2a60, "flag_ocpokap_int_pol"}, /* flag_ocpokap_int_pol , */\
{ 0x2a70, "flag_ocpokan_int_pol"}, /* flag_ocpokan_int_pol , */\
{ 0x2a80, "flag_ocpokbp_int_pol"}, /* flag_ocpokbp_int_pol , */\
{ 0x2a90, "flag_ocpokbn_int_pol"}, /* flag_ocpokbn_int_pol , */\
{ 0x2aa0, "flag_adc10_ready_int_pol"}, /* flag_adc10_ready_int_pol , */\
{ 0x2ab0, "flag_clipa_high_int_pol"}, /* flag_clipa_high_int_pol , */\
{ 0x2ac0, "flag_clipa_low_int_pol"}, /* flag_clipa_low_int_pol , */\
{ 0x2ad0, "flag_clipb_high_int_pol"}, /* flag_clipb_high_int_pol , */\
{ 0x2ae0, "flag_clipb_low_int_pol"}, /* flag_clipb_low_int_pol , */\
{ 0x2af0, "flag_tdm_error_int_pol"}, /* flag_tdm_error_int_pol , */\
{ 0x2b00, "flag_cfma_err_int_pol"}, /* flag_cfma_err_int_pol , */\
{ 0x2b10, "flag_cfma_ack_int_pol"}, /* flag_cfma_ack_int_pol , */\
{ 0x3000, "flag_voutcomp"}, /* Status flag_voutcomp, indication Vset is larger than Vbat, */\
{ 0x3010, "flag_voutcomp93"}, /* Status flag_voutcomp93, indication Vset is larger than 1.07 x Vbat, */\
{ 0x3020, "flag_voutcomp86"}, /* Status flag voutcomp86, indication Vset is larger than 1.14 x Vbat, */\
{ 0x3030, "flag_hiz"}, /* Status flag_hiz, indication Vbst is larger than Vbat, */\
{ 0x3040, "flag_ocpokbst"}, /* Status flag_ocpokbst, indication no over current in boost converter PMOS switch, */\
{ 0x3050, "flag_peakcur"}, /* Status flag_peakcur, indication current is max in dcdc converter, */\
{ 0x3060, "flag_ocpokap"}, /* Status flag_ocpokap, indication no over current in amplifier A PMOS output stage, */\
{ 0x3070, "flag_ocpokan"}, /* Status flag_ocpokan, indication no over current in amplifier A NMOS output stage, */\
{ 0x3080, "flag_ocpokbp"}, /* Status flag_ocpokbp, indication no over current in amplifier B PMOS output stage, */\
{ 0x3090, "flag_ocpokbn"}, /* Status flag_ocpokbn, indication no over current in amplifier B NMOS output stage, */\
{ 0x30a0, "flag_adc10_ready"}, /* Status flag_adc10_ready, indication adc10 is ready, */\
{ 0x30b0, "flag_clipa_high"}, /* Status flag_clipa_high, indication pmos amplifier A is clipping, */\
{ 0x30c0, "flag_clipa_low"}, /* Status flag_clipa_low, indication nmos amplifier A is clipping, */\
{ 0x30d0, "flag_clipb_high"}, /* Status flag_clipb_high, indication pmos amplifier B is clipping, */\
{ 0x30e0, "flag_clipb_low"}, /* Status flag_clipb_low, indication nmos amplifier B is clipping, */\
{ 0x310f, "mtp_man_data_out"}, /* MTP manual read out data , */\
{ 0x3200, "key01_locked"}, /* Indicates KEY1 is locked , */\
{ 0x3210, "key02_locked"}, /* Indicates KEY2 is locked , */\
{ 0x3225, "mtp_ecc_tcout"}, /* MTP error correction test data out , */\
{ 0x3280, "mtpctrl_valid_test_rd"}, /* MTP test readout for read , */\
{ 0x3290, "mtpctrl_valid_test_wr"}, /* MTP test readout for write , */\
{ 0x32a0, "flag_in_alarm_state"}, /* Flag alarm state , */\
{ 0x32b0, "mtp_ecc_err2"}, /* Two or more bit errors detected in MTP, can not reconstruct value, */\
{ 0x32c0, "mtp_ecc_err1"}, /* One bit error detected in MTP, reconstructed value, */\
{ 0x32d0, "mtp_mtp_hvf"}, /* High voltage ready flag for MTP , */\
{ 0x32f0, "mtp_zero_check_fail"}, /* Zero check failed for MTP , */\
{ 0x3309, "data_adc10_tempbat"}, /* ADC10 data output for testing battery voltage and temperature, */\
{ 0x400f, "hid_code"}, /* 5A6Bh, 23147d to access hidden registers (default for engineering), */\
{ 0x4100, "bypass_hp"}, /* Bypass High Pass Filter , */\
{ 0x4110, "hard_mute"}, /* Hard Mute , */\
{ 0x4120, "soft_mute"}, /* Soft Mute , */\
{ 0x4134, "pwm_delay"}, /* PWM delay setting , */\
{ 0x4180, "pwm_shape"}, /* PWM Shape , */\
{ 0x4190, "pwm_bitlength"}, /* PWM Bitlength in noise shaper , */\
{ 0x4203, "drive"}, /* Drive bits to select number of amplifier power stages, */\
{ 0x4240, "reclock_pwm"}, /* Control for enabling reclocking of PWM signal , */\
{ 0x4250, "reclock_voltsense"}, /* Control for enabling reclocking of voltage sense signal, */\
{ 0x4281, "dpsalevel"}, /* DPSA threshold level , */\
{ 0x42a1, "dpsa_release"}, /* DPSA release time , */\
{ 0x42c0, "coincidence"}, /* Prevent simultaneously switching of output stage , */\
{ 0x42d0, "kickback"}, /* Prevent double pulses of output stage , */\
{ 0x4306, "drivebst"}, /* Drive bits to select the power transistor sections boost converter, */\
{ 0x4370, "boost_alg"}, /* Control for boost adaptive loop gain , */\
{ 0x4381, "boost_loopgain"}, /* DCDC boost loopgain setting , */\
{ 0x43a0, "ocptestbst"}, /* Boost OCP. For old ocp (ctrl_reversebst is 0); For new ocp (ctrl_reversebst is 1), */\
{ 0x43d0, "test_abistfft_enbl"}, /* FFT Coolflux , */\
{ 0x43e0, "bst_dcmbst"}, /* DCM mode control for DCDC during I2C direct control mode, */\
{ 0x43f0, "test_bcontrol"}, /* test_bcontrol , */\
{ 0x4400, "reversebst"}, /* OverCurrent Protection selection of power stage boost converter, */\
{ 0x4410, "sensetest"}, /* Test option for the sense NMOS in booster for current mode control., */\
{ 0x4420, "enbl_engagebst"}, /* Enable power stage of dcdc controller , */\
{ 0x4470, "enbl_slopecur"}, /* Enable bit of max-current dac , */\
{ 0x4480, "enbl_voutcomp"}, /* Enable vout comparators , */\
{ 0x4490, "enbl_voutcomp93"}, /* Enable vout-93 comparators , */\
{ 0x44a0, "enbl_voutcomp86"}, /* Enable vout-86 comparators , */\
{ 0x44b0, "enbl_hizcom"}, /* Enable hiz comparator , */\
{ 0x44c0, "enbl_peakcur"}, /* Enable peak current , */\
{ 0x44d0, "bypass_ovpglitch"}, /* Bypass OVP Glitch Filter , */\
{ 0x44e0, "enbl_windac"}, /* Enable window dac , */\
{ 0x44f0, "enbl_powerbst"}, /* Enable line of the powerstage , */\
{ 0x4507, "ocp_thr"}, /* OCP threshold level , */\
{ 0x4580, "bypass_glitchfilter"}, /* Bypass glitch filter , */\
{ 0x4590, "bypass_ovp"}, /* Bypass OVP , */\
{ 0x45a0, "bypass_uvp"}, /* Bypass UVP , */\
{ 0x45b0, "bypass_otp"}, /* Bypass OTP , */\
{ 0x45d0, "bypass_ocpcounter"}, /* Bypass OCP counter , */\
{ 0x45e0, "bypass_lost_clk"}, /* Bypass lost clock detector , */\
{ 0x45f0, "vpalarm"}, /* vpalarm (UVP/OUP handling) , */\
{ 0x4600, "bypass_gc"}, /* Bypasses the CS gain correction , */\
{ 0x4610, "cs_gain_control"}, /* Current sense gain control , */\
{ 0x4627, "cs_gain"}, /* Current sense gain , */\
{ 0x46a0, "bypass_lp"}, /* Bypass the low power filter inside temperature sensor, */\
{ 0x46b0, "bypass_pwmcounter"}, /* Bypass PWM Counter , */\
{ 0x46c0, "cs_negfixed"}, /* Current sense does not switch to neg , */\
{ 0x46d2, "cs_neghyst"}, /* Current sense switches to neg depending on hyseteris level, */\
{ 0x4700, "switch_fb"}, /* Current sense control switch_fb , */\
{ 0x4713, "se_hyst"}, /* Current sense control se_hyst , */\
{ 0x4754, "se_level"}, /* Current sense control se_level , */\
{ 0x47a5, "ktemp"}, /* Current sense control temperature compensation trimming, */\
{ 0x4800, "cs_negin"}, /* Current sense control negin , */\
{ 0x4810, "cs_sein"}, /* Current sense control cs_sein , */\
{ 0x4820, "cs_coincidence"}, /* Coincidence current sense , */\
{ 0x4830, "iddqtestbst"}, /* IDDQ testing in powerstage of DCDC boost converter, */\
{ 0x4840, "coincidencebst"}, /* Switch protection on to prevent simultaneously switching power stages bst and amp, */\
{ 0x4876, "delay_se_neg"}, /* delay of se and neg , */\
{ 0x48e1, "cs_ttrack"}, /* Sample and hold track time , */\
{ 0x4900, "bypass_clip"}, /* Bypass clip control , */\
{ 0x4920, "cf_cgate_off"}, /* Disable clock gating in the coolflux , */\
{ 0x4940, "clipfast"}, /* Clock selection for HW clipper for battery safeguard, */\
{ 0x4950, "cs_8ohm"}, /* 8 ohm mode for current sense (gain mode) , */\
{ 0x4974, "delay_clock_sh"}, /* delay_sh, tunes S7H delay , */\
{ 0x49c0, "inv_clksh"}, /* Invert the sample/hold clock for current sense ADC, */\
{ 0x49d0, "inv_neg"}, /* Invert neg signal , */\
{ 0x49e0, "inv_se"}, /* Invert se signal , */\
{ 0x49f0, "setse"}, /* Switches between Single Ended and differential mode; 1 is single ended, */\
{ 0x4a12, "adc10_sel"}, /* Select the input to convert the 10b ADC , */\
{ 0x4a60, "adc10_reset"}, /* Reset for ADC10 - I2C direct control mode , */\
{ 0x4a81, "adc10_test"}, /* Test mode selection signal for ADC10 - I2C direct control mode, */\
{ 0x4aa0, "bypass_lp_vbat"}, /* LP filter in batt sensor , */\
{ 0x4ae0, "dc_offset"}, /* Current sense decimator offset control , */\
{ 0x4af0, "tsense_hibias"}, /* Bit to set the biasing in temp sensor to high , */\
{ 0x4b00, "adc13_iset"}, /* MICADC setting of current consumption (debug use only), */\
{ 0x4b14, "adc13_gain"}, /* MICADC gain setting (two's complement format) , */\
{ 0x4b61, "adc13_slowdel"}, /* MICADC delay setting for internal clock (debug use only), */\
{ 0x4b83, "adc13_offset"}, /* MICADC offset setting , */\
{ 0x4bc0, "adc13_bsoinv"}, /* MICADC bit stream output invert mode for test , */\
{ 0x4bd0, "adc13_resonator_enable"}, /* MICADC give extra SNR with less stability (debug use only), */\
{ 0x4be0, "testmicadc"}, /* Mux at input of MICADC for test purpose , */\
{ 0x4c0f, "abist_offset"}, /* Offset control for ABIST testing , */\
{ 0x4d05, "windac"}, /* For testing direct control windac , */\
{ 0x4dc3, "pwm_dcc_cnt"}, /* control pwm duty cycle when enbl_pwm_dcc is 1 , */\
{ 0x4e04, "slopecur"}, /* For testing direct control slopecur , */\
{ 0x4e50, "ctrl_dem"}, /* Dynamic element matching control, rest of codes are optional, */\
{ 0x4ed0, "enbl_pwm_dcc"}, /* Enable direct control of pwm duty cycle , */\
{ 0x4f00, "bst_bypass_bstcur"}, /* Bypass control for boost current settings , */\
{ 0x4f10, "bst_bypass_bstfoldback"}, /* Bypass control for boost foldback , */\
{ 0x4f20, "bst_ctrl_azbst"}, /* Control of auto-zeroing of zero current comparator, */\
{ 0x5007, "gain"}, /* Gain setting of the gain multiplier , */\
{ 0x5081, "sourceb"}, /* PWM OUTB selection control , */\
{ 0x50a1, "sourcea"}, /* PWM OUTA selection control , */\
{ 0x50c1, "sourcebst"}, /* Sets the source of the pwmbst output to boost converter input for testing, */\
{ 0x50e0, "tdm_enable_loopback"}, /* TDM loopback test , */\
{ 0x5104, "pulselengthbst"}, /* Pulse length setting test input for boost converter, */\
{ 0x5150, "bypasslatchbst"}, /* Bypass latch in boost converter , */\
{ 0x5160, "invertbst"}, /* Invert pwmbst test signal , */\
{ 0x5174, "pulselength"}, /* Pulse length setting test input for amplifier , */\
{ 0x51c0, "bypasslatch"}, /* Bypass latch in PWM source selection module , */\
{ 0x51d0, "invertb"}, /* invert pwmb test signal , */\
{ 0x51e0, "inverta"}, /* invert pwma test signal , */\
{ 0x51f0, "bypass_ctrlloop"}, /* bypass_ctrlloop bypasses the control loop of the amplifier, */\
{ 0x5210, "test_rdsona"}, /* tbd for rdson testing , */\
{ 0x5220, "test_rdsonb"}, /* tbd for rdson testing , */\
{ 0x5230, "test_rdsonbst"}, /* tbd for rdson testing , */\
{ 0x5240, "test_cvia"}, /* tbd for rdson testing , */\
{ 0x5250, "test_cvib"}, /* tbd for rdson testing , */\
{ 0x5260, "test_cvibst"}, /* tbd for rdson testing , */\
{ 0x5306, "digimuxa_sel"}, /* DigimuxA input selection control (see Digimux list for details), */\
{ 0x5376, "digimuxb_sel"}, /* DigimuxB input selection control (see Digimux list for details), */\
{ 0x5400, "hs_mode"}, /* I2C high speed mode selection control , */\
{ 0x5412, "test_parametric_io"}, /* Control for parametric tests of IO cells , */\
{ 0x5440, "enbl_ringo"}, /* Enable ring oscillator control, for test purpose to check with ringo, */\
{ 0x5456, "digimuxc_sel"}, /* DigimuxC input selection control (see Digimux list for details), */\
{ 0x54c0, "dio_ehs"}, /* Slew control for DIO in output mode , */\
{ 0x54d0, "gainio_ehs"}, /* Slew control for GAINIO in output mode , */\
{ 0x550d, "enbl_amp"}, /* enbl_amp for testing to enable all analoge blocks in amplifier, */\
{ 0x5600, "use_direct_ctrls"}, /* Use direct controls to overrule several functions for testing - I2C direct control mode, */\
{ 0x5610, "rst_datapath"}, /* Reset datapath during direct control mode , */\
{ 0x5620, "rst_cgu"}, /* Reset CGU during durect control mode , */\
{ 0x5637, "enbl_ref"}, /* For testing to enable all analoge blocks in references, */\
{ 0x56b0, "enbl_engage"}, /* Enable output stage amplifier , */\
{ 0x56c0, "use_direct_clk_ctrl"}, /* use_direct_clk_ctrl, to overrule several functions direct for testing, */\
{ 0x56d0, "use_direct_pll_ctrl"}, /* use_direct_pll_ctrl, to overrule several functions direct for testing, */\
{ 0x5707, "anamux"}, /* Anamux control , */\
{ 0x57e0, "otptest"}, /* otptest, test mode otp amplifier , */\
{ 0x57f0, "reverse"}, /* 1b = Normal mode, slope is controlled , */\
{ 0x5813, "pll_selr"}, /* PLL pll_selr , */\
{ 0x5854, "pll_selp"}, /* PLL pll_selp , */\
{ 0x58a5, "pll_seli"}, /* PLL pll_seli , */\
{ 0x5950, "pll_mdec_msb"}, /* Most significant bits of pll_mdec[16] , */\
{ 0x5960, "pll_ndec_msb"}, /* Most significant bits of pll_ndec[9] , */\
{ 0x5970, "pll_frm"}, /* PLL pll_frm , */\
{ 0x5980, "pll_directi"}, /* PLL pll_directi , */\
{ 0x5990, "pll_directo"}, /* PLL pll_directo , */\
{ 0x59a0, "enbl_pll"}, /* PLL enbl_pll , */\
{ 0x59f0, "pll_bypass"}, /* PLL bypass , */\
{ 0x5a0f, "tsig_freq"}, /* Internal sinus test generator frequency control LSB bits, */\
{ 0x5b02, "tsig_freq_msb"}, /* Select internal sine wave generator, frequency control MSB bits, */\
{ 0x5b30, "inject_tsig"}, /* Control bit to switch to internal sinus test generator, */\
{ 0x5b44, "adc10_prog_sample"}, /* ADC10 program sample setting - I2C direct control mode, */\
{ 0x5c0f, "pll_mdec"}, /* PLL MDEC - I2C direct PLL control mode only , */\
{ 0x5d06, "pll_pdec"}, /* PLL PDEC - I2C direct PLL control mode only , */\
{ 0x5d78, "pll_ndec"}, /* PLL NDEC - I2C direct PLL control mode only , */\
{ 0x6007, "mtpkey1"}, /* 5Ah, 90d To access KEY1_Protected registers (Default for engineering), */\
{ 0x6185, "mtp_ecc_tcin"}, /* MTP ECC TCIN data , */\
{ 0x6203, "mtp_man_address_in"}, /* MTP address from I2C register for read/writing mtp in manual single word mode, */\
{ 0x6260, "mtp_ecc_eeb"}, /* Enable code bit generation (active low!) , */\
{ 0x6270, "mtp_ecc_ecb"}, /* Enable correction signal (active low!) , */\
{ 0x6280, "man_copy_mtp_to_iic"}, /* Start copying single word from mtp to I2C mtp register, */\
{ 0x6290, "man_copy_iic_to_mtp"}, /* Start copying single word from I2C mtp register to mtp, */\
{ 0x62a0, "auto_copy_mtp_to_iic"}, /* Start copying all the data from mtp to I2C mtp registers, */\
{ 0x62b0, "auto_copy_iic_to_mtp"}, /* Start copying data from I2C mtp registers to mtp , */\
{ 0x62d2, "mtp_speed_mode"}, /* MTP speed mode , */\
{ 0x6340, "mtp_direct_enable"}, /* mtp_direct_enable , */\
{ 0x6350, "mtp_direct_wr"}, /* mtp_direct_wr , */\
{ 0x6360, "mtp_direct_rd"}, /* mtp_direct_rd , */\
{ 0x6370, "mtp_direct_rst"}, /* mtp_direct_rst , */\
{ 0x6380, "mtp_direct_ers"}, /* mtp_direct_ers , */\
{ 0x6390, "mtp_direct_prg"}, /* mtp_direct_prg , */\
{ 0x63a0, "mtp_direct_epp"}, /* mtp_direct_epp , */\
{ 0x63b4, "mtp_direct_test"}, /* mtp_direct_test , */\
{ 0x640f, "mtp_man_data_in"}, /* Write data for MTP manual write , */\
{ 0x7000, "cf_rst_dsp"}, /* Reset CoolFlux DSP , */\
{ 0x7011, "cf_dmem"}, /* Target memory for access , */\
{ 0x7030, "cf_aif"}, /* Auto increment flag for memory-address , */\
{ 0x7040, "cf_int"}, /* CF Interrupt - auto clear , */\
{ 0x7087, "cf_req"}, /* CF request for accessing the 8 channels , */\
{ 0x710f, "cf_madd"}, /* Memory address , */\
{ 0x720f, "cf_mema"}, /* Activate memory access , */\
{ 0x7307, "cf_err"}, /* CF error flags , */\
{ 0x7387, "cf_ack"}, /* CF acknowledgement of the requests channels , */\
{ 0x8000, "calibration_onetime"}, /* Calibration schedule selection , */\
{ 0x8010, "calibr_ron_done"}, /* Calibration of RON status bit , */\
{ 0x8105, "calibr_vout_offset"}, /* calibr_vout_offset (DCDCoffset) 2's compliment (key1 protected), */\
{ 0x8163, "calibr_delta_gain"}, /* delta gain for vamp (alpha) 2's compliment (key1 protected), */\
{ 0x81a5, "calibr_offs_amp"}, /* offset for vamp (Ampoffset) 2's compliment (key1 protected), */\
{ 0x8207, "calibr_gain_cs"}, /* gain current sense (Imeasalpha) 2's compliment (key1 protected), */\
{ 0x8284, "calibr_temp_offset"}, /* temperature offset 2's compliment (key1 protected), */\
{ 0x82d2, "calibr_temp_gain"}, /* temperature gain 2's compliment (key1 protected) , */\
{ 0x830f, "calibr_ron"}, /* calibration value of the RON resistance of the coil, */\
{ 0x8505, "type_bits_hw"}, /* bit0 = disable function dcdcoff_mode ($09[7]) , */\
{ 0x8601, "type_bits_1_0_sw"}, /* MTP control SW , */\
{ 0x8681, "type_bits_9_8_sw"}, /* MTP control SW , */\
{ 0x870f, "type_bits2_sw"}, /* MTP-control SW2 , */\
{ 0x8806, "htol_iic_addr"}, /* 7-bit I2C address to be used during HTOL testing , */\
{ 0x8870, "htol_iic_addr_en"}, /* HTOL I2C_Address_Enable , */\
{ 0x8881, "ctrl_ovp_response"}, /* OVP response control , */\
{ 0x88a0, "disable_ovp_alarm_state"}, /* OVP alarm state control , */\
{ 0x88b0, "enbl_stretch_ovp"}, /* OVP alram strech control , */\
{ 0x88c0, "cf_debug_mode"}, /* Coolflux debug mode , */\
{ 0x8a0f, "production_data1"}, /* production_data1 , */\
{ 0x8b0f, "production_data2"}, /* production_data2 , */\
{ 0x8c0f, "production_data3"}, /* production_data3 , */\
{ 0x8d0f, "production_data4"}, /* production_data4 , */\
{ 0x8e0f, "production_data5"}, /* production_data5 , */\
{ 0x8f0f, "production_data6"}, /* production_data6 , */\
{ 0xffff,"Unknown bitfield enum" } /* not found */\
};
enum TFA9896_irq {
TFA9896_irq_vdds = 0,
TFA9896_irq_plls = 1,
TFA9896_irq_ds = 2,
TFA9896_irq_vds = 3,
TFA9896_irq_uvds = 4,
TFA9896_irq_cds = 5,
TFA9896_irq_clks = 6,
TFA9896_irq_clips = 7,
TFA9896_irq_mtpb = 8,
TFA9896_irq_clk = 9,
TFA9896_irq_spks = 10,
TFA9896_irq_acs = 11,
TFA9896_irq_sws = 12,
TFA9896_irq_wds = 13,
TFA9896_irq_amps = 14,
TFA9896_irq_arefs = 15,
TFA9896_irq_err = 32,
TFA9896_irq_ack = 33,
TFA9896_irq_max = 34,
TFA9896_irq_all = -1 /* all irqs */};
#define TFA9896_IRQ_NAMETABLE static tfaIrqName_t TFA9896IrqNames[]= {\
{ 0, "VDDS"},\
{ 1, "PLLS"},\
{ 2, "DS"},\
{ 3, "VDS"},\
{ 4, "UVDS"},\
{ 5, "CDS"},\
{ 6, "CLKS"},\
{ 7, "CLIPS"},\
{ 8, "MTPB"},\
{ 9, "CLK"},\
{ 10, "SPKS"},\
{ 11, "ACS"},\
{ 12, "SWS"},\
{ 13, "WDS"},\
{ 14, "AMPS"},\
{ 15, "AREFS"},\
{ 16, "16"},\
{ 17, "17"},\
{ 18, "18"},\
{ 19, "19"},\
{ 20, "20"},\
{ 21, "21"},\
{ 22, "22"},\
{ 23, "23"},\
{ 24, "24"},\
{ 25, "25"},\
{ 26, "26"},\
{ 27, "27"},\
{ 28, "28"},\
{ 29, "29"},\
{ 30, "30"},\
{ 31, "31"},\
{ 32, "ERR"},\
{ 33, "ACK"},\
{ 34, "34"},\
};
#endif /* _TFA9896_TFAFIELDNAMES_H */

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/*
* Copyright (C) 2014-2020 NXP Semiconductors, All Rights Reserved.
* Copyright 2020 GOODIX
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
*/
#ifndef __TFA98XX_INC__
#define __TFA98XX_INC__
#include <linux/kernel.h>
#include <linux/types.h>
#include <linux/list.h>
#include <linux/miscdevice.h>
#include "tfa_device.h"
#include "tfa_container.h"
#include "config.h"
/* max. length of a alsa mixer control name */
#define MAX_CONTROL_NAME 48
#define TFA98XX_MAX_REGISTER 0xff
#define TFA98XX_FLAG_SKIP_INTERRUPTS (1 << 0)
#define TFA98XX_FLAG_SAAM_AVAILABLE (1 << 1)
#define TFA98XX_FLAG_STEREO_DEVICE (1 << 2)
#define TFA98XX_FLAG_MULTI_MIC_INPUTS (1 << 3)
#define TFA98XX_FLAG_TAPDET_AVAILABLE (1 << 4)
#define TFA98XX_FLAG_CALIBRATION_CTL (1 << 5)
#define TFA98XX_FLAG_REMOVE_PLOP_NOISE (1 << 6)
#define TFA98XX_FLAG_LP_MODES (1 << 7)
#define TFA98XX_FLAG_TDM_DEVICE (1 << 8)
#define TFA98XX_FLAG_ADAPT_NOISE_MODE (1 << 9)
#define TFA98XX_NUM_RATES 10
/* DSP init status */
enum tfa98xx_dsp_init_state {
TFA98XX_DSP_INIT_STOPPED, /* DSP not running */
TFA98XX_DSP_INIT_RECOVER, /* DSP error detected at runtime */
TFA98XX_DSP_INIT_FAIL, /* DSP init failed */
TFA98XX_DSP_INIT_PENDING, /* DSP start requested */
TFA98XX_DSP_INIT_DONE, /* DSP running */
TFA98XX_DSP_INIT_INVALIDATED, /* DSP was running, requires re-init */
};
enum tfa98xx_dsp_fw_state {
TFA98XX_DSP_FW_NONE = 0,
TFA98XX_DSP_FW_PENDING,
TFA98XX_DSP_FW_FAIL,
TFA98XX_DSP_FW_OK,
};
enum tfa98xx_misc_device_id {
MISC_DEVICE_TFA98XX_REG,
MISC_DEVICE_TFA98XX_RW,
MISC_DEVICE_TFA98XX_RPC,
MISC_DEVICE_TFA98XX_PROFILE,
MISC_DEVICE_TFA98XX_IOCTL,
MISC_DEVICE_MAX
};
struct tfa98xx_miscdevice_info {
char devicename[255];
struct file_operations operations;
};
enum TFA_DEVICE_MUTE{
TFA98XX_DEVICE_MUTE_OFF = 0,
TFA98XX_DEVICE_MUTE_ON,
};
enum {
IOCTL_CMD_GET_MEMTRACK_DATA = 0,
IOCTL_CMD_GET_CNT_VERSION,
};
enum {
TFA_KCONTROL_VALUE_DISABLED = 0,
TFA_KCONTROL_VALUE_ENABLED
};
struct livedata_cfg {
int address;
int track;
int scaler;
};
struct tfa98xx_firmware {
void *base;
struct tfa98xx_device *dev;
char name[9]; //TODO get length from tfa parameter defs
};
struct tfa98xx_baseprofile {
char basename[MAX_CONTROL_NAME]; /* profile basename */
int len; /* profile length */
int item_id; /* profile id */
int sr_rate_sup[TFA98XX_NUM_RATES]; /* sample rates supported by this profile */
struct list_head list; /* list of all profiles */
};
enum tfa_reset_polarity{
LOW=0,
HIGH=1
};
struct tfa98xx {
struct regmap *regmap;
struct i2c_client *i2c;
struct regulator *vdd;
#if LINUX_VERSION_CODE >= KERNEL_VERSION(4,18,0)
struct snd_soc_component *codec;
#else
struct snd_soc_codec *codec;
#endif
struct workqueue_struct *tfa98xx_wq;
struct delayed_work init_work;
struct delayed_work monitor_work;
struct delayed_work interrupt_work;
struct delayed_work tapdet_work;
struct delayed_work nmodeupdate_work;
struct mutex dsp_lock;
int dsp_init;
int dsp_fw_state;
int sysclk;
int rst_gpio;
u16 rev;
int audio_mode;
struct tfa98xx_firmware fw;
char *fw_name;
int rate;
wait_queue_head_t wq;
struct device *dev;
unsigned int init_count;
int pstream;
int cstream;
struct input_dev *input;
bool tapdet_enabled; /* service enabled */
bool tapdet_open; /* device file opened */
unsigned int tapdet_profiles; /* tapdet profile bitfield */
bool tapdet_poll; /* tapdet running on polling mode */
unsigned int rate_constraint_list[TFA98XX_NUM_RATES];
struct snd_pcm_hw_constraint_list rate_constraint;
int reset_gpio;
int power_gpio;
int irq_gpio;
int spk_sw_gpio;
enum tfa_reset_polarity reset_polarity;
struct list_head list;
struct tfa_device *tfa;
int vstep;
int profile;
int prof_vsteps[TFACONT_MAXPROFS]; /* store vstep per profile (single device) */
#ifdef CONFIG_DEBUG_FS
struct dentry *dbg_dir;
#endif
u8 reg;
unsigned int flags;
bool set_mtp_cal;
uint16_t cal_data;
enum TFA_DEVICE_MUTE tfa_mute_mode;
struct device_node *spk_id_gpio_p;
struct miscdevice tfa98xx_reg;
struct miscdevice tfa98xx_rw;
struct miscdevice tfa98xx_rpc;
struct miscdevice tfa98xx_profile;
struct miscdevice tfa98xx_control;
};
/*for furture, we will move it to DTS to mark left and right channel*/
#define TFA_LEFT_DEVICE_ADDRESS (0x34)
#define TFA_RIGHT_DEVICE_ADDRESS (0x35)
#endif /* __TFA98XX_INC__ */

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/*
* Copyright (C) 2014-2020 NXP Semiconductors, All Rights Reserved.
* Copyright 2020 GOODIX
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
*/
/*
* tfa98xx_parameters.h
*
* Created on: Jul 22, 2013
* Author: NLV02095
*/
#ifndef TFA98XXPARAMETERS_H_
#define TFA98XXPARAMETERS_H_
//#include "config.h"
// workaround for Visual Studio:
// fatal error C1083: Cannot open include file: 'config.h': No such file or directory
#ifdef __KERNEL__
#include <linux/types.h>
#else
#include <stdint.h>
#endif
#include "tfa_service.h"
#if (defined(WIN32) || defined(_X64))
/* These warnings are disabled because it is only given by Windows and there is no easy fix */
#pragma warning(disable:4200)
#pragma warning(disable:4214)
#endif
/*
* profiles & volumesteps
*
*/
#define TFA_MAX_PROFILES (64)
#define TFA_MAX_VSTEPS (64)
#define TFA_MAX_VSTEP_MSG_MARKER (100) /* This marker is used to indicate if all msgs need to be written to the device */
#define TFA_MAX_MSGS (10)
// the pack pragma is required to make that the size in memory
// matches the actual variable lenghts
// This is to assure that the binary files can be transported between
// different platforms.
#pragma pack (push, 1)
/*
* typedef for 24 bit value using 3 bytes
*/
typedef struct uint24 {
uint8_t b[3];
} uint24_t;
/*
* the generic header
* all char types are in ASCII
*/
typedef struct TfaHeader {
uint16_t id;
char version[2]; // "V_" : V=version, vv=subversion
char subversion[2]; // "vv" : vv=subversion
uint16_t size; // data size in bytes following CRC
uint32_t CRC; // 32-bits CRC for following data
char customer[8]; // “name of customer”
char application[8]; // “application name”
char type[8]; // “application type name”
} TfaHeader_t;
typedef enum TfaSamplerate {
fs_8k, // 8kHz
fs_11k025, // 11.025kHz
fs_12k, // 12kHz
fs_16k, // 16kHz
fs_22k05, // 22.05kHz
fs_24k, // 24kHz
fs_32k, // 32kHz
fs_44k1, // 44.1kHz
fs_48k, // 48kHz
fs_96k, // 96kHz
fs_count // Should always be last item.
} TfaSamplerate_t;
// Keep in sync with TfaSamplerate_t !
static const int TfaSamplerateHz[fs_count] = { 8000, 11025, 12000, 16000, 22050, 24000, 32000, 44100, 48000, 96000 };
/*
* coolflux direct memory access
*/
typedef struct TfaDspMem {
uint8_t type; /* 0--3: p, x, y, iomem */
uint16_t address; /* target address */
uint8_t size; /* data size in words */
int words[]; /* payload in signed 32bit integer (two's complement) */
} TfaDspMem_t;
/*
* the biquad coefficients for the API together with index in filter
* the biquad_index is the actual index in the equalizer +1
*/
#define BIQUAD_COEFF_SIZE 6
/*
* Output fixed point coeffs structure
*/
typedef struct {
int a2;
int a1;
int b2;
int b1;
int b0;
}TfaBiquad_t;
typedef struct TfaBiquadOld {
uint8_t bytes[BIQUAD_COEFF_SIZE*sizeof(uint24_t)];
}TfaBiquadOld_t;
typedef struct TfaBiquadFloat {
float headroom;
float b0;
float b1;
float b2;
float a1;
float a2;
} TfaBiquadFloat_t;
/*
* EQ filter definitions
* Note: This is not in line with smartstudio (JV: 12/12/2016)
*/
typedef enum TfaFilterType {
fCustom, //User defined biquad coefficients
fFlat, //Vary only gain
fLowpass, //2nd order Butterworth low pass
fHighpass, //2nd order Butterworth high pass
fLowshelf,
fHighshelf,
fNotch,
fPeak,
fBandpass,
f1stLP,
f1stHP,
fElliptic
} TfaFilterType_t;
/*
* filter parameters for biquad (re-)calculation
*/
typedef struct TfaFilter {
TfaBiquadOld_t biquad;
uint8_t enabled;
uint8_t type; // (== enum FilterTypes, assure 8bits length)
float frequency;
float Q;
float gain;
} TfaFilter_t ; //8 * float + int32 + byte == 37
/*
* biquad params for calculation
*/
#define TFA_BQ_EQ_INDEX 0
#define TFA_BQ_ANTI_ALIAS_INDEX 10
#define TFA_BQ_INTEGRATOR_INDEX 13
/*
* Loudspeaker Compensation filter definitions
*/
typedef struct TfaLsCompensationFilter {
TfaBiquad_t biquad;
uint8_t lsCompOn; // Loudspeaker compensation on/off; when 'off', the DSP code doesn't apply the bwExt => bwExtOn GUI flag should be gray to avoid confusion
uint8_t bwExtOn; // Bandwidth extension on/off
float fRes; // [Hz] speaker resonance frequency
float Qt; // Speaker resonance Q-factor
float fBwExt; // [Hz] Band width extension frequency
float samplingFreq;// [Hz] Sampling frequency
} TfaLsCompensationFilter_t;
/*
* Anti Aliasing Elliptic filter definitions
*/
typedef struct TfaAntiAliasFilter {
TfaBiquad_t biquad; /**< Output results fixed point coeffs */
uint8_t enabled;
float cutOffFreq; // cut off frequency
float samplingFreq; // sampling frequency
float rippleDb; // range: [0.1 3.0]
float rolloff; // range: [-1.0 1.0]
} TfaAntiAliasFilter_t;
/**
* Integrator filter input definitions
*/
typedef struct TfaIntegratorFilter {
TfaBiquad_t biquad; /**< Output results fixed point coeffs */
uint8_t type; /**< Butterworth filter type: high or low pass */
float cutOffFreq; /**< cut off frequency in Hertz; range: [100.0 4000.0] */
float samplingFreq; /**< sampling frequency in Hertz */
float leakage; /**< leakage factor; range [0.0 1.0] */
} TfaIntegratorFilter_t;
typedef struct TfaEqFilter {
TfaBiquad_t biquad;
uint8_t enabled;
uint8_t type; // (== enum FilterTypes, assure 8bits length)
float cutOffFreq; // cut off frequency, // range: [100.0 4000.0]
float samplingFreq; // sampling frequency
float Q; // range: [0.5 5.0]
float gainDb; // range: [-10.0 10.0]
} TfaEqFilter_t ; //8 * float + int32 + byte == 37
typedef struct TfaContAntiAlias {
int8_t index; /**< index determines destination type; anti-alias, integrator,eq */
uint8_t type;
float cutOffFreq; // cut off frequency
float samplingFreq;
float rippleDb; // integrator leakage
float rolloff;
uint8_t bytes[5*3]; // payload 5*24buts coeffs
}TfaContAntiAlias_t;
typedef struct TfaContIntegrator {
int8_t index; /**< index determines destination type; anti-alias, integrator,eq */
uint8_t type;
float cutOffFreq; // cut off frequency
float samplingFreq;
float leakage; // integrator leakage
float reserved;
uint8_t bytes[5*3]; // payload 5*24buts coeffs
}TfaContIntegrator_t;
typedef struct TfaContEq {
int8_t index;
uint8_t type; // (== enum FilterTypes, assure 8bits length)
float cutOffFreq; // cut off frequency, // range: [100.0 4000.0]
float samplingFreq; // sampling frequency
float Q; // range: [0.5 5.0]
float gainDb; // range: [-10.0 10.0]
uint8_t bytes[5*3]; // payload 5*24buts coeffs
} TfaContEq_t ; //8 * float + int32 + byte == 37
typedef union TfaContBiquad {
TfaContEq_t eq;
TfaContAntiAlias_t aa;
TfaContIntegrator_t in;
}TfaContBiquad_t;
#define TFA_BQ_EQ_INDEX 0
#define TFA_BQ_ANTI_ALIAS_INDEX 10
#define TFA_BQ_INTEGRATOR_INDEX 13
#define TFA98XX_MAX_EQ 10
typedef struct TfaEqualizer {
TfaFilter_t filter[TFA98XX_MAX_EQ];
} TfaEqualizer_t;
/*
* files
*/
#define HDR(c1,c2) (c2<<8|c1) // little endian
typedef enum TfaHeaderType {
paramsHdr = HDR('P','M'), /* containter file */
volstepHdr = HDR('V','P'),
patchHdr = HDR('P','A'),
speakerHdr = HDR('S','P'),
presetHdr = HDR('P','R'),
configHdr = HDR('C','O'),
equalizerHdr = HDR('E','Q'),
drcHdr = HDR('D','R'),
msgHdr = HDR('M','G'), /* generic message */
infoHdr = HDR('I','N')
} TfaHeaderType_t;
/*
* equalizer file
*/
#define TFA_EQ_VERSION '1'
#define TFA_EQ_SUBVERSION "00"
typedef struct TfaEqualizerFile {
TfaHeader_t hdr;
uint8_t samplerate; // ==enum samplerates, assure 8 bits
TfaFilter_t filter[TFA98XX_MAX_EQ];// note: API index counts from 1..10
} TfaEqualizerFile_t;
/*
* patch file
*/
#define TFA_PA_VERSION '1'
#define TFA_PA_SUBVERSION "00"
typedef struct TfaPatchFile {
TfaHeader_t hdr;
uint8_t data[];
} TfaPatch_t;
/*
* generic message file
* - the payload of this file includes the opcode and is send straight to the DSP
*/
#define TFA_MG_VERSION '3'
#define TFA_MG_SUBVERSION "00"
typedef struct TfaMsgFile {
TfaHeader_t hdr;
uint8_t data[];
} TfaMsgFile_t;
/*
* NOTE the tfa98xx API defines the enum Tfa98xx_config_type that defines
* the subtypes as decribes below.
* tfa98xx_dsp_config_parameter_type() can be used to get the
* supported type for the active device..
*/
/*
* config file V1 sub 1
*/
#define TFA_CO_VERSION '1'
#define TFA_CO3_VERSION '3'
#define TFA_CO_SUBVERSION1 "01"
typedef struct TfaConfigS1File {
TfaHeader_t hdr;
uint8_t data[55*3];
} TfaConfigS1_t;
/*
* config file V1 sub 2
*/
#define TFA_CO_SUBVERSION2 "02"
typedef struct TfaConfigS2File {
TfaHeader_t hdr;
uint8_t data[67*3];
} TfaConfigS2_t;
/*
* config file V1 sub 3
*/
#define TFA_CO_SUBVERSION3 "03"
typedef struct TfaConfigS3File {
TfaHeader_t hdr;
uint8_t data[67*3];
} TfaConfigS3_t;
/*
* config file V1.0
*/
#define TFA_CO_SUBVERSION "00"
typedef struct TfaConfigFile {
TfaHeader_t hdr;
uint8_t data[];
} TfaConfig_t;
/*
* preset file
*/
#define TFA_PR_VERSION '1'
#define TFA_PR_SUBVERSION "00"
typedef struct TfaPresetFile {
TfaHeader_t hdr;
uint8_t data[];
} TfaPreset_t;
/*
* drc file
*/
#define TFA_DR_VERSION '1'
#define TFA_DR_SUBVERSION "00"
typedef struct TfaDrcFile {
TfaHeader_t hdr;
uint8_t data[];
} TfaDrc_t;
/*
* drc file
* for tfa 2 there is also a xml-version
*/
#define TFA_DR3_VERSION '3'
#define TFA_DR3_SUBVERSION "00"
typedef struct TfaDrcFile2 {
TfaHeader_t hdr;
uint8_t version[3];
uint8_t data[];
} TfaDrc2_t;
/*
* volume step structures
*/
// VP01
#define TFA_VP1_VERSION '1'
#define TFA_VP1_SUBVERSION "01"
typedef struct TfaVolumeStep1 {
float attenuation; // IEEE single float
uint8_t preset[TFA98XX_PRESET_LENGTH];
} TfaVolumeStep1_t;
// VP02
#define TFA_VP2_VERSION '2'
#define TFA_VP2_SUBVERSION "01"
typedef struct TfaVolumeStep2 {
float attenuation; // IEEE single float
uint8_t preset[TFA98XX_PRESET_LENGTH];
TfaFilter_t filter[TFA98XX_MAX_EQ];// note: API index counts from 1..10
} TfaVolumeStep2_t;
/*
* volumestep file
*/
#define TFA_VP_VERSION '1'
#define TFA_VP_SUBVERSION "00"
typedef struct TfaVolumeStepFile {
TfaHeader_t hdr;
uint8_t vsteps; // can also be calulated from size+type
uint8_t samplerate; // ==enum samplerates, assure 8 bits
uint8_t payload; //start of variable length contents:N times volsteps
}TfaVolumeStepFile_t;
/*
* volumestep2 file
*/
typedef struct TfaVolumeStep2File {
TfaHeader_t hdr;
uint8_t vsteps; // can also be calulated from size+type
uint8_t samplerate; // ==enum samplerates, assure 8 bits
TfaVolumeStep2_t vstep[]; //start of variable length contents:N times volsteps
}TfaVolumeStep2File_t;
/*
* volumestepMax2 file
*/
typedef struct TfaVolumeStepMax2File {
TfaHeader_t hdr;
uint8_t version[3];
uint8_t NrOfVsteps;
uint8_t vstepsBin[];
}TfaVolumeStepMax2File_t;
/*
* volumestepMax2 file
* This volumestep should ONLY be used for the use of bin2hdr!
* This can only be used to find the messagetype of the vstep (without header)
*/
typedef struct TfaVolumeStepMax2_1File {
uint8_t version[3];
uint8_t NrOfVsteps;
uint8_t vstepsBin[];
}TfaVolumeStepMax2_1File_t;
struct TfaVolumeStepRegisterInfo {
uint8_t NrOfRegisters;
uint16_t registerInfo[];
};
struct TfaVolumeStepMessageInfo {
uint8_t NrOfMessages;
uint8_t MessageType;
uint24_t MessageLength;
uint8_t CmdId[3];
uint8_t ParameterData[];
};
/**************************old v2 *************************************************/
/*
* subv 00 volumestep file
*/
typedef struct TfaOldHeader {
uint16_t id;
char version[2]; // "V_" : V=version, vv=subversion
char subversion[2]; // "vv" : vv=subversion
uint16_t size; // data size in bytes following CRC
uint32_t CRC; // 32-bits CRC for following data
} TfaOldHeader_t;
typedef struct TfaOldFilter {
double bq[5];
int32_t type;
double frequency;
double Q;
double gain;
uint8_t enabled;
} TfaOldFilter_t ;
typedef struct TfaOldVolumeStep2 {
float attenuation; // IEEE single float
uint8_t preset[TFA98XX_PRESET_LENGTH];
TfaOldFilter_t eq[10];
} TfaOldVolumeStep2_t;
typedef struct TfaOldVolumeStepFile {
TfaOldHeader_t hdr;
TfaOldVolumeStep2_t step[];
}TfaOldVolumeStep2File_t;
/**************************end old v2 *************************************************/
/*
* speaker file header
*/
struct TfaSpkHeader {
struct TfaHeader hdr;
char name[8]; // speaker nick name (e.g. “dumbo”)
char vendor[16];
char type[8];
// dimensions (mm)
uint8_t height;
uint8_t width;
uint8_t depth;
uint16_t ohm;
};
/*
* speaker file
*/
#define TFA_SP_VERSION '1'
#define TFA_SP_SUBVERSION "00"
typedef struct TfaSpeakerFile {
TfaHeader_t hdr;
char name[8]; // speaker nick name (e.g. “dumbo”)
char vendor[16];
char type[8];
// dimensions (mm)
uint8_t height;
uint8_t width;
uint8_t depth;
uint8_t ohm_primary;
uint8_t ohm_secondary;
uint8_t data[]; //payload TFA98XX_SPEAKERPARAMETER_LENGTH
} TfaSpeakerFile_t;
#define TFA_VP3_VERSION '3'
#define TFA_VP3_SUBVERSION "00"
struct TfaFWVer {
uint8_t Major;
uint8_t minor;
uint8_t minor_update:6;
uint8_t Update:2;
};
struct TfaFWMsg {
struct TfaFWVer fwVersion;
struct TfaMsg payload;
};
typedef struct TfaLiveData {
char name[25];
char addrs[25];
int tracker;
int scalefactor;
} TfaLiveData_t;
#define TFA_SP3_VERSION '3'
#define TFA_SP3_SUBVERSION "00"
struct TfaSpeakerFileMax2 {
TfaHeader_t hdr;
char name[8]; // speaker nick name (e.g. “dumbo”)
char vendor[16];
char type[8];
// dimensions (mm)
uint8_t height;
uint8_t width;
uint8_t depth;
uint8_t ohm_primary;
uint8_t ohm_secondary;
struct TfaFWMsg FWmsg; //payload including FW ver and Cmd ID
};
/*
* parameter container file
*/
/*
* descriptors
* Note 1: append new DescriptorType at the end
* Note 2: add new descriptors to dsc_name[] in tfaContUtil.c
*/
typedef enum TfaDescriptorType {
dscDevice, // device list
dscProfile, // profile list
dscRegister, // register patch
dscString, // ascii, zero terminated string
dscFile, // filename + file contents
dscPatch, // patch file
dscMarker, // marker to indicate end of a list
dscMode,
dscSetInputSelect,
dscSetOutputSelect,
dscSetProgramConfig,
dscSetLagW,
dscSetGains,
dscSetvBatFactors,
dscSetSensesCal,
dscSetSensesDelay,
dscBitfield,
dscDefault, // used to reset bitfields to there default values
dscLiveData,
dscLiveDataString,
dscGroup,
dscCmd,
dscSetMBDrc,
dscFilter,
dscNoInit,
dscFeatures,
dscCfMem, // coolflux memory x,y,io
dscSetFwkUseCase,
dscSetVddpConfig,
dsc_last // trailer
} TfaDescriptorType_t;
#define TFA_BITFIELDDSCMSK 0x7fffffff
typedef struct TfaDescPtr {
uint32_t offset:24;
uint32_t type:8; // (== enum TfaDescriptorType, assure 8bits length)
}TfaDescPtr_t;
/*
* generic file descriptor
*/
typedef struct TfaFileDsc {
TfaDescPtr_t name;
uint32_t size; // file data length in bytes
uint8_t data[]; //payload
} TfaFileDsc_t;
/*
* device descriptor list
*/
typedef struct TfaDeviceList {
uint8_t length; // nr of items in the list
uint8_t bus; // bus
uint8_t dev; // device
uint8_t func; // subfunction or subdevice
uint32_t devid; // device hw fw id
TfaDescPtr_t name; // device name
TfaDescPtr_t list[]; // items list
} TfaDeviceList_t;
/*
* profile descriptor list
*/
typedef struct TfaProfileList {
uint32_t length:8; // nr of items in the list + name
uint32_t group:8; // profile group number
uint32_t ID:16; // profile ID
TfaDescPtr_t name; // profile name
TfaDescPtr_t list[]; // items list (lenght-1 items)
} TfaProfileList_t;
#define TFA_PROFID 0x1234
/*
* livedata descriptor list
*/
typedef struct TfaLiveDataList {
uint32_t length:8; // nr of items in the list
uint32_t ID:24; // profile ID
TfaDescPtr_t name; // livedata name
TfaDescPtr_t list[]; // items list
} TfaLiveDataList_t;
#define TFA_LIVEDATAID 0x5678
/*
* Bitfield descriptor
*/
typedef struct TfaBitfield {
uint16_t value;
uint16_t field; // ==datasheet defined, 16 bits
} TfaBitfield_t;
/*
* Bitfield enumuration bits descriptor
*/
typedef struct TfaBfEnum {
unsigned int len:4; // this is the actual length-1
unsigned int pos:4;
unsigned int address:8;
} TfaBfEnum_t;
/*
* Register patch descriptor
*/
typedef struct TfaRegpatch {
uint8_t address; // register address
uint16_t value; // value to write
uint16_t mask; // mask of bits to write
} TfaRegpatch_t;
/*
* Mode descriptor
*/
typedef struct TfaUseCase {
int value; // mode value, maps to enum Tfa98xx_Mode
} TfaMode_t;
/*
* NoInit descriptor
*/
typedef struct TfaNoInit {
uint8_t value; // noInit value
} TfaNoInit_t;
/*
* Features descriptor
*/
typedef struct TfaFeatures {
uint16_t value[3]; // features value
} TfaFeatures_t;
/*
* the container file
* - the size field is 32bits long (generic=16)
* - all char types are in ASCII
*/
#define TFA_PM_VERSION '1'
#define TFA_PM3_VERSION '3'
#define TFA_PM_SUBVERSION '1'
typedef struct TfaContainer {
char id[2]; // "XX" : XX=type
char version[2]; // "V_" : V=version, vv=subversion
char subversion[2]; // "vv" : vv=subversion
uint32_t size; // data size in bytes following CRC
uint32_t CRC; // 32-bits CRC for following data
uint16_t rev; // "extra chars for rev nr"
char customer[8]; // “name of customer”
char application[8]; // “application name”
char type[8]; // “application type name”
uint16_t ndev; // "nr of device lists"
uint16_t nprof; // "nr of profile lists"
uint16_t nliveData; // "nr of livedata lists"
TfaDescPtr_t index[]; // start of item index table
} TfaContainer_t;
#pragma pack (pop)
#endif /* TFA98XXPARAMETERS_H_ */

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/*
* Copyright (C) 2014-2020 NXP Semiconductors, All Rights Reserved.
* Copyright 2020 GOODIX
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
*/
typedef struct TfaBfName {
unsigned short bfEnum;
char *bfName;
} tfaBfName_t;
typedef struct TfaIrqName {
unsigned short irqEnum;
char *irqName;
} tfaIrqName_t;
#include "tfa1_tfafieldnames.h"
#include "tfa2_tfafieldnames_N1C.h"
/* diffs for specific devices */
#include "tfa9887_tfafieldnames.h"
#include "tfa9890_tfafieldnames.h"
#include "tfa9891_tfafieldnames.h"
#include "tfa9872_tfafieldnames.h"
#include "tfa9912_tfafieldnames.h"
#include "tfa9896_tfafieldnames.h"
#include "tfa9873_tfafieldnames.h"
#include "tfa9873_tfafieldnames_B0.h"
#include "tfa9874_tfafieldnames.h"
#include "tfa9878_tfafieldnames.h"
#include "tfa9894_tfafieldnames.h"
#include "tfa9894_tfafieldnames_N2.h"
/* missing 'common' defs break the build but unused in TFA1 context */
#define TFA1_BF_AMPINSEL -1
#define TFA1_BF_MANSCONF -1
#define TFA1_BF_MANCOLD -1
#define TFA1_BF_INTSMUTE -1
#define TFA1_BF_CFSMR -1
#define TFA1_BF_CFSML -1
#define TFA1_BF_DCMCCAPI -1
#define TFA1_BF_DCMCCSB -1
#define TFA1_BF_USERDEF -1
#define TFA1_BF_MANSTATE -1
#define TFA1_BF_MANOPER -1
#define TFA1_BF_REFCKSEL -1
#define TFA1_BF_VOLSEC -1
#define TFA1_BF_FRACTDEL -1
#define TFA1_BF_ACKDMG -1
#define TFA1_BF_SSRIGHTE -1
#define TFA1_BF_SSLEFTE -1
#define TFA1_BF_R25CL -1
#define TFA1_BF_R25CR -1
#define TFA1_BF_SWPROFIL 0x8045 /*!< profile save */
#define TFA1_BF_SWVSTEP 0x80a5 /*!< vstep save */
/* missing 'common' defs break the build */
#define TFA2_BF_CFSM -1
/* MTP access uses registers
* defs are derived from corresponding bitfield names as used in the BF macros
*/
#define MTPKEY2 MTPK /* unlock key2 MTPK */
#define MTP0 MTPOTC /* MTP data */
#define MTP_CONTROL CIMTP /* copy i2c to mtp */
/* interrupt enable register uses HW name in TFA2 */
#define TFA2_BF_INTENVDDS TFA2_BF_IEVDDS
/* TFA9891 specific bit field names */
#define TFA1_BF_SAAMGAIN 0x2202
#define TFA2_BF_SAAMGAIN -1
/* TFA9872 specific bit field names */
#define TFA2_BF_IELP0 TFA9872_BF_IELP0
#define TFA2_BF_ISTLP0 TFA9872_BF_ISTLP0
#define TFA2_BF_IPOLP0 TFA9872_BF_IPOLP0
#define TFA2_BF_IELP1 TFA9872_BF_IELP1
#define TFA2_BF_ISTLP1 TFA9872_BF_ISTLP1
#define TFA2_BF_IPOLP1 TFA9872_BF_IPOLP1
#define TFA2_BF_LP0 TFA9872_BF_LP0
#define TFA2_BF_LP1 TFA9872_BF_LP1
#define TFA2_BF_R25C TFA9872_BF_R25C
#define TFA2_BF_SAMMODE TFA9872_BF_SAMMODE
/* interrupt bit field names of TFA2 and TFA1 do not match */
#define TFA1_BF_IEACS TFA1_BF_INTENACS
#define TFA1_BF_IPOACS TFA1_BF_INTPOLACS
#define TFA1_BF_ISTACS TFA1_BF_INTOACS
#define TFA1_BF_ISTVDDS TFA1_BF_INTOVDDS
#define TFA1_BF_ICLVDDS TFA1_BF_INTIVDDS
#define TFA1_BF_IPOVDDS TFA1_BF_INTPOLVDDS
#define TFA1_BF_IENOCLK TFA1_BF_INTENNOCLK
#define TFA1_BF_ISTNOCLK TFA1_BF_INTONOCLK
#define TFA1_BF_IPONOCLK TFA1_BF_INTPOLNOCLK
/* interrupt bit fields not available on TFA1 */
#define TFA1_BF_IECLKOOR -1
#define TFA1_BF_ISTCLKOOR -1
#define TFA1_BF_IEMWSRC -1
#define TFA1_BF_ISTMWSRC -1
#define TFA1_BF_IPOMWSRC -1
#define TFA1_BF_IEMWSMU -1
#define TFA1_BF_ISTMWSMU -1
#define TFA1_BF_IPOMWSMU -1
#define TFA1_BF_IEMWCFC -1
#define TFA1_BF_ISTMWCFC -1
#define TFA1_BF_IPOMWCFC -1
#define TFA1_BF_CLKOOR -1
#define TFA1_BF_MANWAIT1 -1
#define TFA1_BF_MANWAIT2 -1
#define TFA1_BF_MANMUTE -1
#define TFA1_BF_IPCLKOOR -1
#define TFA1_BF_ICLCLKOOR -1
#define TFA1_BF_IPOSWS -1
#define TFA1_BF_IESWS -1
#define TFA1_BF_ISTSWS -1
#define TFA1_BF_IESPKS -1
#define TFA1_BF_ISTSPKS -1
#define TFA1_BF_IPOSPKS -1
#define TFA1_BF_IECLKS -1
#define TFA1_BF_ISTCLKS -1
#define TFA1_BF_IPOCLKS -1
#define TFA1_BF_IEAMPS -1
#define TFA1_BF_ISTAMPS -1
#define TFA1_BF_IPOAMPS -1
#define TFA1_BF_IELP0 -1
#define TFA1_BF_ISTLP0 -1
#define TFA1_BF_IPOLP0 -1
#define TFA1_BF_IELP1 -1
#define TFA1_BF_ISTLP1 -1
#define TFA1_BF_IPOLP1 -1
#define TFA1_BF_LP0 -1
#define TFA1_BF_LP1 -1
#define TFA1_BF_R25C -1
#define TFA1_BF_SAMMODE -1
/* TDM STATUS fields not available on TFA1 */
#define TFA1_BF_TDMLUTER -1
#define TFA1_BF_TDMERR -1

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/*
* Copyright (C) 2014-2020 NXP Semiconductors, All Rights Reserved.
* Copyright 2020 GOODIX
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
*/
/*
* tfaContainer.h
*
* Created on: Sep 11, 2013
* Author: wim
*/
#ifndef TFACONTAINER_H_
#define TFACONTAINER_H_
/* static limits */
#define TFACONT_MAXDEVS (4) /* maximum nr of devices */
#define TFACONT_MAXPROFS (16) /* maximum nr of profiles */
#include "tfa98xx_parameters.h"
/**
* Pass the container buffer, initialize and allocate internal memory.
*
* @param cnt pointer to the start of the buffer holding the container file
* @param length of the data in bytes
* @return
* - tfa_error_ok if normal
* - tfa_error_container invalid container data
* - tfa_error_bad_param invalid parameter
*
*/
enum tfa_error tfa_load_cnt(void *cnt, int length);
/**
* Return the descriptor string
* @param cnt pointer to the container struct
* @param dsc pointer to Tfa descriptor
* @return descriptor string
*/
char *tfaContGetString(TfaContainer_t *cnt, TfaDescPtr_t *dsc);
/**
* Gets the string for the given command type number
* @param type number representing a command
* @return string of a command
*/
char *tfaContGetCommandString(uint32_t type);
/**
* get the device type from the patch in this devicelist
* - find the patch file for this devidx
* - return the devid from the patch or 0 if not found
* @param cnt pointer to container file
* @param dev_idx device index
* @return descriptor string
*/
int tfa_cnt_get_devid(TfaContainer_t *cnt, int dev_idx);
/**
* Get the slave for the device if it exists.
* @param tfa the device struct pointer
* @param slave_addr the index of the device
* @return Tfa98xx_Error
*/
enum Tfa98xx_Error tfaContGetSlave(struct tfa_device *tfa, uint8_t *slave_addr);
void tfaContSetSlave(uint8_t slave_addr);
/**
* Get the index for a skave address.
* @param tfa the device struct pointer
* @return the device index
*/
int tfa_cont_get_idx(struct tfa_device *tfa);
/**
* Write reg and bitfield items in the devicelist to the target.
* @param tfa the device struct pointer
* @return Tfa98xx_Error
*/
enum Tfa98xx_Error tfaContWriteRegsDev(struct tfa_device *tfa);
/**
* Write reg and bitfield items in the profilelist to the target.
* @param tfa the device struct pointer
* @param prof_idx the profile index
* @return Tfa98xx_Error
*/
enum Tfa98xx_Error tfaContWriteRegsProf(struct tfa_device *tfa, int prof_idx);
/**
* Write a patchfile in the devicelist to the target.
* @param tfa the device struct pointer
* @return Tfa98xx_Error
*/
enum Tfa98xx_Error tfaContWritePatch(struct tfa_device *tfa);
/**
* Write all param files in the devicelist to the target.
* @param tfa the device struct pointer
* @return Tfa98xx_Error
*/
enum Tfa98xx_Error tfaContWriteFiles(struct tfa_device *tfa);
/**
* Get sample rate from passed profile index
* @param tfa the device struct pointer
* @param prof_idx the index of the profile
* @return sample rate value
*/
unsigned int tfa98xx_get_profile_sr(struct tfa_device *tfa, unsigned int prof_idx);
/**
* Get the device name string
* @param cnt the pointer to the container struct
* @param dev_idx the index of the device
* @return device name string or error string if not found
*/
char *tfaContDeviceName(TfaContainer_t *cnt, int dev_idx);
/**
* Get the application name from the container file application field
* @param tfa the device struct pointer
* @param name the input stringbuffer with size: sizeof(application field)+1
* @return actual string length
*/
int tfa_cnt_get_app_name(struct tfa_device *tfa, char *name);
/**
* Get profile index of the calibration profile
* @param tfa the device struct pointer
* @return profile index, -2 if no calibration profile is found or -1 on error
*/
int tfaContGetCalProfile(struct tfa_device *tfa);
/**
* Is the profile a tap profile ?
* @param tfa the device struct pointer
* @param prof_idx the index of the profile
* @return 1 if the profile is a tap profile or 0 if not
*/
int tfaContIsTapProfile(struct tfa_device *tfa, int prof_idx);
/**
* Get the name of the profile at certain index for a device in the container file
* @param cnt the pointer to the container struct
* @param dev_idx the index of the device
* @param prof_idx the index of the profile
* @return profile name string or error string if not found
*/
char *tfaContProfileName(TfaContainer_t *cnt, int dev_idx, int prof_idx);
/**
* Process all items in the profilelist
* NOTE an error return during processing will leave the device muted
* @param tfa the device struct pointer
* @param prof_idx index of the profile
* @param vstep_idx index of the vstep
* @return Tfa98xx_Error
*/
enum Tfa98xx_Error tfaContWriteProfile(struct tfa_device *tfa, int prof_idx, int vstep_idx);
/**
* Specify the speaker configurations (cmd id) (Left, right, both, none)
* @param dev_idx index of the device
* @param configuration name string of the configuration
*/
void tfa98xx_set_spkr_select(int dev_idx, char *configuration);
enum Tfa98xx_Error tfa_cont_write_filterbank(struct tfa_device *tfa, TfaFilter_t *filter);
/**
* Write all param files in the profilelist to the target
* this is used during startup when maybe ACS is set
* @param tfa the device struct pointer
* @param prof_idx the index of the profile
* @param vstep_idx the index of the vstep
* @return Tfa98xx_Error
*/
enum Tfa98xx_Error tfaContWriteFilesProf(struct tfa_device *tfa, int prof_idx, int vstep_idx);
enum Tfa98xx_Error tfaContWriteFilesVstep(struct tfa_device *tfa, int prof_idx, int vstep_idx);
enum Tfa98xx_Error tfaContWriteDrcFile(struct tfa_device *tfa, int size, uint8_t data[]);
/**
* Get the device list dsc from the tfaContainer
* @param cont pointer to the tfaContainer
* @param dev_idx the index of the device
* @return device list pointer
*/
TfaDeviceList_t *tfaContGetDevList(TfaContainer_t *cont, int dev_idx);
/**
* Get the Nth profile for the Nth device
* @param cont pointer to the tfaContainer
* @param dev_idx the index of the device
* @param prof_idx the index of the profile
* @return profile list pointer
*/
TfaProfileList_t *tfaContGetDevProfList(TfaContainer_t *cont, int dev_idx, int prof_idx);
/**
* Get the number of profiles for device from contaienr
* @param cont pointer to the tfaContainer
* @param dev_idx the index of the device
* @return device list pointer
*/
int tfa_cnt_get_dev_nprof(struct tfa_device *tfa);
/**
* Get the Nth livedata for the Nth device
* @param cont pointer to the tfaContainer
* @param dev_idx the index of the device
* @param livedata_idx the index of the livedata
* @return livedata list pointer
*/
TfaLiveDataList_t *tfaContGetDevLiveDataList(TfaContainer_t *cont, int dev_idx, int livedata_idx);
/**
* Check CRC for container
* @param cont pointer to the tfaContainer
* @return error value 0 on error
*/
int tfaContCrcCheckContainer(TfaContainer_t *cont);
/**
* Get the device list pointer
* @param cnt pointer to the container struct
* @param dev_idx the index of the device
* @return pointer to device list
*/
TfaDeviceList_t *tfaContDevice(TfaContainer_t *cnt, int dev_idx);
/**
* Return the pointer to the first profile in a list from the tfaContainer
* @param cont pointer to the tfaContainer
* @return pointer to first profile in profile list
*/
TfaProfileList_t *tfaContGet1stProfList(TfaContainer_t *cont);
/**
* Return the pointer to the next profile in a list
* @param prof is the pointer to the profile list
* @return profile list pointer
*/
TfaProfileList_t* tfaContNextProfile(TfaProfileList_t *prof);
/**
* Return the pointer to the first livedata in a list from the tfaContainer
* @param cont pointer to the tfaContainer
* @return pointer to first livedata in profile list
*/
TfaLiveDataList_t *tfaContGet1stLiveDataList(TfaContainer_t *cont);
/**
* Return the pointer to the next livedata in a list
* @param livedata_idx is the pointer to the livedata list
* @return livedata list pointer
*/
TfaLiveDataList_t* tfaContNextLiveData(TfaLiveDataList_t *livedata_idx);
/**
* Write a bit field
* @param tfa the device struct pointer
* @param bf bitfield to write
* @return Tfa98xx_Error
*/
enum Tfa98xx_Error tfaRunWriteBitfield(struct tfa_device *tfa, TfaBitfield_t bf);
/**
* Write a parameter file to the device
* @param tfa the device struct pointer
* @param file filedescriptor pointer
* @param vstep_idx index to vstep
* @param vstep_msg_idx index to vstep message
* @return Tfa98xx_Error
*/
enum Tfa98xx_Error tfaContWriteFile(struct tfa_device *tfa, TfaFileDsc_t *file, int vstep_idx, int vstep_msg_idx);
/**
* Get the max volume step associated with Nth profile for the Nth device
* @param tfa the device struct pointer
* @param prof_idx profile index
* @return the number of vsteps
*/
int tfacont_get_max_vstep(struct tfa_device *tfa, int prof_idx);
/**
* Get the file contents associated with the device or profile
* Search within the device tree, if not found, search within the profile
* tree. There can only be one type of file within profile or device.
* @param tfa the device struct pointer
* @param prof_idx I2C profile index in the device
* @param type file type
* @return 0 NULL if file type is not found
* @return 1 file contents
*/
TfaFileDsc_t *tfacont_getfiledata(struct tfa_device *tfa, int prof_idx, enum TfaHeaderType type);
/**
* Dump the contents of the file header
* @param hdr pointer to file header data
*/
void tfaContShowHeader(TfaHeader_t *hdr);
/**
* Read a bit field
* @param tfa the device struct pointer
* @param bf bitfield to read out
* @return Tfa98xx_Error
*/
enum Tfa98xx_Error tfaRunReadBitfield(struct tfa_device *tfa, TfaBitfield_t *bf);
/**
* Get hw feature bits from container file
* @param tfa the device struct pointer
* @param hw_feature_register pointer to where hw features are stored
*/
void get_hw_features_from_cnt(struct tfa_device *tfa, int *hw_feature_register);
/**
* Get sw feature bits from container file
* @param tfa the device struct pointer
* @param sw_feature_register pointer to where sw features are stored
*/
void get_sw_features_from_cnt(struct tfa_device *tfa, int sw_feature_register[2]);
/**
* Factory trimming for the Boost converter
* check if there is a correction needed
* @param tfa the device struct pointer
*/
enum Tfa98xx_Error tfa98xx_factory_trimmer(struct tfa_device *tfa);
/**
* Search for filters settings and if found then write them to the device
* @param tfa the device struct pointer
* @param prof_idx profile to look in
* @return Tfa98xx_Error
*/
enum Tfa98xx_Error tfa_set_filters(struct tfa_device *tfa, int prof_idx);
/**
* Get the firmware version from the patch in the container file
* @param tfa the device struct pointer
* @return firmware version
*/
int tfa_cnt_get_patch_version(struct tfa_device *tfa);
int tfa_tib_dsp_msgmulti(struct tfa_device *tfa, int length, const char *buffer);
#endif /* TFACONTAINER_H_ */

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/*
* Copyright (C) 2014-2020 NXP Semiconductors, All Rights Reserved.
* Copyright 2020 GOODIX
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
*/
/**\file
*
* The tfa_device interface controls a single I2C device instance by
* referencing to the device specific context provided by means of the
* tfa_device structure pointer.
* Multiple instances of tfa_device structures will be created and maintained
* by the caller.
*
* The API is functionally grouped as:
* - tfa_dev basic codec interface to probe, start/stop and control the device state
* - access to internal MTP storage
* - abstraction for interrupt bits and handling
* - container reading support
*/
#ifndef __TFA_DEVICE_H__
#define __TFA_DEVICE_H__
#include "config.h"
struct tfa_device;
/*
* hw/sw feature bit settings in MTP
*/
enum featureSupport {
supportNotSet, /**< default means not set yet */
supportNo, /**< no support */
supportYes /**< supported */
};
/*
* supported Digital Audio Interfaces bitmap
*/
enum Tfa98xx_DAI {
Tfa98xx_DAI_I2S = 0x01, /**< I2S only */
Tfa98xx_DAI_TDM = 0x02, /**< TDM, I2S */
Tfa98xx_DAI_PDM = 0x04, /**< PDM */
};
/*
* device ops function structure
*/
struct tfa_device_ops {
enum Tfa98xx_Error(*dsp_msg)(struct tfa_device *tfa, int length, const char *buf);
enum Tfa98xx_Error(*dsp_msg_read)(struct tfa_device *tfa, int length, unsigned char *bytes);
enum Tfa98xx_Error(*reg_read)(struct tfa_device *tfa, unsigned char subaddress, unsigned short *value);
enum Tfa98xx_Error(*reg_write)(struct tfa_device *tfa, unsigned char subaddress, unsigned short value);
enum Tfa98xx_Error(*mem_read)(struct tfa_device *tfa, unsigned int start_offset, int num_words, int *pValues);
enum Tfa98xx_Error(*mem_write)(struct tfa_device *tfa, unsigned short address, int value, int memtype);
enum Tfa98xx_Error (*tfa_init)(struct tfa_device *tfa); /**< init typically for loading optimal settings */
enum Tfa98xx_Error (*dsp_reset)(struct tfa_device *tfa, int state); /**< reset the coolflux dsp */
enum Tfa98xx_Error (*dsp_system_stable)(struct tfa_device *tfa, int *ready); /**< ready when clocks are stable to allow DSP subsystem access */
enum Tfa98xx_Error (*dsp_write_tables)(struct tfa_device *tfa, int sample_rate); /**< write the device/type specific delaytables */
enum Tfa98xx_Error (*auto_copy_mtp_to_iic)(struct tfa_device *tfa); /**< Set auto_copy_mtp_to_iic */
enum Tfa98xx_Error (*factory_trimmer)(struct tfa_device *tfa); /**< Factory trimming for the Boost converter */
int (*set_swprof)(struct tfa_device *tfa, unsigned short new_value); /**< Set the sw profile in the struct and the hw register */
int (*get_swprof)(struct tfa_device *tfa); /**< Get the sw profile from the hw register */
int(*set_swvstep)(struct tfa_device *tfa, unsigned short new_value); /**< Set the sw vstep in the struct and the hw register */
int(*get_swvstep)(struct tfa_device *tfa); /**< Get the sw vstep from the hw register */
int(*get_mtpb)(struct tfa_device *tfa); /**< get status of MTB busy bit*/
enum Tfa98xx_Error (*set_mute)(struct tfa_device *tfa, int mute); /**< set mute */
enum Tfa98xx_Error (*faim_protect)(struct tfa_device *tfa, int state); /**< Protect FAIM from being corrupted */
enum Tfa98xx_Error(*set_osc_powerdown)(struct tfa_device *tfa, int state); /**< Allow to change internal osc. gating settings */
enum Tfa98xx_Error(*update_lpm)(struct tfa_device *tfa, int state); /**< Allow to change lowpowermode settings */
};
/**
* Device states and modifier flags to allow a device/type independent fine
* grained control of the internal state.\n
* Values below 0x10 are referred to as base states which can be or-ed with
* state modifiers, from 0x10 and higher.
*
*/
enum tfa_state {
TFA_STATE_UNKNOWN, /**< unknown or invalid */
TFA_STATE_POWERDOWN, /**< PLL in powerdown, Algo is up/warm */
TFA_STATE_INIT_HW, /**< load I2C/PLL hardware setting (~wait2srcsettings) */
TFA_STATE_INIT_CF, /**< coolflux HW access possible (~initcf) */
TFA_STATE_INIT_FW, /**< DSP framework active (~patch loaded) */
TFA_STATE_OPERATING, /**< Amp and Algo running */
TFA_STATE_FAULT, /**< An alarm or error occurred */
TFA_STATE_RESET, /**< I2C reset and ACS set */
/* --sticky state modifiers-- */
TFA_STATE_MUTE=0x10, /**< Algo & Amp mute */
TFA_STATE_UNMUTE=0x20, /**< Algo & Amp unmute */
TFA_STATE_CLOCK_ALWAYS=0x40, /**< PLL connect to internal oscillator */
TFA_STATE_CLOCK_AUDIO=0x80, /**< PLL connect to audio clock (BCK/FS) */
TFA_STATE_LOW_POWER=0x100, /**< lowest possible power state */
};
/**
* This is the main tfa device context structure, it will carry all information
* that is needed to handle a single I2C device instance.
* All functions dealing with the device will need access to the fields herein.
*/
struct tfa_device {
int dev_idx; /**< device container index */
int in_use;
int buffer_size; /**< lowest level max buffer size */
int has_msg; /**< support direct dsp messaging */
int dynamicTDMmode; /**tracking dynamic TDM setting from alsa input stream*/
int bitwidth; /**bitwdith from alsa input stream*/
unsigned char slave_address; /**< I2C slave address (not shifted) */
unsigned short rev; /**< full revid of this device */
unsigned char tfa_family; /**< tfa1/tfa2 */
enum featureSupport supportDrc;
enum featureSupport supportFramework;
enum featureSupport support_saam;
int sw_feature_bits[2]; /**< cached copy of sw feature bits */
int hw_feature_bits; /**< cached copy of hw feature bits */
int profile; /**< active profile */
int vstep; /**< active vstep */
unsigned char spkr_count;
unsigned char spkr_select;
unsigned char support_tcoef;/**< legacy tfa9887, will be removed */
enum Tfa98xx_DAI daimap; /**< supported audio interface types */
int mohm[3]; /**< speaker calibration values in milli ohms -1 is error */
struct tfa_device_ops dev_ops;
uint16_t interrupt_enable[3];
uint16_t interrupt_status[3];
int ext_dsp; /**< respond to external DSP: -1:none, 0:no_dsp, 1:cold, 2:warm */
int bus; /* TODO fix ext_dsp and bus handling */
int tfadsp_event; /**< enum tfadsp_event_en is for external registry */
int verbose; /**< verbosity level for debug print output */
enum tfa_state state; /**< last known state or-ed with optional state_modifier */
struct TfaContainer *cnt;/**< the loaded container file */
struct TfaVolumeStepRegisterInfo *p_regInfo; /**< remember vstep for partial updates */
int partial_enable; /**< enable partial updates */
void *data; /**< typically pointing to Linux driver structure owning this device */
int convert_dsp32; /**< convert 24 bit DSP messages to 32 bit */
int sync_iv_delay; /**< synchronize I/V delay at cold start */
int is_probus_device; /**< probus device: device without internal DSP */
int advance_keys_handling;
int needs_reset; /**< add the reset trigger for SetAlgoParams and SetMBDrc commands */
struct kmem_cache *cachep; /**< Memory allocator handle */
char fw_itf_ver[4]; /* Firmware ITF version */
};
/**
* The tfa_dev_probe is called before accessing any device accessing functions.
* Access to the tfa device register 3 is attempted and will record the
* returned id for further use. If no device responds the function will abort.
* The recorded id will by used by the query functions to fill the remaining
* relevant data fields of the device structure.
* Data such as MTP features that requires device access will only be read when
* explicitly called and the result will be then cached in the struct.
*
* A structure pointer passed to this device needs to refer to existing memory
* space allocated by the caller.
*
* @param slave = I2C slave address of the target device (not shifted)
* @param tfa struct = points to memory that holds the context for this device
* instance
*
* @return
* - 0 if the I2C device responded to a read of register address 3\n
* when the device responds but with an unknown id a warning will be printed
* - -1 if no response from the I2C device
*
*/
int tfa_dev_probe(int slave, struct tfa_device *tfa);
/**
* Start this instance at the profile and vstep as provided.
* The profile and vstep will be loaded first in case the current value differs
* from the requested values.
* Note that this call will not change the mute state of the tfa, which means
* that of this instance was called in muted state the caller will have to
* unmute in order to get audio.
*
* @param tfa struct = pointer to context of this device instance
* @param profile the selected profile to run
* @param vstep the selected vstep to use
* @return tfa_error enum
*/
enum tfa_error tfa_dev_start(struct tfa_device *tfa, int profile, int vstep);
/**
* Stop audio for this instance as gracefully as possible.
* Audio will be muted and the PLL will be shutdown together with any other
* device/type specific settings needed to prevent audio artifacts or
* workarounds.
*
* Note that this call will change state of the tfa to mute and powered down.
*
* @param tfa struct = pointer to context of this device instance
* @return tfa_error enum
*/
enum tfa_error tfa_dev_stop(struct tfa_device *tfa);
/**
* This interface allows a device/type independent fine grained control of the
* internal state of the instance.
* Whenever a base state is requested an attempt is made to actively bring the device
* into this state. However this may depend on external conditions beyond control of
* this software layer. Therefore in case the state cannot be set an erro will
* be returned and the current state remains unchanged.
* The base states, lower values below 0x10, are all mutually exclusive, they higher ones
* can also function as a sticky modifier which means for example that operating
* state could be in either muted or unmuted state. Or in case of init_cf it can be
* internal clock (always) or external audio clock.
* This function is intended to be used for device mute/unmute synchronization
* when called from higher layers. Mostly internal calls will use this to control
* the startup and profile transitions in a device/type independent way.
*
* @param tfa struct = pointer to context of this device instance
* @param state struct = desired device state after function return
* @return tfa_error enum
*/
enum tfa_error tfa_dev_set_state(struct tfa_device *tfa, enum tfa_state state,int is_calibration);
/**
* Retrieve the current state of this instance in an active way.
* The state field in tfa structure will reflect the result unless an error is
* returned.
* Note that the hardware state may change on external events an as such this
* field should be treated as volatile.
*
* @param tfa struct = pointer to context of this device instance
* @return tfa_error enum
*
*/
enum tfa_state tfa_dev_get_state(struct tfa_device *tfa);
/**
* Deduce the width from machine driver and decide TDM setting to be
* programmed to the TFA amplifier dynamically
* @param tfa struct = pointer to context of this device instance
* @param width = parmeters read from top layer to decide the applicable TDM settings
* @return tfa_error enum
- 0 if the width received is correct (16/32/24)
* - others if width received is not correct
*/
int tfa_dev_set_tdm_bitwidth(struct tfa_device *tfa, int width);
/*****************************************************************************/
/*****************************************************************************/
/**
* MTP support functions
*/
enum tfa_mtp {
TFA_MTP_OTC, /**< */
TFA_MTP_EX, /**< */
TFA_MTP_RE25, /**< */
TFA_MTP_RE25_PRIM, /**< */
TFA_MTP_RE25_SEC, /**< */
TFA_MTP_LOCK, /**< */
};
/**
*
*/
int tfa_dev_mtp_get(struct tfa_device *tfa, enum tfa_mtp item);
/**
*
*/
enum tfa_error tfa_dev_mtp_set(struct tfa_device *tfa, enum tfa_mtp item, int value);
//irq
/* tfa2 interrupt support
* !!! enum tfa9912_irq !!!*/
/*
* interrupt bit function to clear
*/
int tfa_irq_clear(struct tfa_device *tfa, int bit);
/*
* return state of irq or -1 if illegal bit
*/
int tfa_irq_get(struct tfa_device *tfa, int bit);
/*
* interrupt bit function that operates on the shadow regs in the handle
*/
int tfa_irq_ena(struct tfa_device *tfa, int bit, int state);
/*
* interrupt bit function that sets the polarity
*/
int tfa_irq_set_pol(struct tfa_device *tfa, int bit, int state);
/*
* mask interrupts by disabling them
*/
int tfa_irq_mask(struct tfa_device *tfa);
/*
* unmask interrupts by enabling them again
*/
int tfa_irq_unmask(struct tfa_device *tfa);
//cnt read
//debug?
/* IRQ handle for tfa987x device */
int tfa987x_irq_enable(struct tfa_device *tfa, int bit, int status);
void tfa987x_irq_mask(struct tfa_device *tfa);
void tfa987x_irq_unmask(struct tfa_device *tfa);
int tfa987x_irq_clear(struct tfa_device *tfa, int bit);
int tfa987x_irq_handle(struct tfa_device *tfa);
#endif /* __TFA_DEVICE_H__ */

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/*
* Copyright (C) 2014-2020 NXP Semiconductors, All Rights Reserved.
* Copyright 2020 GOODIX
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
*/
#ifndef TFA98XX_INTERNALS_H
#define TFA98XX_INTERNALS_H
#include "config.h"
#include "tfa_service.h" //TODO cleanup for enum Tfa98xx_Status_ID
/*
* tfadsp_fw_api.c
*/
/**
* Return a text version of the firmware status ID code
* @param status the given status ID code
* @return the firmware status ID string
*/
const char *tfadsp_fw_status_string(enum Tfa98xx_Status_ID status);
int tfadsp_fw_start(struct tfa_device *tfa, int prof_idx, int vstep_idx);
int tfadsp_fw_get_api_version(struct tfa_device *tfa, uint8_t *buffer);
#define FW_MAXTAG 150
int tfadsp_fw_get_tag(struct tfa_device *tfa, uint8_t *buffer);
int tfadsp_fw_get_status_change(struct tfa_device *tfa, uint8_t *buffer);
int tfadsp_fw_set_re25(struct tfa_device *tfa, int prim, int sec );
int tfadsp_fw_get_re25(struct tfa_device *tfa, uint8_t *buffer);
/*
* the order matches the ACK bits order in TFA98XX_CF_STATUS
*/
enum tfa_fw_event { /* not all available on each device */
tfa_fw_i2c_cmd_ack,
tfa_fw_reset_start,
tfa_fw_short_on_mips,
tfa_fw_soft_mute_ready,
tfa_fw_volume_ready,
tfa_fw_error_damage,
tfa_fw_calibrate_done,
tfa_fw_max
};
/* the following type mappings are compiler specific */
#define subaddress_t unsigned char
/* module Ids */
#define MODULE_FRAMEWORK 0
#define MODULE_SPEAKERBOOST 1
#define MODULE_BIQUADFILTERBANK 2
#define MODULE_TAPTRIGGER 5
#define MODULE_SETRE 9
/* RPC commands */
/* SET */
#define FW_PAR_ID_SET_MEMORY 0x03
#define FW_PAR_ID_SET_SENSES_DELAY 0x04
#define FW_PAR_ID_SETSENSESCAL 0x05
#define FW_PAR_ID_SET_INPUT_SELECTOR 0x06
#define FW_PAR_ID_SET_OUTPUT_SELECTOR 0x08
#define FW_PAR_ID_SET_PROGRAM_CONFIG 0x09
#define FW_PAR_ID_SET_GAINS 0x0A
#define FW_PAR_ID_SET_MEMTRACK 0x0B
#define FW_PAR_ID_SET_FWKUSECASE 0x11
#define TFA1_FW_PAR_ID_SET_CURRENT_DELAY 0x03
#define TFA1_FW_PAR_ID_SET_CURFRAC_DELAY 0x06
/* GET */
#define FW_PAR_ID_GET_MEMORY 0x83
#define FW_PAR_ID_GLOBAL_GET_INFO 0x84
#define FW_PAR_ID_GET_FEATURE_INFO 0x85
#define FW_PAR_ID_GET_MEMTRACK 0x8B
#define FW_PAR_ID_GET_TAG 0xFF
#define FW_PAR_ID_GET_API_VERSION 0xFE
#define FW_PAR_ID_GET_STATUS_CHANGE 0x8D
/* Load a full model into SpeakerBoost. */
/* SET */
#define SB_PARAM_SET_ALGO_PARAMS 0x00
#define SB_PARAM_SET_LAGW 0x01
#define SB_PARAM_SET_ALGO_PARAMS_WITHOUT_RESET 0x02
#define SB_PARAM_SET_RE25C 0x05
#define SB_PARAM_SET_LSMODEL 0x06
#define SB_PARAM_SET_MBDRC 0x07
#define SB_PARAM_SET_MBDRC_WITHOUT_RESET 0x08
#define SB_PARAM_SET_EXCURSION_FILTERS 0x0A
#define SB_PARAM_SET_DRC 0x0F
/* GET */
#define SB_PARAM_GET_ALGO_PARAMS 0x80
#define SB_PARAM_GET_LAGW 0x81
#define SB_PARAM_GET_RE25C 0x85
#define SB_PARAM_GET_LSMODEL 0x86
#define SB_PARAM_GET_MBDRC 0x87
#define SB_PARAM_GET_MBDRC_DYNAMICS 0x89
#define SB_PARAM_GET_EXCURSION_FILTERS 0x8A
#define SB_PARAM_GET_TAG 0xFF
#define SB_PARAM_SET_EQ 0x0A /* 2 Equaliser Filters. */
#define SB_PARAM_SET_PRESET 0x0D /* Load a preset */
#define SB_PARAM_SET_CONFIG 0x0E /* Load a config */
#define SB_PARAM_SET_AGCINS 0x10
#define SB_PARAM_SET_CURRENT_DELAY 0x03
#define SB_PARAM_GET_STATE 0xC0
#define SB_PARAM_GET_XMODEL 0xC1 /* Gets current Excursion Model. */
#define SB_PARAM_GET_XMODEL_COEFFS 0x8C /* Get coefficients for XModel */
#define SB_PARAM_GET_EXCURSION_FILTERS 0x8A /* Get excursion filters */
#define SB_PARAM_SET_EXCURSION_FILTERS 0x0A /* Set excursion filters */
/* SET: TAPTRIGGER */
#define TAP_PARAM_SET_ALGO_PARAMS 0x01
#define TAP_PARAM_SET_DECIMATION_PARAMS 0x02
/* GET: TAPTRIGGER*/
#define TAP_PARAM_GET_ALGO_PARAMS 0x81
#define TAP_PARAM_GET_TAP_RESULTS 0x84
/* sets the speaker calibration impedance (@25 degrees celsius) */
#define SB_PARAM_SET_RE0 0x89
#define BFB_PAR_ID_SET_COEFS 0x00
#define BFB_PAR_ID_GET_COEFS 0x80
#define BFB_PAR_ID_GET_CONFIG 0x81
/* for compatibility */
#define FW_PARAM_GET_STATE FW_PAR_ID_GLOBAL_GET_INFO
#define FW_PARAM_GET_FEATURE_BITS FW_PAR_ID_GET_FEATURE_BITS
/* RPC Status results */
#define STATUS_OK 0
#define STATUS_INVALID_MODULE_ID 2
#define STATUS_INVALID_PARAM_ID 3
#define STATUS_INVALID_INFO_ID 4
/* the maximum message length in the communication with the DSP */
#define TFA2_MAX_PARAM_SIZE (507*3) /* TFA2 */
#define TFA1_MAX_PARAM_SIZE (145*3) /* TFA1 */
#define ROUND_DOWN(a,n) (((a)/(n))*(n))
/* feature bits */
#define FEATURE1_TCOEF 0x100 /* bit8 set means tCoefA expected */
#define FEATURE1_DRC 0x200 /* bit9 NOT set means DRC expected */
/* DSP firmware xmem defines */
#define TFA1_FW_XMEM_CALIBRATION_DONE 231
#define TFA2_FW_XMEM_CALIBRATION_DONE 516
#define TFA1_FW_XMEM_COUNT_BOOT 0xa1
#define TFA2_FW_XMEM_COUNT_BOOT 512
#define TFA2_FW_XMEM_CMD_COUNT 520
/* note that the following defs rely on the handle variable */
#define TFA_FW_XMEM_CALIBRATION_DONE TFA_FAM_FW(tfa,XMEM_CALIBRATION_DONE)
#define TFA_FW_XMEM_COUNT_BOOT TFA_FAM_FW(tfa,XMEM_COUNT_BOOT)
#define TFA_FW_XMEM_CMD_COUNT TFA_FAM_FW(tfa,XMEM_CMD_COUNT)
#define TFA2_FW_ReZ_SCALE 65536
#define TFA1_FW_ReZ_SCALE 16384
#endif /* TFA98XX_INTERNALS_H */

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/*
* Copyright (C) 2014-2020 NXP Semiconductors, All Rights Reserved.
* Copyright 2020 GOODIX
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
*/
/*
* tfa_ext.h
*
* Created on: Jun 8, 2016
* Author: wim
*/
#ifndef TFA_SRC_TFA_EXT_H_
#define TFA_SRC_TFA_EXT_H_
#include "tfa_device.h"
/*
* events
*/
/** Maximum value for enumerator */
#define LVM_MAXENUM (0xffff)
/**
This enum type specifies the different events that may trigger a callback.
*/
enum tfadsp_event_en
{
TFADSP_CMD_ACK = 1, /**< Command handling is completed */
TFADSP_SOFT_MUTE_READY = 8, /**< Muting completed */
TFADSP_VOLUME_READY = 16, /**< Volume change completed */
TFADSP_DAMAGED_SPEAKER = 32, /**< Damaged speaker was detected */
TFADSP_CALIBRATE_DONE = 64, /**< Calibration is completed */
TFADSP_SPARSESIG_DETECTED = 128, /**< Sparse signal detected */
TFADSP_CMD_READY = 256, /**< Ready to receive commands */
TFADSP_EXT_PWRUP = 0x8000,/**< DSP API has started, powered up */
TFADSP_EXT_PWRDOWN = 0x8001,/**< DSP API stopped, power down */
TFADSP_EVENT_DUMMY = LVM_MAXENUM
} ;
typedef int (*tfa_event_handler_t)(struct tfa_device *tfa, enum tfadsp_event_en tfadsp_event);
typedef int (*dsp_send_message_t)(struct tfa_device *tfa, int length, const char *buf);
typedef int (*dsp_read_message_t)(struct tfa_device *tfa, int length, char *buf);
typedef int (*dsp_write_reg_t)(struct tfa_device *tfa, unsigned char subaddress, unsigned short value);
int tfa_ext_register(dsp_write_reg_t tfa_write_reg, dsp_send_message_t tfa_send_message, dsp_read_message_t tfa_read_message, tfa_event_handler_t *tfa_event_handler);
#endif /* TFA_SRC_TFA_EXT_H_ */

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/*
* Copyright (C) 2014-2020 NXP Semiconductors, All Rights Reserved.
* Copyright 2020 GOODIX
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
*/
/*
internal functions for TFA layer (not shared with SRV and HAL layer!)
*/
#ifndef __TFA_INTERNAL_H__
#define __TFA_INTERNAL_H__
#include "tfa_dsp_fw.h"
#include "tfa_ext.h"
#if __GNUC__ >= 4
#define TFA_INTERNAL __attribute__ ((visibility ("hidden")))
#else
#define TFA_INTERNAL
#endif
#define TFA98XX_GENERIC_SLAVE_ADDRESS 0x1C
TFA_INTERNAL enum Tfa98xx_Error tfa98xx_check_rpc_status(struct tfa_device *tfa, int *pRpcStatus);
TFA_INTERNAL enum Tfa98xx_Error tfa98xx_wait_result(struct tfa_device *tfa, int waitRetryCount);
#endif /* __TFA_INTERNAL_H__ */

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/*
* Copyright 2015-2018 NXP Semiconductors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#ifndef _TFA_PLATFORM_INTERFACE_DEFINITION_H_
#define _TFA_PLATFORM_INTERFACE_DEFINITION_H_
#define AFE_MODULE_ID_TFADSP_RX (0x1000B911)
#define AFE_MODULE_ID_TFADSP_TX (0x1000B912)
#define AFE_PARAM_ID_TFADSP_TX_SET_ENABLE (0x1000B920)
#define AFE_PARAM_ID_TFADSP_RX_CFG (0x1000B921)
#define AFE_PARAM_ID_TFADSP_RX_GET_RESULT (0x1000B922)
#define AFE_PARAM_ID_TFADSP_RX_SET_BYPASS (0x1000B923)
#if defined(CONFIG_TARGET_PRODUCT_LISA)
#define TFA_USING_PRIMARY_TDM
#else
#define TFA_USING_TERTIARY_MI2S
#endif
#if defined(TFA_USING_PRIMARY_TDM)
/*Attention: port_id = AFE_PORT_ID_SECONDARY_MI2S_RX/TX, AFE_PORT_ID_TERTIARY_MI2S_RX/TX,
AFE_PORT_ID_QUATERNARY_MI2S_RX/TX or AFE_PORT_ID_QUINARY_MI2S_RX/TX*/
#define AFE_PORT_ID_TFADSP_RX (AFE_PORT_ID_PRIMARY_TDM_RX)
#define AFE_PORT_ID_TFADSP_TX (AFE_PORT_ID_PRIMARY_TDM_TX)
#define PLATFORM_TDM_RX_VI_FB_RX_MUX_TEXT "PRI_TDM_RX_0"
#define PLATFORM_TDM_RX_VI_FB_TX_MUX_TEXT "PRI_TDM_TX_0"
#define PLATFORM_TDM_RX_VI_FB_MUX_NAME "PRI_TDM_RX_VI_FB_MUX"
#define PLATFORM_TDM_RX_VI_FB_TX_VALUE MSM_BACKEND_DAI_PRI_TDM_TX_0
#define PLATFORM_TDM_RX_VI_FB_MUX_ENUM MSM_BACKEND_DAI_PRI_TDM_RX_0
#define TFA_TX_HOSTLESS_CODEC_NAME "PRI_TDM_TX_0_HOSTLESS"
#define TFA_TX_HOSTLESS_STREAM_NAME "Primary TDM0 Hostless Capture"
#define TFA_TX_HOSTLESS_CPU_DAI_NAME "PRI_TDM_TX_0_HOSTLESS"
#elif defined(TFA_USING_PRIMARY_MI2S)
/*Attention: port_id = AFE_PORT_ID_SECONDARY_MI2S_RX/TX, AFE_PORT_ID_TERTIARY_MI2S_RX/TX,
AFE_PORT_ID_QUATERNARY_MI2S_RX/TX or AFE_PORT_ID_QUINARY_MI2S_RX/TX*/
#define AFE_PORT_ID_TFADSP_RX (AFE_PORT_ID_PRIMARY_MI2S_RX)
#define AFE_PORT_ID_TFADSP_TX (AFE_PORT_ID_PRIMARY_MI2S_TX)
#define PLATFORM_RX_VI_FB_RX_MUX_TEXT "PRI_MI2S_RX"
#define PLATFORM_RX_VI_FB_TX_MUX_TEXT "PRI_MI2S_TX"
#define PLATFORM_RX_VI_FB_MUX_NAME "PRI_MI2S_RX_VI_FB_MUX"
#define PLATFORM_RX_VI_FB_TX_VALUE MSM_BACKEND_DAI_PRI_MI2S_TX
#define PLATFORM_RX_VI_FB_MUX_ENUM MSM_BACKEND_DAI_PRI_MI2S_RX
#define TFA_TX_HOSTLESS_CODEC_NAME "Primary MI2S_TX Hostless"
#define TFA_TX_HOSTLESS_STREAM_NAME "Primary MI2S_TX Hostless"
#define TFA_TX_HOSTLESS_CPU_DAI_NAME "PRI_MI2S_TX_HOSTLESS"
#elif defined(TFA_USING_SECONDARY_MI2S)
/*Attention: port_id = AFE_PORT_ID_SECONDARY_MI2S_RX/TX, AFE_PORT_ID_TERTIARY_MI2S_RX/TX,
AFE_PORT_ID_QUATERNARY_MI2S_RX/TX or AFE_PORT_ID_QUINARY_MI2S_RX/TX*/
#define AFE_PORT_ID_TFADSP_RX (AFE_PORT_ID_SECONDARY_MI2S_RX)
#define AFE_PORT_ID_TFADSP_TX (AFE_PORT_ID_SECONDARY_MI2S_TX)
#define PLATFORM_RX_VI_FB_RX_MUX_TEXT "SEC_MI2S_RX"
#define PLATFORM_RX_VI_FB_TX_MUX_TEXT "SEC_MI2S_TX"
#define PLATFORM_RX_VI_FB_MUX_NAME "SECONDARY_MI2S_RX_VI_FB_MUX"
#define PLATFORM_RX_VI_FB_TX_VALUE MSM_BACKEND_DAI_SECONDARY_MI2S_TX
#define PLATFORM_RX_VI_FB_MUX_ENUM MSM_BACKEND_DAI_SECONDARY_MI2S_RX
#define TFA_TX_HOSTLESS_CODEC_NAME "Secondary MI2S_TX Hostless"
#define TFA_TX_HOSTLESS_STREAM_NAME "Secondary MI2S_TX Hostless"
#define TFA_TX_HOSTLESS_CPU_DAI_NAME "SEC_MI2S_TX_HOSTLESS"
#elif defined(TFA_USING_TERTIARY_MI2S)
/*Attention: port_id = AFE_PORT_ID_SECONDARY_MI2S_RX/TX, AFE_PORT_ID_TERTIARY_MI2S_RX/TX,
AFE_PORT_ID_QUATERNARY_MI2S_RX/TX or AFE_PORT_ID_QUINARY_MI2S_RX/TX*/
#define AFE_PORT_ID_TFADSP_RX (AFE_PORT_ID_TERTIARY_MI2S_RX)
#define AFE_PORT_ID_TFADSP_TX (AFE_PORT_ID_TERTIARY_MI2S_TX)
#define PLATFORM_RX_VI_FB_RX_MUX_TEXT "TERT_MI2S_RX"
#define PLATFORM_RX_VI_FB_TX_MUX_TEXT "TERT_MI2S_TX"
#define PLATFORM_RX_VI_FB_MUX_NAME "TERTIARY_MI2S_RX_VI_FB_MUX"
#define PLATFORM_RX_VI_FB_TX_VALUE MSM_BACKEND_DAI_TERTIARY_MI2S_TX
#define PLATFORM_RX_VI_FB_MUX_ENUM MSM_BACKEND_DAI_TERTIARY_MI2S_RX
#define TFA_TX_HOSTLESS_CODEC_NAME "Tertiary MI2S_TX Hostless"
#define TFA_TX_HOSTLESS_STREAM_NAME "Tertiary MI2S_TX Hostless"
#define TFA_TX_HOSTLESS_CPU_DAI_NAME "TERT_MI2S_TX_HOSTLESS"
#elif defined(TFA_USING_QUATERNARY_MI2S)
/*Attention: port_id = AFE_PORT_ID_SECONDARY_MI2S_RX/TX, AFE_PORT_ID_TERTIARY_MI2S_RX/TX,
AFE_PORT_ID_QUATERNARY_MI2S_RX/TX or AFE_PORT_ID_QUINARY_MI2S_RX/TX*/
#define AFE_PORT_ID_TFADSP_RX (AFE_PORT_ID_QUATERNARY_MI2S_RX)
#define AFE_PORT_ID_TFADSP_TX (AFE_PORT_ID_QUATERNARY_MI2S_TX)
#define PLATFORM_RX_VI_FB_RX_MUX_TEXT "QUAT_MI2S_RX"
#define PLATFORM_RX_VI_FB_TX_MUX_TEXT "QUAT_MI2S_TX"
#define PLATFORM_RX_VI_FB_MUX_NAME "QUATERNARY_MI2S_RX_VI_FB_MUX"
#define PLATFORM_RX_VI_FB_TX_VALUE MSM_BACKEND_DAI_QUATERNARY_MI2S_TX
#define PLATFORM_RX_VI_FB_MUX_ENUM MSM_BACKEND_DAI_QUATERNARY_MI2S_RX
#define TFA_TX_HOSTLESS_CODEC_NAME "Quaternary MI2S_TX Hostless"
#define TFA_TX_HOSTLESS_STREAM_NAME "Quaternary MI2S_TX Hostless"
#define TFA_TX_HOSTLESS_CPU_DAI_NAME "QUAT_MI2S_TX_HOSTLESS"
#elif defined(TFA_USING_QUINARY_MI2S)
/*Attention: port_id = AFE_PORT_ID_SECONDARY_MI2S_RX/TX, AFE_PORT_ID_TERTIARY_MI2S_RX/TX,
AFE_PORT_ID_QUATERNARY_MI2S_RX/TX or AFE_PORT_ID_QUINARY_MI2S_RX/TX*/
#define AFE_PORT_ID_TFADSP_RX (AFE_PORT_ID_QUINARY_MI2S_RX)
#define AFE_PORT_ID_TFADSP_TX (AFE_PORT_ID_QUINARY_MI2S_TX)
#define PLATFORM_RX_VI_FB_RX_MUX_TEXT "QUIN_MI2S_RX"
#define PLATFORM_RX_VI_FB_TX_MUX_TEXT "QUIN_MI2S_TX"
#define PLATFORM_RX_VI_FB_MUX_NAME "QUINARY_MI2S_RX_VI_FB_MUX"
#define PLATFORM_RX_VI_FB_TX_VALUE MSM_BACKEND_DAI_QUINARY_MI2S_TX
#define PLATFORM_RX_VI_FB_MUX_ENUM MSM_BACKEND_DAI_QUINARY_MI2S_RX
#define TFA_TX_HOSTLESS_CODEC_NAME "Quinary MI2S_TX Hostless"
#define TFA_TX_HOSTLESS_STREAM_NAME "Quinary MI2S_TX Hostless"
#define TFA_TX_HOSTLESS_CPU_DAI_NAME "QUIN_MI2S_TX_HOSTLESS"
#else
#error you should define which mi2s will be used for TFA device.
#endif
#endif /* _TFA_PLATFORM_INTERFACE_DEFINITION_H_ */

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#ifndef _VERSIONS_H
#define TFA98XX_GIT_VERSIONS "v6.5.2_xxxxxxxxxx"
#define _VERSIONS_H
#endif

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